A Low Power Folded Mixer for UWB System Applications in 0.18-μm CMOS Technology

This letter presents a wideband mixer using a commercial 0.18-mum CMOS technology process for ultra-wideband (UWB) system applications. To achieve wideband frequency response and low dc power consumption for UWB system applications, the folded approach is utilized to reduce supply voltage as well as dc power consumption, and wideband input matching network is used to achieve wideband frequency response. The measured results show that the proposed mixer demonstrates a wideband frequency response from 0.2 to 16GHz with a conversion gain of better than 5.3dB. The dc power consumption is 15mW under a supply voltage of 1.8V, with a compact size of 0.68mmtimes0.65mm     

A Ku-Band Frequency Synthesizer in 0.18-μm CMOS Technology

This letter presents a fully integrated frequency synthesizer implemented in a 0.18-mum foundry CMOS process. By employing a modified differential Colpitts voltage controlled oscillator to improve the tuning range and the phase noise, the integer-N frequency synthesizer demonstrates an output frequency from 14.8 to 16.9GHz, allowing wideband operations at Ku-band. Operated at an output frequency of 15GHz, the proposed synthesizer exhibits a reference sideband power of -50dBc and a phase noise of -104.5dBc/Hz at 1-MHz offset. The fabricated circuit consumes a dc power of 70mW from a 2-V supply voltage     

Millimeter-Wave Bandpass Filters by Standard 0.18-μm CMOS Technology

Millimeter-wave (mm-wave) bandpass filters are presented using the standard 0.18-mum CMOS process. Without any postprocessing steps, thin film microstrip (TFMS) structure is properly constructed on the low-resistivity silicon substrate, aiming at reducing the substrate loss and crosstalk to a large extent. Using the broadside-coupled scheme, a tight coupling is achieved so as to make up a class of low-loss and broadband TFMS bandpass filters in the mm-wave range. To achieve a small size, one-stage and two-stage filters with sinuous-shaped resonators are designed and fabricated. A good agreement between the predicted and measured results has been observed up to 110 GHz     

A 16–46 GHz Mixer Using Broadband Multilayer Balun in 0.18-μm CMOS Technology

A 16-46 GHz mixer using broadband balun fabricated in standard 0.18-mum CMOS process is demonstrated. The broadside-coupled balun with wide bandwidth and low insertion loss utilizes the inherent 3D multilayer structure in CMOS process. The mixer exhibits radio frequency bandwidth from 16 to 46 GHz with a conversion loss ranging from 13 plusmn 1.5 dB, and achieves bandwidth over 103% with a compact chip size of 0.24 mm².     

A 0.18-μm CMOS 1.25-Gbps Automatic-Gain-Control Amplifier

A 1.25-Gbps automatic-gain-control (AGC) amplifier is presented and it has been fabricated in 0.18-mum CMOS technology. To achieve a constant settling time, this AGC amplifier with the proposed variable gain amplifier (VGA) is presented. The measured VGA has a gain tuning range of 28.5 dB from -10 to 18.5 dB, and its measured group delay is about 12.15 ns. For the bit-error rate of 10^-12, the sensitivity and the overload for this AGC amplifier are 25 and 430 mV, respectively. It achieves input dynamic range of 24.7 dB. The power dissipation is 43.2 mW from a single 1.8-V supply voltage. The chip area is 0.82 mm times 0.56 mm includes I/O pads.     

An Ultra-Wide-Band 0.4–10-GHz LNA in 0.18-μm CMOS

A two-stage ultra-wide-band CMOS low-noise amplifier (LNA) is presented. With the common-gate configuration employed as the input stage, the broad-band input matching is obtained and the noise does not rise rapidly at higher frequency. By combining the common-gate and common-source stages, the broad-band characteristic and small area are achieved by using two inductors. This LNA has been fabricated in a 0.18-mum CMOS process. The measured power gain is 11.2-12.4 dB and noise figure is 4.4-6.5 dB with -3-dB bandwidth of 0.4-10 GHz. The measured IIP3 is -6 dBm at 6 GHz. It consumes 12 mW from a 1.8-V supply voltage and occupies only 0.42 mm²     

A 60-GHz Millimeter-Wave Bandpass Filter Using 0.18-μm CMOS Technology

This letter presents the design and implementation of a 60-GHz millimeter-wave RF-integrated-circuit-on-chip bandpass filter using a 0.18-mum standard CMOS process. A planar ring resonator structure with dual-transmission zeros was adopted in the design of this CMOS filter. The die size of the chip is 1.148times1.49 mm². The investigations of sensitivity to the insertion loss and the passband bandwidth for different perturbation stub sizes are also studied. The filter has a 3-dB bandwidth of about 12 GHz at the center frequency of 64 GHz. The measured insertion loss of the passband is about 4.9 dB, and the return loss is better than 10 dB within the passband.     

A Dual-Antenna Phased-Array UWB Transceiver in 0.18-μm CMOS

A dual-antenna ultra-wideband (UWB) transceiver in 0.18-mum CMOS for mode-1 OFDM applications employs the techniques of antenna diversity and integrated RF selectivity to improve robustness to interferers. Optimal selectivity in receiver and band flatness in transmitter are achieved by on-chip calibration of each band. The packaged device achieves an overall noise figure of 4.7 dB, an IIP3 of -0.8 dBm, a TX P1 dB of 3.1 dBm, and an error vector magnitude (EVM) of -27.2 dB for 480 Mb/s. The transmit output spectrum is fully compliant with FCC mask for UWB without any external bandpass filter     

A 0.18-μm CMOS Balanced Amplifier for 24-GHz Applications

A 24-GHz balanced amplifier (BA) with a 45-dB gain is realized in 0.18-mum CMOS technology. An effective technique, pi-type parallel resonance, is proposed to boost the high-frequency gain of a MOSFET by resonating out the inherent capacitances. The miniaturized lumped-element coupler in the circuit occupies a chip area of only ~2% compared to that of the conventional transmission-line coupler. The BA consumes 123 mW from a supply voltage of 1 V. To the best of the authors' knowledge, the proposed CMOS BA presents the highest gain of 45.0 dB with a chip area of 0.97 times 0.63 mm² (core area: 0.78 times 0.43 mm²) among the published narrowband amplifiers with similar technologies and operation frequencies.     

40-Gb/s High-Gain Distributed Amplifiers With Cascaded Gain Stages in 0.18-μm CMOS

A novel circuit topology for high-gain distributed amplifiers is presented in this study. Based on the conventional distributed architecture, the gain cells are realized by cascading cas- code stages for gain enhancement. In addition, the stagger-tuning technique is extensively utilized in the design of the cascode stages as well as the cascaded stages, leading to significant improvement in terms of the operating bandwidth and the gain flatness. With the proposed circuit architecture, two amplifiers are implemented in a standard 0.18-mum CMOS technology. The amplifier with a 3 times 3 configuration exhibits a gain of 16.2 dB and a 3-dB bandwidth of 33.4 GHz, while the one in a form of 2 times 4 demonstrates a gain of 20 dB and a bandwidth of 39.4 GHz. Consuming a dc power of 260 mW from a 2.8-V supply voltage, both circuits provide clear eye-opening with a pseudorandom bit sequence (PRBS) at 40 Gb/s.     

Low-Power Approaches to High-Speed Current-Steering Digital-to-Analog Converters in 0.18-μm CMOS

This paper will discuss a number of circuit approaches which lower the power consumed by a current steering digital-to-analog converter while maintaining both DC and AC performance levels. An example design provides 14-bit resolution and 200 MSPS conversion rate in a one-poly four-metal (1P4M) 0.18-mum CMOS process. The inclusion of optional 3.3-V compatible devices allows operation over a supply range from 1.7 to 3.6 V. A power dissipation/conversion rate figure of merit of as low as 0.17 mW/MSPS was achieved for 1.8-V operation and as low as 0.28 mW/MSPS at 3.3 V. A measured single-tone SFDR of 70 dB is achieved at a 50-MHz output frequency, with a two-tone IMD of -75 dBc at 71 MHz output.     

A 32-GHz Rotary Traveling-Wave Voltage Controlled Oscillator in 0.18-μm CMOS

A millimeter-wave multiphase voltage-controlled oscillator (VCO) is presented. In order to facilitate high-frequency oscillation and to minimize the phase error caused by the device and layout mismatch, a rotary traveling-wave topology based on transmission lines with inductive loading is employed for the circuit implementation. Using a 0.18-mum CMOS process, the fabricated VCO provides half- quadrature output phases at 32 GHz. The measured output power and phase noise at 1-MHz offset are -9 dBm and -108 dBc/Hz, respectively. Operated at a supply voltage of 1.2 V, the power consumption of the proposed circuit is 54 mW.     

1.25/2.5-Gb/s Dual Bit-Rate Burst-Mode Clock Recovery Circuits in 0.18-μm CMOS Technology

A burst-mode clock recovery circuit with a novel dual bit-rate structure is presented. It utilizes two gated oscillators to align the clock with data edges and can operate in half-rate clocking mode, doubling data throughput, as well as in full-rate clocking mode. The gated oscillator reset-phase control scheme causes the starting phase of gated oscillators to alternate repeatedly between 0deg and 180deg according to the current clock phase. A prototype chip was designed with the 0.18-mum CMOS technology, and a 1.25/2.5-Gb/s dual-mode operation was verified by measurement     

A 3.3 mW K-Band 0.18-μ m 1P6M CMOS Active Bandpass Filter Using Complementary Current-Reuse Pair

This letter presents a low-power active bandpass filter (BPF) at K-band fabricated by the standard 0.18 mum 1P6M CMOS technology. The proposed filter is evolved from the conventional half-wavelength resonator filter, using the complementary-conducting-strip transmission line (CCS TL) as the half-wavelength resonator. Furthermore, the complementary MOS cross-couple pair is proposed as a form of current-reuse scheme for achieving low-power consumption and high Q-factor simultaneously. The simulated results indicate that the Q-factor of the proposed half-wavelength resonator can be boosted from 9 to 513 at 25.65 GHz compared with the resonator enhanced by the nMOS cross-couple pair to Q-factor of merely 43 under the same power consumption. The proposed active BPF of order two occupies the chip area of 360 mum times 360 mum without contact pads. The measured results show that the center frequency of the active BPF is 22.70 GHz and a bandwidth of 1.68 GHz (7.39 %). The measured P_{1 dB} and noise figure at 22.70 GHz are -7.65 dBm and 14.05 dB, respectively. There is a 56.84 dB suppression between the fundamental tone and the second harmonic when the input power is -11.26 dBm. While showing 0 dB loss and some residual gain, the active BPF consumes 2.0 mA at 1.65 V supply voltage with maximum of 0.15 dB insertion loss and 9.96 dB return loss at pass band.     

A 0.8-V 0.25-mW Current-Mirror OTA With 160-MHz GBW in 0.18-μm CMOS

A low-voltage low-power CMOS operational transconductance amplifier (OTA) with near rail-to-rail output swing is presented in this brief. The proposed circuit is based on the current-mirror OTA topology. In addition, several circuit techniques are adopted to enhance the voltage gain. Simulated from a 0.8-V supply voltage, the proposed OTA achieves a 62-dB dc gain and a gain-bandwidth product of 160 MHz while driving a 2-pF load. The OTA is designed in a 0.18-mum CMOS process. The power consumption is 0.25 mW including the common-mode feedback circuit     

A 2.2-μm-Pitch Single-Transistor Charge-Modulation Pixel in a 0.13-μm CMOS Process

This paper presents the investigation of a 2.2-mum-pitch single-transistor pixel designed in a 0.13-mum CMOS process. Based on charge-induced potential variation of the floating-body of the transistor, this single pixel device can be operated to perform photodetection, charge integration, signal readout, and reset. The main electrical characteristics of the pixel are evaluated by device modeling and simulations as well as measurements of test chips. With optimization of process and electrical parameters, testing results show a conversion factor of 47 muV/hole, a charge-handling capability of 3500 holes, a temporal noise of four holes, and a dynamic range of 40 dB.     

An Ultra-Wideband High-Linearity CMOS Mixer With New Wideband Active Baluns

A 2-11-GHz high linearity CMOS down-conversion mixer with wideband active baluns using 0.18-mum CMOS technology is demonstrated in this paper. The mixer employs a folded cascode Gilbert cell topology and on-chip broadband active baluns. The folded cascode approach is adopted to increase the output swing, and the linearity is enhanced by a harmonic distortion canceling technique derived from the harmonic balance analysis. The proposed configuration shows the highest IIP₃ and IP_{1 dB}, and exhibits more compact size than most published studies. A broadband active balun is used to generate wideband differential signals, together with the derivation of a closed-form expression for the phase imbalance. This single-ended wideband mixer has the conversion gain of 6.9plusmn1.5 dB, input 1-dB compression point (IP_{1 dB}) of - 3.5 dBm, single-sideband noise figure of 15.5 dB, and third-order input intercept point (IIP₃) of 6.5 dBm under the power consumption of 25.7 mW from a 1.8-V power supply. The chip area is 0.85 x 0.57 mm².     

Ultra-Compact High-Linearity High-Power Fully Integrated DC–20-GHz 0.18-μm CMOS T/R Switch

A fully integrated ultra-broadband transmit/receive (T/R) switch has been developed using nMOS transistors with a deep n-well in a standard 0.18-mum CMOS process, and demonstrates unprecedented insertion loss, isolation, power handling, and linearity. The new CMOS T/R switch exploits patterned-ground-shield on-chip inductors together with MOSFET's parasitic capacitances to synthesize artificial transmission lines, which result in low insertion loss over an extremely wide bandwidth. Negative bias to the bulk or positive bias to the drain of the MOSFET devices with floating bulk is used to reduce effects of the parasitic diodes, leading to enhanced linearity and power handling for the switch. Within dc-10, 10-18, and 18-20 GHz, the developed CMOS T/R switch exhibits insertion loss of less than 0.7, 1.0, and 2.5 dB and isolation between 32-60, 25-32, and 25-27 dB, respectively. The measured 1-dB power compression point and input third-order intercept point reach as high as 26.2 and 41 dBm, respectively. The new CMOS T/R switch has a die area of only 230 mumtimes250 mum. The achieved ultra-broadband performance and high power-handling capability, approaching those achieved in GaAs-based T/R switches, along with the full-integration ability confirm the usefulness of switches in CMOS technology, and demonstrate their great potential for many broadband CMOS radar and communication applications     

A DLL-Based Programmable Clock Multiplier in 0.18-μ m CMOS With −70 dBc Reference Spur

This paper describes a 150-400 MHz programmable clock multiplier which uses a recirculating DLL. The clock multiplier uses a sampling phase detector and employs chopping, autozeroing and various other circuit techniques to reduce static phase offset and crosstalk between the reference and the output clock. The DLL is implemented in 0.18-mum CMOS, consumes 16 mW of power, and achieves 1-5 ps RMS jitter and -70 dBc reference spur level.     

A 0.5–7.5 GHz Ultra Low-Voltage Low-Power Mixer Using Bulk-Injection Method by 0.18- μm CMOS Technology

A fully differential low-voltage low-power downconversion mixer using a TSMC 0.18-mum CMOS logic process is presented in this letter. The mixer was designed with a four-terminal MOS transistor, the radio-frequency (RF) and local-oscillator signals apply to the gate and bulk of the device, respectively while the intermediate frequency (IF) signals output was from the drain. The mixer features a maximum conversion gain of 5.7dB at 2.4 GHz, an ultra low dc power consumption of 0.48 mW, a noise figure of 15 dB, and an input IP of 5.7 dBm. Moreover, the chip area of the mixer core is only 0.18 times 0.2 mm². The measured 3-dB RF frequency bandwidth is from 0.5 to 7.5 GHz with an IF of 100 MHz, and it is greatly suitable for low-power in wireless communication.