Electrical and structural characterization of PLD grown CeO2–HfO2 laminated high-k gate dielectrics

The electrical and physical properties of CeO₂–HfO₂ nanolaminates deposited by pulsed laser deposition (PLD) are investigated. The properties of the nanolaminates are compared with binary CeO₂ and HfO₂ thin films. Layers were deposited using CeO₂ and HfO₂ targets at substrate temperatures between 220 and 620 °C in 10 Pa Ar+H₂ or O₂. In situ post deposition anneal (PDA) was achieved by controlled cooling down to room temperature with . Nanolaminates starting with CeO₂ show lower EOT and leakage compared to layers starting with HfO₂. TEM and XRD analyses showed thickness-dependent crystallinity of the layers, varying from amorphous to highly oriented polycrystalline phase.C–V and I–V measurements were done on the capacitors. Lowest fixed-charge density was found for the nanolaminates deposited at 520 °C. The k values of the nanolaminates extracted by the EOT-physical thickness plots were found to be 141, 48 and 22, for deposition temperatures 420, 520 and 620 °C, respectively. Higher k value for lower deposition temperatures is explained by the thickness dependent morphology of the layers. An with was found for binary HfO₂ layer with 4 nm physical thickness. Lowest leakage current density was for a 4 nm laminate deposited at 420 °C and with a cooling rate of 2 °C/min during PDA.     

Electrical properties of SiO2/TiO2 high-k gate dielectric stack

The trapping/detrapping behavior of charge carriers in ultrathin SiO₂/TiO₂ stacked gate dielectric during constant current (CCS) and voltage stressing (CVS) has been investigated. Titanium tetrakis iso-propoxides (TTIP) was used as the organometallic source for the deposition of ultra-thin TiO₂ films at low temperature (<200 °C) on strained-Si/relaxed-Si_0.8Ge_0.2 heterolayers by plasma-enhanced chemical vapor deposition (PECVD) in a microwave (700 W, 2.45 GHz) plasma cavity discharge system at a pressure of 66.67 Pa. Stress-induced leakage current (SILC) through SiO₂/TiO₂ stacked gate dielectric is modeled by taking into account the inelastic trap-assisted tunneling (ITAT) mechanism via traps located below the conduction band of TiO₂ layer. The increase in the gate current density observed during CVS from room temperature up to 125 ^oC has been analyzed and modeled considering both the buildup of charges in the layer as well as the SILC contribution. Trap generation rate and trap cross-section are extracted. A capture cross-section in the range of 10⁻¹⁹ cm² as compared to 10⁻¹⁶ cm² in SiO₂ has been observed. A temperature-dependent trap generation rate and defects have also been investigated using time-dependent current density variation during CVS. The time dependence of defect density variation is calculated within the dispersive transport model, assuming that these defects are produced during random hopping transport of positively charge species in the insulating high-k stacked layers. SILC generation kinetics, i.e. defect generation probability under different injected fluences for various high-constant stress voltages in both polarities have been studied. An empirical relation between trap generation probability and applied stress voltage for various injected fluences has been developed.     

Hf-O-N and HfO2 barrier layers for Hf-Ti-O gate dielectric thin films

Hf-O-N and HfO₂ thin films were evaluated as barrier layers for Hf-Ti-O metal oxide semiconductor capacitor structures. The films were processed by sequential pulsed laser deposition at 300 °C and ultra-violet ozone oxidation process at 500 °C. The as-deposited Hf-Ti-O films were polycrystalline in nature after oxidation at 500 °C and a fully crystallized (o)-HfTiO₄ phase was formed upon high temperature annealing at 900 °C. The Hf-Ti-O films deposited on Hf-O-N barrier layer exhibited a higher dielectric constant than the films deposited on the HfO₂ barrier layer. Leakage current densities lower than 5 × 10 A/cm² were achieved with both barrier layers at a sub 20 Å equivalent oxide thickness.     

Electrical reliability aspects of HfO2 high-k gate dielectrics with TaN metal gate electrodes under constant voltage stress

The dielectric breakdown property of ultrathin 2.5 and 5.0 nm hafnium oxide (HfO₂) gate dielectric layers with metal nitride (TaN) gate electrodes for metal oxide semiconductor (MOS) structure has been investigated. Reliability studies were performed with constant voltage stressing to verify the processing condition effects (film thicknesses and post metal annealing temperatures) on times to breakdown. The leakage current characteristics are improved with post metal annealing temperatures (PMA) for both 2.5 and 5.0 nm HfO₂ physical thicknesses. However, it is more prominent (2 orders of magnitudes) for 2.5 nm HfO₂ film thickness. The values of oxide-trapped charge density and interface-state density are also improved for 2.5 nm HfO₂ film. The different stages of charge-trapping behaviors, i.e., stress-induced leakage current, soft and hard breakdown mechanisms have been detected. During constant voltage stress of the MOS capacitors, an increase in the time-dependent gate current is observed, followed by the occurrence of several fluctuations. The amplitude of the fluctuations is much larger in the 5.0 nm HfO₂ gate dielectric layer compared to the 2.5 nm HfO₂ layer. After the occurrence of such fluctuations, the current–voltage characteristics exhibited an increased in gate current compared to the fresh (unstressed) devices.     

Direct tunneling gate current model for symmetric double gate junctionless transistor with SiO2/high-k gate stacked dielectric

A junctionless transistor is emerging as a most promising device for the future technology in the decananometer regime. To explore and exploit the behavior completely, the understanding of gate tunneling current is of great importance. In this paper we have explored the gate tunneling current of a double gate junctionless transistor(DGJLT) for the first time through an analytical model, to meet the future requirement of expected high-k gate dielectric material that could replace SiO₂. We therefore present the high-k gate stacked architecture of the DGJLT to minimize the gate tunneling current. This paper also demonstrates the impact of conduction band offset, workfunction difference and k-values on the tunneling current of the DGJLT.     

Electrical properties of metal–HfO2–silicon system measured from metal–insulator–semiconductor capacitors and metal–insulator–semiconductor field–effect transistors using HfO2 gate dielectric

Metal–insulator–semiconductor (MIS) capacitors and metal–insulator–semiconductor field effect transistors (MISFETs) incorporating HfO₂ gate dielectrics were fabricated using RF magnetron sputtering. In this work, the essential structures and electrical properties of HfO₂ thin film were examined. The leakage current measured from MIS capacitors depends on the sputtering gas mixture and the annealing temperature. The best condition to achieve the lowest leakage current is to perform the annealing at 500 °C with a mixture of 50% N₂ and 50% O₂ gas ratio. Aluminum is used as the top electrode. The Al/HfO₂ and the HfO₂/Si barrier heights extracted from Schottky emission are 1.02 eV and 0.94 eV, respectively. An Al/HfO₂/Si energy band diagram is proposed based on these results.     

Observation and characterization of defects in HfO2 high-K gate dielectric layers

A deeper understanding of Hf-based high-K materials in terms of their structural and electrical defects is important for device implementation. We have studied the occurrence of such defects using wet-etch defect delineation, electron microscopy, depth-profiling and conventional electrical measurements. It is evident that defects are present in HfO₂ films that are related to the microstructure and stoichiometry of the film, which in turn depend on the deposition temperature, starting surface and post-deposition treatments. These results appear to be independent of the deposition technique. Two types of defects were observed, those that are physically visible and cause immediate failures especially on large-area structures, and those that cause high leakage but not immediate failures. The existence of defects affects not only leakage or performance but will also affect the reliability through trapping of charge at the defect sites. As films continue to be scaled thinner, the requirements on defect reduction to minimize electrical impact may become more stringent.     

Thin-film transistors incorporating a thin, high-quality PECVD SiO2 gate dielectric

Thin-film transistors (TFTs) have been made that incorporate a thin (~380 Å), high-quality plasma-enhanced chemical vapor deposition (PECVD) SiO₂ film as the gate dielectric in a staggered-inverted structure. Threshold voltages and mobilities have been found to be in the range of 1.6-2.4 V and 0.20-0.25 cm² V^-1 s^-1, respectively, where the exact values are dependent on the measurement technique used. Very low gate leakage currents (<10^-11 A) were recorded when measured using a ramped I-V technique, even for electric fields as high as 5×10⁶ V/cm     

Electrical properties of Ge metal–oxide–semiconductor capacitors with high-k La2O3 gate dielectric incorporated by N or/and Ti

LaON, LaTiO and LaTiON films are deposited as gate dielectrics by incorporating N or/and Ti into La2O3 using the sputtering method to fabricate Ge MOS capacitors, and the electrical properties of the devices are carefully examined. LaON/Ge capacitors exhibit the best interface quality, gate leakage property and device reliability, but a smaller k value (14.9). LaTiO/Ge capacitors exhibit a higher k value (22.7), but a deteriorated interface quality, gate leakage property and device reliability. LaTiON/Ge capacitors exhibit the highest k value (24.6), and a relatively better interface quality (3.1E11 eV^-1cm^-2), gate leakage property (3.6E3 A/cm^2 at Vg = 1 V + Vfb) and device reliability. Therefore, LaTiON is more suitable for high performance Ge MOS devices as a gate dielectric than LaON and LaTiO materials.     

Thermally deposited Ag-doped CdS thin film transistors with high-k rare-earth oxide Nd2O3 as gate dielectric

The performance of thermally deposited CdS thin film transistors doped with Ag has been reported. Ag-doped CdS thin films have been prepared using chemical method. High dielectric constant rare earth oxide Nd₂O₃ has been used as gate insulator. The thin film trasistors are fabricated in coplanar electrode structure on ultrasonically cleaned glass substrates with a channel length of 50 μm. The thin film transistors exhibit a high mobility of 4.3 cm² V^?1 s^?1 and low threshold voltage of 1 V. The ON-OFF ratio of the thin film transistors is found as 10⁵. The TFTs also exhibit good transconductance and gain band-width product of 1.15 × 10^?3 mho and 71 kHz respectively.     

Silicon nano-particles in SiO2 sol–gel film for nano-crystal memory device applications

A novel 2-bit nano-silicon based non-volatile memory is proposed to double memory density. The thin film structure exhibits two conduction states (ON and OFF) at different voltages and has a cost-effective structure. The structure utilizes the good electrical properties of fluorinated SiO₂ thin films, together with the bi-stable properties conferred by the nano-silicon particles therein embedded. A polymeric layer of 8-hydroxyquinoline aluminum salt (Alq3) further deposited on the top of the nano-particle layer through chemical evaporation and a silver paste contact determines the final structure. The positive 0–15 V scan reveals two discontinuities with an ON/OFF ratio of 10⁴–10⁵ (2–4 V) and OFF/ON of 10³ (12.5–13.0 V). The reverse scan displays again two distinct thresholds, range of 10.5–11.0 V (ON/OFF ratio 10⁻³), respectively, 0.5 V (OFF/ON ratio 10⁻⁵–10⁻⁴).     

具有SiO2/SiNX/SiO2 复合绝缘层的有机薄膜晶体管

We have investigated a SiO_2/SiN_x/SiO_2 composite insulation layer structured gate dielectric for an organic thin film transistor(OTFT) with the purpose of improving the performance of the SiO_2 gate insulator. The SiO_2/SiN_x/SiO_2 composite insulation layer was prepared by magnetron sputtering.Compared with the same thickness of a SiO_2 insulation layer device,the SiO_2/SiN_x/SiO_2 composite insulation layer is an effective method of fabricating OTFT with improved electric characteristics and decrease...     

Thermal stability of high-k Er-silicate gate dielectric formed by interfacial reaction between Er and SiO2 films

We fabricated a high-k Er-silicate gate dielectric using interfacial reaction between Er and SiO₂ films and investigated its thermal stability. The reduced capacitance with increasing annealing temperature is associated with the chemical bonding change of Er-silicate from Er-rich to Si-rich, induced by a reaction between Er-silicate and Si during thermal treatment. Further an increase in the annealing temperature (>500 °C) causes the formation of Si dangling bonds, which is responsible for an increased interface trap density.     

Reliability of thin ZrO2 gate dielectric layers

In this work we examine the positive bias temperature instability (PBTI) and stress induced leakage current (SILC) reliability of nFET devices with thin (2.5 nm) ZrO₂ gate dielectric layers. nFET devices show anomalous PBTI behavior in the form of a negative threshold voltage (V_t) shift during positive bias stress with little temperature dependence and it is not ‘frozen out’ at lower temperatures, indicating a single non-diffusion based mechanism. Correlations between the PBTI and the stress induced leakage current (SILC) suggest that the PBTI effect originates from trapping into empty defects which are initially detected as SILC and located just below the silicon conduction band. These defects also appear to be linked to the time dependent dielectric breakdown behavior.     

高介电常数栅介质/二氧化硅界面偶极子成因研究

The formation of an electric dipole at the high-k/SiO2 interface is quantitatively analyzed. The band lineups and physical origin of dipole formation at the high-k/SiO2 interface are explained by the dielectric contact induced gap states(DCIGS). The charge neutrality level(CNL) of the DCIGS, which represents a distribution of high-k and SiO2 contact induced gap states, is utilized to study the dipole moment. The charge transfer due to different CNLs of high-k and SiO2 is considered as the dominant origin of dipole formation. The theoretically calculated dipole strengths of high-k/SiO2 systems based on this model are in good agreement with the experimental data.     

An investigation of surface state capture cross-sections for metal–oxide–semiconductor field-effect transistors using HfO2 gate dielectrics

MOSFETs and MOSCs incorporating HfO₂ gate dielectrics were fabricated. The I_DS–V_DS, I_DS–V_GS, gated-diode and C–V characteristics were investigated. The subthreshold swing and the interface trap density were obtained. The surface recombination velocity and the minority carrier lifetime in the field-induced depletion region measured from the gated diodes were about 2.73 × 10³ cm/s and 1.63 × 10⁻⁶ s, respectively. The effective capture cross section of surface state was determined to be 1.6 × 10⁻¹⁵ cm² using the gated-diode technique in comparison with the subthreshold swing measurement. A comparison with conventional MOSFETs using SiO₂ gate oxide was also made.     

Investigation of atomic vapour deposited TiN/HfO2/SiO2 gate stacks for MOSFET devices

HfO₂ films were grown by atomic vapour deposition (AVD) on SiO₂/Si (1 0 0) substrates. The positive shift of the flat band voltage of the HfO₂ based metal-oxide-silicon (MOS) devices indicates the presence of negative fixed charges with a density of 5 × 10¹² cm⁻². The interface trap charge density of HfO₂/SiO₂ stacks can be reduced to 3 × 10¹¹ eV⁻¹ cm⁻² near mid gap, by forming gas annealing. The extracted work function of 4.7 eV preferred the use of TiN as metal gate for PMOS transistors. TiN/HfO₂/SiO₂ gate stacks were integrated into gate-last-formed MOSFET structures. The extracted maximum effective mobility of HfO₂ based PMOS transistors is 56 cm²/Vs.     

Top gate ZnO-Al2O3 thin film transistors fabricated using a chemical bath deposition technique

ZnO thin films were prepared by a simple chemical bath deposition technique using an inorganic solution mixture of ZnCl₂ and NH₃ on glass substrates and then were used as the active material in thin film transistors (TFTs). The TFTs were fabricated in a top gate coplanar electrode structure with high-k Al₂O₃ as the gate insulator and Al as the source, drain and gate electrodes. The TFTs were annealed in air at 500 ℃ for 1 h. The TFTs with a 50 μm channel length exhibited a high field-effect mobility of 0.45 cm²/(V·s) and a low threshold voltage of 1.8 V. The sub-threshold swing and drain current ON-OFF ratio were found to be 0.6 V/dec and 10⁶, respectively.     

Improvement on low-temperature deposited HfO2 film and interfacial layer by high-pressure oxygen treatment

In this study, high-pressure oxygen (O₂ and O₂ + UV light) technologies were employed to effectively improve the properties of low-temperature-deposited metal oxide dielectric films and interfacial layer. In this work, 13 nm HfO₂ thin films were deposited by sputtering method at room temperature. Then, the oxygen treatments with a high-pressure of 1500 psi at 150 °C were performed to replace the conventional high temperature annealing. According to the XPS analyses, integration area of the absorption peaks of O-Hf and O-Hf-Si bonding energies apparently raise and the quantity of oxygen in deposited thin films also increases from XPS measurement. In addition, the leakage current density of standard HfO₂ film after O₂ and O₂ + UV light treatments can be improved from 3.12 × 10⁻⁶ A/cm² to 6.27 × 10⁻⁷ and 1.3 × 10⁻⁸ A/cm² at |Vg| = 3 V. The proposed low-temperature and high pressure O₂ or O₂ + UV light treatment for improving high-k dielectric films is applicable for the future flexible electronics.     

Comparative study of AlGaN/GaN metal-oxide-semiconductor heterostructure field-effect transistors with Al2O3 and HfO2 gate oxide

AlGaN/GaN metal-oxide-semiconductor heterostructure field-effect transistors (MOSHFETs) with Al₂O₃ gate oxide which was deposited by atomic layer deposition (ALD) were fabricated and their performance was then compared with that of AlGaN/GaN MOSHFETs with HfO₂ gate oxide. The capacitance (C)-voltage (V) curve of the Al₂O₃/GaN MOS diodes showed a lower hysteresis and lower interface state density than the C-V curve of the HfO₂/GaN diodes, indicating better quality of the Al₂O₃/GaN interface. The saturation of drain current in the I_D-V_GS relation of the Al₂O₃ AlGaN/GaN MOSHFETs was not as pronounced as that of the HfO₂ AlGaN/GaN MOSHFETs. The gate leakage current of the Al₂O₃ MOSHFET was five to eight orders of magnitude smaller than that of the HfO₂ MOSHFETs.