A room temperature 0.1 μm CMOS on SOI

An advanced 0.1 μm CMOS technology on SOI is presented. In order to minimize short channel effects, relatively thick nondepleted (0.15 μm) SOI film, highly nonuniform channel doping and source-drain extension-halo were used. Excellent short channel effects (SCE) down to channel lengths below 0.1 μm were obtained. It is shown that undepleted SOI results in better short channel effect when compared to ultrathin depleted SOI. Devices with little short channel effect all the way to below 500 Å effective channel length were obtained. Furthermore, utilization of source-drain extension-halo minimizes the bipolar effect inherent in the floating body. These devices were applied to a variety of circuits: Very high speeds were obtained: Unloaded delay was 20 ps, unloaded NAND (FI=FO=3) was 64 ps, and loaded NAND (FI=FO=3, C_L=0.3 pF) delay was 130 ps at supply of 1.8 V. This technology was applied to a self-resetting 512 K SRAM. Access times of 2.5 ns at 1.5 V and 3.5 ns at 1.0 V were obtained     

350 MHz opamp-RC filter in 0.18 μm CMOS

A 350 MHz fifth-order elliptic opamp-RC filter demonstrates that opamp-based filters need not have bandwidth disadvantages compared to transconductor-based filters. The filter, fabricated in standard digital 0.18 μm CMOS with 1.8 V V_DD, achieves 0.5 Vp-p signal swing at -40 dB THD     

6.8 GHz monolithic oscillator fabricated by 0.35 μm CMOStechnologies

A 6.8 GHz CMOS monolithic oscillator with a 5.9 dBm output power has been demonstrated by 0.35 μm 1P4M CMOS technologies. The oscillator was designed based on a home-made modified BSIM3v3 large-signal model, where the high-frequency parasitics were included. In addition, on chip spiral inductors and MIM capacitors for the resonant circuit were characterised and used in this monolithic oscillator circuit     

Inverter performance of 0.10 μm CMOS operating at roomtemperature

The switching performance of 0.10 μm CMOS devices operating at room temperature has been discussed on the basis of both experimental and simulated results. The measured propagation delay time of a 0.10 μm gate length CMOS has been quantitatively divided into intrinsic and parasitic components for the first time. The results have shown that the drain junction capacitance strongly affects the propagation delay time in the present 0.10 μm CMOS. The switching performance of a 0.10 μm ground rule CMOS has been simulated by using device parameters extracted from the experimental results. In the 0.10 μm ground rule CMOS, it has been shown that an increase of the contact resistance will degrade the propagation delay time, which is one of the most essential problems in further device miniaturization. It has been also demonstrated that even if the specific contact resistance ρ_c is reduced to be less than 1×10^-7 Ω cm, further reduction of the gate overlap capacitance C_ov will be required to achieve the propagation delay time to be less than 10 ps in the 0.10 μm ground rule CMOS at room temperature     

Scaling of poly-encapsulated LOCOS for 0.35 μm CMOS technology

We demonstrate the scaling of Poly-Encapsulated LOCOS (PELOX) for 0.35 μm CMOS technology without detrimental effects on gate oxide and shallow source/drain junction integrity. As-grown bird's beak punchthrough is shown to fundamentally limit the scalability of LOCOS-based schemes for narrow nitride features. A quantitative comparison of bird's beak punchthrough is made between LOCOS, Poly-Buffer LOCOS (PBL), and PELOX. The PELOX scalability is emphasized by evaluating the impact of the polysilicon-sealed cavity length for narrow nitride features. We present the realization of a 1 μm active/isolation pitch fully meeting the geometry and off-leakage requirements of 0.35 μm CMOS technologies (VDS⩽5 V). This field-implant-free isolation module avoids unnecessary process complexity by successfully integrating scaled PELOX with the split well-drive-in scheme. A highlight of this new approach is that the NMOSFET characteristics are largely width-independent down to 0.3 μm dimensions     

0.25 μm gate length CMOS devices for cryogenic operation

Under cryogenic operation, a low V_th realizes a high speed performance at a greatly reduced power-supply voltage, which is the most attractive feature of Cryo-CMOS. It is very important in sub-0.25 μm Cryo-CMOS devices to reconcile the miniaturization and the low V_th. Double implanted MOSFET's technology was employed to achieve the low V_th while maintaining the short channel effects immunity. We have investigated both the DC characteristics and the speed performance of 0.25 μm gate length CMOS devices for cryogenic operation. The measured transconductances in the saturation region were 600 mS/mm for 0.2 μm gate length n-MOSFET's and 310 mS/mm for 0.25 μm gate length p-MOSFET's at 80 K. The propagation delay time in the fastest CMOS ring oscillator was 22.8 ps at V_dd=1 V at 80 K. The high speed performance at extremely low power-supply voltages has been experimentally demonstrated. The speed analysis suggests that the sub-l0 ps switching of Cryo-CMOS devices will be realized by reducing the parasitic capacitances and through further miniaturization down to 0.1 μm gate length or below     

基于AAC音频编码与混沌加密的语音加密技术实现

为了减少语音的加密数据量,在此提出一种基于压缩编码和混沌加密的语音加密方案。采用先编码后加密的实现方法,语音编码算法采用AAC低复杂度编码算法,加密算法采用二维猫映射算法,在ARM9硬件平台下的实现结果表明AAC编码压缩比为18∶1,猫映射加解密算法执行效率快,解密后无失真,实验结论证实该方案是可行的。在此将音频压缩算法与混沌加密结合起来,在不影响语音音质和加密效果的前提下减少了加密运算的数据量以及最终加密文件的大小,缩短了加解密语音数据所花费的时间,减少了语音保密通信所需要的带宽。     

Fully integrated 0.25 μm CMOS VCSEL driver with current peaking

A vertical-cavity-surface-emitting laser (VCSEL) driver chip based on a novel circuit concept for current peaking has been designed and fabricated in a 0.25 μm complementary metal-oxide-semiconductor (CMOS) process. This concept allows the easy integration of a peaking driving scheme in CMOS. Experimental results show speed extension from 500 Mbit/s for current on-off to 3.9 Gbit/s for current peaking driving     

140 Mbit/s receiver performance at 2.4 μm using InAsSbP detector

A 140 Mbit/s optical receiver has been demonstrated using for the first time an InAsSbP photodetector operating at room temperature and optimised for operation at 2.4 μm, close to the minimum-loss wavelength of fluoride fibre. The receiver sensitivity was measured to be -32 dBm at 140 Mbit/s and 2.4 μm     

A methodology for deep sub-0.25 μm CMOS technology prediction

We present a novel methodology for characterization of sub-quartermicron CMOS technologies. It involves process calibration, device calibration employing two-dimensional device simulation and automated Technology Computer Aided Design (TCAD) optimization and, finally, transient mixed-mode device/circuit simulation. The proposed methodology was tested on 0.25 μm technology and applied to 0.13 μm technology in order to estimate ring oscillator speed. The simulation results show an excellent agreement with available experimental data     

A digitally controlled 2.4-GHz oscillator in 65-nm CMOS

This article presents a 2.4-GHz digitally controlled oscillator (DCO) for the ISM band. The circuit is designed using a 65-nm CMOS technology with an operating voltage of 1.2 V. The DCO comprises an LC oscillator core and the digital interface logic. The measured total frequency range is from 2.26 to 3.04 GHz. Its frequency quantization step is approximately 20 kHz, and using a digital ΣΔ-modulator (SDM), its effective frequency resolution is better than 1 kHz. Current consumption of the oscillator core is tunable through a 6-bit digital word. The measured phase noise is −122 dBc/Hz at 1-MHz offset frequency with 4.8-mA current consumption.     

Improving the RF performance of 0.18 μm CMOS with deep n-wellimplantation

The radio-frequency (RF) figures of merit of 0.18 μm complementary metal-oxide-semiconductor (CMOS) technology are investigated by evaluating the unity-current-gain cutoff frequency (F _t) and maximum oscillation frequency (F_max). The device fabricated with an added deep n-well structure is shown to greatly enhance both the cutoff frequency and the maximum oscillation frequency, with negligible DC disturbance. Specifically, an 18% increase in F_t and 25% increase in F_max are achieved. Since the deep n-well implant can be easily adopted in a standard CMOS process, the approach appears to be very promising for future CMOS RF applications     

A 660 MB/s interface megacell portable circuit in 0.3 μm-0.7μm CMOS ASIC

A byte-wide I/O cell with 660 MB/s data rate uses low-jitter DLL-generated clocks, self-calibrated controlled-current drivers, and linear amplifier input receivers. The CAD techniques developed allow the design to be ported to CMOS processes ranging from 0.7 μm to 0.3 μm. The chip is 0.9×3.4 mm² using 0.3 μm rules     

BiCMOS technology with 60 GHz n-p-n bipolar and 0.25 μm CMOS

A BiCMOS technology has been developed that integrates a high-performance self-aligned double-polysilicon bipolar device into an advanced 0.25 μm CMOS process. The process sequence has been tailored to allow maximum flexibility in the bipolar device design without perturbation of the CMOS device parameters. Thus, n-p-n cutoff frequencies as high as 60 GHz were achieved while maintaining a CMOS ring oscillator delay per stage of about 54 ps at 2.5 V supply comparable to the performance in the CMOs-only technology. BiCMOS and BiNMOS circuits were also fabricated. BiNMOS circuits exhibited ≈45% delay improvement compared to CMOS-only circuits under high load conditions at 2.5 V     

Multipass diode-pumped Nd:YAG optical amplifiers at 1.06 μm and1.32 μm

We have built two versions of a diode-pumped Nd:YAG amplifier using a compact multipass confocal geometry with a fiber-coupled input. This confocal geometry provided efficient power and high gain in a volume of approximately 100 cm³. When pumped with a commercially mature 2 W 809 nm laser diode, the 1.06 μm version produced 460 mW and a small signal gain of 51 dB. The 1.32 μm version produced 170 mW and a small signal gain of 29 dB. Such an efficient amplifier, especially at 1.32 μm would be useful as a power booster in fiber optic telecommunications     

A 300 MHz digital double-sideband to single-sideband converter in 1μm CMOS

A 43-tap FIR Hilbert transform digital filter chip is described which implements both a double-sideband (DSB) to single-sideband (SSB) conversion with a decimation-by-2 and the converse operation of a SSB to DSB conversion with an interpolation-by-2. Over 70 dB of image rejection is achieved by the Hilbert transform filter. The 3.57×7.07 mm², 45 000 transistor chip was fabricated in a 1 μm N-well CMOS process and operates at sample rates in excess of 300 MHz     

A 200 MHz quadrature digital synthesizer/mixer in 0.8 μm CMOS

A 200 MHz quadrature direct digital frequency synthesizer/complex mixer (QDDFSM) chip is presented. The chip synthesizes 12 b sine and cosine waveforms with a spectral purity of -84.3 dBc. The frequency resolution is 0.047 Hz with a corresponding switching speed of 5 ns and a tuning latency of 14 clock cycles. The chip is also capable of frequency, phase, and quadrature amplitude modulation. These modulation capabilities operate up to the maximum clocking frequency. The chip provides the capability of parallel operation of multiple chips with throughputs up to 800 MHz. The 0.8 μm triple level metal N-well CMOS chip has a complexity of 52000 transistors with a core area of 2.6×6.1 mm². Power dissipation is 2 W at 200 MHz and 5 V     

A 500 MHz, 32 bit, 0.4 μm CMOS RISC processor

A 500 MHz, 32 bit RISC microprocessor has been experimentally developed using an 8-stage pipelined architecture and high-speed circuits, including a 500 MHz 1 kilobyte double-stage pipelined cache, a 1.8 ns register file, a double-stage binary look-ahead carry (BLC) adder circuit, and a 500 MHz phase locked loop (PLL) frequency multiplier. Newly developed circuit-integrating techniques include a stacked power-line structure, which serves as a noise shield and also provides low bounce, a low voltage-swing interface circuit with on-chip adjustable termination resistors, a small-skew clock distribution method, and a clock synchronization circuit which provides small-skew clock among LSI chips. About 200000 transistors are integrated into a 7.90 mm×8.84 mm die area with 0.4 μm CMOS fabrication technology. Power dissipation is 6 W at a 500 MHz operation and 3.3 V supply voltage     

Optimization of implant anneals to improve transistor performancein a 0.15 μm CMOS technology

The impact of including a rapid thermal anneal step after the extension implants is examined for a 0.15 μm CMOS process. SIMS data will verify that shallower junctions can be obtained with only a single anneal cycle after the source-drain implants, implying that transient enhanced diffusion is minimal for this technology. Further, transistor data indicates that improved CMOS device performance can be obtained without the extension anneal cycle     

Parametric oscillation at 3.2 μm in KTP pumped at 1.064 μm

The author reports the stable generation of 0.2-W average power IR pulses around 3.2 μm from the KTP parametric oscillator pumped by the Nd:YAG laser at 1.064 μm. In addition, improved Sellmeier's equations, which correctly predict almost all of the nonlinear experiments thus far reported, are presented, together with the absolute values of d₃₁ and d₃₂