高增益激光的饱和效应和最佳输出耦合

本文在均匀和非均匀谱线加宽情况下,计算了高增益介质在不同小信号增益系数和吸收系数下的激光输出特性,并讨论了饱和效应和最佳输出耦合。     

Current hogging injection logic-a new logic with high functional density

A new design concept for bipolar integrated circuits with high functional density will be presented. The basic current hogging injection logic (CHIL) gate consists of a lateral intermediate collector structure, where the last collector simultaneously forms the base region of an inversely operated vertical output transistor. Thus a CHIL gate can be looked at as a CHL gate with a functionally integrated output transistor, or as an integrated injection logic (I/SUP 2/L) inverter with controlled injection. Dc and pulse measurements are discussed and calculated results with a simple model suitable for computer-aided design (CAD) are presented. The static noise immunity of CHIL circuits is compared to CHL and I/SUP 2/L. CHIL circuits are well suitable for large-scale integration (LSI) and are technologically compatible to all circuits fabricated in a standard buried collector (SBC) process.     

Fast feedthrough logic: a high performance logic family for GaAs

A GaAs dynamic logic family using the feedthrough evaluation concept is presented in this paper. Feedthrough logic (FTL) allows the outputs to be partially generated before the input signals arrive. A modified version of this logic, where the function and its complement are implemented in a differential structure, is also introduced. In an FTL gate, the logic outputs are reset to low during the high phase of the clock and evaluated during the low phase of the clock. Resetting to low alleviates the problems of charge sharing and leakage current associated with the other GaAs dynamic logic families. FTL logic functions can be cascaded in a domino-like fashion without a need for the intervening inverters. We employ this novel concept to design several arithmetic circuits. We compare a 4-bit ripple carry adder in FTL with the other published works in terms of device count, area, delay, clock rate and power consumption. The results demonstrate that FTL is the simplest, the fastest, and consumes least power. In addition, our FTL design compares very well with the standard CMOS technology. FTL gates are fully compatible with direct coupled field-effect transistor logic (DCFL), and therefore, can be included in a DCFL standard cell library for improving cell-based ASIC performance. To match the high-speed of the FTL combinational blocks, we present a single-ended latch for pipelining the FTL blocks. Comparisons with the other published results demonstrate the superior performance of our dynamic latch.     

NCMOS: a high performance CMOS logic

CMOS has been the mainstay technology for VLSI design for the last several years. However, recently, BiCMOS technology has been proposed for speed critical applications. In this paper we propose a new circuit structure called NCMOS, which employs a low Vt NMOS transistor in place of the bipolar transistor, and provides significantly higher speed than a conventional CMOS design. This is realized at the cost of only one extra masking step, compared to 4-5 extra masks for a full BiCMOS process     

抗噪声和工艺参数浮动的高性能多输入多米诺或门设计

A novel technique using a keeper with a simultaneous low supply voltage and low body voltage is proposed to improve the overall performance of high fan-in OR gates without modifying the physical dimensions of the keeper.Simulation results of a 16-input domino OR gate using 45 nm CMOS technology show that the proposed technique could trade off between a high power/speed efficient operation and the robustness to noise effectively.Also,a Monte Carlo analysis indicates that the proposed domino OR gate is more robust to parameter variation compared to a conventional domino OR gate.     

Robustness aware high performance high fan-in domino OR logic design

A novel technique using a keeper with a simultaneous low supply voltage and low body voltage is proposed to improve the overall performance of high fan-in OR gates without modifying the physical dimensions of the keeper. Simulation results of a 16-input domino OR gate using 45 nm CMOS technology show that the proposed technique could trade off between a high power/speed efficient operation and the robustness to noise effectively.Also, a Monte Carlo analysis indicates that the proposed domino OR gate is more robust to parameter variation compared to a conventional domino OR gate.     

GaAs pseudodynamic latched logic for high performance processorcores

A novel GaAs logic family, pseudodynamic latched logic (PDLL), is presented in this paper. It is composed of a dynamic circuit where the logic is performed and a static latch whose function is to permanently refresh the stored data on a dynamic node. Because of this hybrid structure, PDLL takes advantage of both static and dynamic families and thus, permits implementation of very complex structures with good speed-area power tradeoff. Moreover, the inclusion of the latch permits this class of logic family to be highly efficient for pipelined systems working even at high temperature without loss of data due to leakage currents. Barrel-shifters, programmable logic arrays (PLA's), and carry lookahead adders (CLA's) were verified by simulations demonstrating its feasibility for the development of high-performance very large scale integration (VLSI) systems     

Low voltage high performance E/D MOS logic

The letter describes a high performance MOS technology which produces both enhancement- and depletion-mode devices on the same substrate without using ion implantation. The enhancement mode devices, with 1?2 ?m channel lengths, can be realised using regular optical lithography and simple processing techniques.     

Circularly polarized patch antenna with simultaneously wide frequency tuning range and high gain performance

A tunable circularly polarized square patch antenna with parasitic elements is designed for a wide frequency tuning range and high gain characteristics. The proposed antenna is constructed by one main patch and four semi-elliptic parasitic units. By loading four varactor diodes and adjusting their capacitance values, the tunable feature is performed to reallocate the corresponding working frequency. Moreover, the diagonal corners of the antenna are cut and loaded with varactor diodes, which provide the appropriate perturbation between the two orthogonality modes of the antenna, so as to ensure the circular polarization characteristic in the entire operating tuning band. The experimental results demonstrate that the reflection coefficient and axial ratio are less than −13 dB and 3 dB, respectively. The proposed antenna features a relatively wide continuously tuning range of 24% within 1.9-2.3 GHz and a stable gain of over 7 dBi with a radiation efficiency of above 85%.     

Current gain and cutoff frequency falloff at high currents

A theoretical and experimental study of the effects of high-level injection of carriers into a reverse-biased collector-base junction has been performed. Two models which describe the high-current behavior of the junction space-charge region are discussed. The first deals with the formation of a current-induced base region at space-charge-limited current densities. The second model assumes that two-dimensional effects are predominant; at current densities corresponding to the onset of space-charge-limited current, lateral injection of carriers takes place. These phenomena were studied experimentally using silicon double-diffused transistor structures. The existence of space-charge-limited current in the reverse-biased collector depletion layer manifests itself in significant changes in the ac and dc parameters of the transistor. In particular, it is shown that the cutoff frequency (fT) and large-signal current gain (hFE) begin to decrease rapidly with increasing current at the onset of the space-charge limitation. A comparison of experimental results with predictions of the above theories indicates that, while both the formation of a current-induced base region and lateral injection do take place, the latter mechanism controls conventional device performance.     

Measurement of gain in an optically-excited mixture of D2and Ar at high density

Collision-induced gain of approximately 0.015 cm^-1at a wavelength near 4 μm has been measured in a high-density mixture of D2and Ar. The D2molecules were excited by collision-induced absorption of radiation from a hydrogen-fluoride laser.     

一种宽频带高增益高极化隔离度的微带天线

设计了一种具有高增益、高极化隔离特性的宽频带层叠型E形天线。通过激励E形辐射体,获得双峰谐振回路,并在E形天线上方附加寄生元,构成了三峰谐振特性,从而取得较传统E形天线更宽的频带;通过E形天线在低端激励的双电流路径保证了天线在频率低端的高增益特性,而天线本身的辐射体尺寸保证了频率高端的高增益特性。采用Ansoft HFSS电磁仿真软件对提出的天线模型仿进行优化,依次在1.75 GHz,2.1 GHz,2.475 GHz形成了三个谐振峰值;在1.7~2.54 GHz内驻波比≤1.5,其相对带宽达40％,在1.7~2.5 GHz频带内增益＞8 dBi,且具有低达-55 dB的优异交叉极化特性。     

Design and simulation of an ultra-low power high performance CMOS logic: DMTGDI

An ultra-low power, high speed dual mode CMOS logic family called DMTGDI is introduced. This logic family takes over and improves main characteristics of Gate Diffusion Input (GDI) and Dual Mode Logic (DML). Simulations have been performed in 90 nm CMOS on a single bit full adder. DMTGDI shows 60% performance improvement over conventional DML, and significant reduction of power-delay product (PDP), of about 95% in static mode, and 75% in dynamic mode. Monte Carlo simulations reveal that DMTGDI is more robust under process variation comparing to conventional DML. Post layout simulation demonstrates negligible effect of parasitic elements on performance of the single bit adder.     

Small-signal gain performance of the permeable base transistor at EHF

The small-signal amplifier performance at 40.5 GHz is reported for a GaAs permeable base transistor (PBT) having a base grating of 3200-Å periodicity and 1-mm periphery. The device was embedded in a microstrip circuit with appropriate matching networks and biased for optimal small-signal gain with Vbe= 0.2 V, Vce= 2.0 V, and Ice= 59 mA. The prototype amplifier achieved 11 dB of stable gain at 40.5 GHz. The circuit design was facilitated by the moderate impedance levels and highly unilateral nature of the PBT.     

低增益准分子激光阈值和最佳透射率的研究

低增益、宽带脉冲准分子激光阈值及最佳透射率条件和激光泵浦脉宽有密切关系.提出了以激光四能级系统近似模拟准分子激光跃迁辐射系统,在其速率方程的基础上研究低增益脉冲准分子激光阈值和最佳透射率的条件,并给出了其在不同增益脉宽情况下的统一的激光阈值和最佳透射率条件,所取得的结论在相应的实验研究结果中得到证实。     

Spatial nonuniformity of 4H-SiC avalanche photodiodes at high gain

We report spatial nonuniformity of responsivity of 4H-SiC avalanche photodiodes at high gain (M > 1000) that results from variation in the doping density. Two-dimensional raster scans show a steady decline laterally across the device. The direction in which the spatial response decreases is the same as that of increasing breakdown voltage on the wafer.     

A single-chip adaptive delta modulator with optimum performance

This paper describes the design of a high performance Si-Gate CMOS LSI circuit for an Adaptive Delta Modulation System (ADM). The circuit design is based on 4 μ design rules. The size of the die is approximately 25 mm² and the circuit operates synchronously under the control of an 8 MHz two phase non-overlapping clock. A fault tolerant scheme is used at the comparator section for reliability improvement purposes. The adaptation logic of the system is based on the algorithm introduced in [2] where a rigorous proof is provided for showing the optimality of the algorithm in terms of performance. This paper demonstrates the feasibility of implementing this algorithm with a single chip adaptive delta modulator.     

Stacked microstrip antenna with wide bandwidth and high gain

A stacked microstrip antenna with two parasitic elements, one of which increases the impedance bandwidth and the other which enhances the gain, has been investigated experimentally. The effects of each parasitic element have been clarified as well as the characteristics of the stacked three-element antenna and the design procedure for the stacked microstrip antenna have been described