纳米晶非挥发性存储器研究进展

介绍了纳米晶非挥发性存储器的发展状况和基本工作原理,比较了纳米晶非挥发性存储器所涉及到的各种不同的电荷输运机制,系统介绍了纳米晶非挥发性存储器在纳米晶材料设计、纳米晶晶体生长控制方法、隧穿/控制介质层工程和新型存储器器件结构等方面的一些最新研究进展,对纳米晶非挥发性存储器的研究趋势进行了展望。     

Au纳米晶MIS结构存储性能研究

从器件结构和能带的角度分析了提高非易失性存储器性能的可能途径,建立了纳米晶浮栅结构的存储模型,并在模型中考虑了量子限制效应对纳米晶存储性能的影响.基于模型计算,分析了纳米晶材料、高k隧穿介质材料及其厚度对纳米晶浮栅结构存储性能的影响.同时,制作了MIS结构(Si/ZrO2/Au Ncs/SiO2/Al)的存储单元,针对该存储单元的电荷存储能力和电荷保持特性进行测试,并对测试结果进行分析.     

金属纳米晶存储器件数据保持能力建模与验证

金属纳米晶存储器件具有低功耗、高速读写特性及较高的可靠性,因此近年来在非易失存储器研究领域备受关注.对比分析讨论了量子限制效应与库仑阻塞效应对金属纳米晶费密能级的影响后,发现库仑阻塞效应会严重削弱器件数据保持能力.在综合考虑金属纳米晶量子限制效应和库仑阻塞效应的基础上,提出了金属纳米晶存储器件数据保持能力分析模型,并通过与相关研究文献的实验数据对比分析,证实了本模型的合理性.     

Using different work function nanocrystal materials to improve the retention characteristics of nonvolatile memory devices

Recently, nanocrystal nonvolatile memory (NVM) devices have attracted great research interest. Taking into account the effect of work function to account for the better retention characteristics for nanocrystals with larger work function, utilizing different work functions Au, W and Si as floating gates is proposed and comparatively studied in this paper. It was found that Au nanocrystals have better retention characteristic than W and Si. The good retention characteristic of the Au nanocrystal device is due to the larger work function and it is difficult for electrons captured by Au nanocrystal to escape from them. So, the retention characteristic of the device can be improved by using larger work function nanocrystal materials.     

Ge/Si复合纳米结构电荷存储特性的模拟研究

这一研究工作模拟计算了 Ge/ Si复合纳米结构 MOSFET存储器的擦写和存储时间特性。结果表明 ,Ge/ Si复合纳米结构存储器在低压下即可实现 μs和 ns量级编程。与 Si纳米结构存储器相比 ,由于 Ge/ Si复合势阱的作用 ,器件的电荷保留时间提高了 3～ 5个量级 ,有效地解决了快速擦写编程与长久存储之间的矛盾 ,使器件的性能得到明显改善。     

Self-aligned silicon-on-insulator nano flash memory device

This paper reports on the fabrication of a silicon-on-insulator nano flash memory device based on the differential oxidation rate of silicon resulting from gradients in the arsenic doping concentration. The key processes involved are the formation of the desired arsenic doping profile, electron beam lithography and wet oxidation. The resulting device is a triangular-channel MOSFET with a nanocrystal floating gate embedded in the gate oxide. The length, width and height of the nanocrystal are 10, 10 and 20 nm, respectively. As long as the control gate voltage does not exceed ±2V, the device behaves like a thin and narrow P-channel MOSFET. When a voltage of −5 or +5 V is applied to the control gate at room temperature, holes are injected into the floating gate or removed from it, respectively. This effect induces a persistent shift of the threshold voltage of the device, which acts as a miniature EEPROM.     

Electrical characteristics of nano-crystal Si particles for nano-floating gate memory

In these days, the researches of non-volatile memory device using nano-crystal(NC)-Si are actively progressing to replace flash memory devices. Many kinds of non-volatile memory devices such as phase-change(P)-RAM, resistance(Re)-RAM, polymer(Po)-RAM, and nano-floating gate memory(NFGM) are being studied. In this work, we study NFGM device in which information is memorized by storing electrons in silicon nanocrystal. The NFGM device has shown great promise for ultra-dense high-endurance memory device for low-power applications [S. Tiwari, et al., Appl. Phys. Lett. 68 (1996) 1377], and it is able to fabricate 1T-type device. Thus, the NFGM is considered to replace existing flash memory device. Non-volatile memory device has been fabricated by using NC-Si particles. The NC-Si particles have broad size range of 1-5 nm and an average size of 2.7 nm, which are sufficiently small to indicate the quantum effect for silicon. The memory window has been analyzed by C-V characteristic of NC-Si particles. V_d-I_d and V_g-I_d characteristics of the fabricated device have also been measured.     

3-D computer simulation of single-electron charging in siliconnanocrystal floating gate flash memory devices

The operation of a silicon nanocrystal quantum-dot based flash memory device is simulated numerically with emphasis on energy and charge quantization in the quantum-dot. The simulation involves the self-consistent solution of three-dimensional (3-D) Poisson and Schrodinger-like equations, with the Slater rule for determining the charging voltage. We also compute the capacitance-voltage characteristics of the device and derive the threshold voltage, V_T , variation with single-electron charging as a function of design parameters     

基于硅纳米晶的非挥发存储器制备与存储特性

硅纳米晶非挥发存储器由于其卓越的性能以及与传统工艺的高度兼容性,近来引起高度关注。采用两步低压化学气相淀积(LPCVD)生长方式制备硅纳米晶(Si-NC),该方法所制备的硅纳米晶具有密度高、可控性好的特点,且完全兼容于传统CMOS工艺。在此基础上制作四端硅纳米晶非挥发存储器,该器件展示出良好的存储特性,包括10 V操作电压下快速地擦写,数据保持特性的显著提高,以及在105次擦写周期以后阈值电压(Vt)飘移低于10%的良好耐受性。该器件在未来高性能非挥发存储器应用上极具潜质。     

Nanocrystal Memory Cell Integration in a Stand-Alone 16-Mb nor Flash Device

We report on the full process integration of nanocrystal (NC) memory cells in a stand-alone 16-Mb NOR Flash device. The Si NCs are deposited by chemical vapor deposition on a thin tunnel oxide, whose surface is treated with a low thermal budget process, which increases NC density and minimizes oxide degradation. The device fabrication has been obtained by means of conventional Flash technology, which is integrated with the CMOS periphery with high- and low-voltage transistors and charge pump capacitors. The memory program and erase threshold voltage distributions are well separated and narrow. The voltage distribution widths are related to NC sizes and dispersion, and bigger NCs can induce a cell reliability weakness. An endurance issue is also related to the use of an oxide/nitride/oxide dielectric which acts as a charge trapping layer, causing a shift in the program/erase window and a distribution broadening during cycling.     

Inside Front Cover: Three‐Dimensionally Ordered Gold Nanocrystal/Silica Superlattice Thin Films Synthesized via Sol–Gel Self‐Assembly (Adv. Funct. Mater. 7/2006)

The synthesis of three‐dimensionally ordered, transparent gold‐nanocrystal (NC)/silica superlattice thin films using the self‐assembly (by spin‐coating) of water‐soluble gold nanocrystal micelles and soluble silica is reported by Fan and co‐workers on p. 891. The robust, 3D NC/silica superlattice films are of interest for the development of collective optical and electronic phenomena, and, importantly, for the integration of NC arrays into device architectures. Nanocrystals and their ordered arrays hold many important applications in fields such as catalysis, surface‐enhanced Raman spectroscopy based sensors, memory storage, and electronic and optical nanodevices. Herein, a simple and general method to synthesize ordered, three‐dimensional, transparent gold nanocrystal/silica superlattice thin films by self‐assembly of gold nanocrystal micelles with silica or organosilsesquioxane by spin‐coating is reported. The self‐assembly process is conducted under acidic sol–gel conditions (ca. pH 2), ensuring spin‐solution homogeneity and stability and facilitating the formation of ordered and transparent gold nanocrystal/silica films. The monodisperse nanocrystals are organized within inorganic host matrices as a face‐centered cubic mesostructure, and characterized by transmission electron spectroscopy and X‐ray diffraction.     

A novel 2-T structure memory device using a Si nanodot for embedded application

Performance and reliability of a 2 transistor Si nanocrystal nonvolatile memory(NVM) are investigated. A good performance of the memory cell has been achieved,including a fast program/erase(P/E) speed under low voltages,an excellent data retention(maintaining for 10 years) and good endurance with a less threshold voltage shift of less than 10%after 10~4 P/E cycles.The data show that the device has strong potential for future embedded NVM applications.     

Hafnium silicate nanocrystal memory using sol-gel-spin-coating method

The authors fabricate the hafnium silicate nanocrystal memory for the first time using a very simple sol-gel-spin-coating method and 900 /spl deg/C 1-min rapid thermal annealing (RTA). From the TEM identification, the nanocrystals are formed as the charge trapping layer after 900 /spl deg/C 1-min RTA and the size is about 5 nm. They demonstrate the composition of nanocrystal is hafnium silicate from the X-ray-photoelectron-spectroscopy analysis. They verify the electric properties in terms of program/erase (P/E) speed, charge retention, and endurance. The sol-gel device exhibits the long charge retention time of 10/sup 4/ s with only 6% charge loss, and good endurance performance for P/E cycles up to 10/sup 5/.     

可嵌入式应用的新型2T结构硅纳米晶存储器

本文研究了2T硅纳米晶非挥发存储器性能和可靠性。存储单元可获得良好性能,包括低压操作下快速的擦写速度,卓越的数据保持特性（保持10年）,良好的耐受性（10k次擦写周期以后小于10%的阈值电压飘移）。数据表明了此器件在未来嵌入式非挥发存储应用的可能性。     

Ionising radiation and electrical stress on nanocrystal memory cell array

In this work, we have investigated the effects of irradiation and electrical stress of nanocrystal memory cell arrays. Heavy ion irradiation has no or negligible immediate effects on the nanocrystal MOSFET characteristics, and on the programming window of the cells. By electrically stressing irradiated device, we see accelerated oxide breakdown similar to that previously observed on conventional thin gate oxide MOS capacitors, but no appreciable change of the degradation kinetics in terms of programming window closure and shift. The accelerated breakdown is ascribed to the degradation of the oxide–nitride–oxide (ONO) layer used as control oxide after exposure to ionising irradiation.     

金属纳米晶快闪存储器研究进展

金属纳米晶具有态密度高、费米能级选择范围广以及无多维载流子限制效应等优越性,预示着金属纳米晶快闪存储器在下一代闪存器件中具有很好的应用前景。从金属纳米晶存储器的工作原理、纳米晶的制备方法、以及新型介质材料和电荷俘获层结构等方面,对金属纳米晶存储器近年来的研究进展进行了总结。     

Numerical investigation of characteristics of p-channel Ge/Si hetero-nanocrystal memory

The characteristics of p-channel Ge/Si hetero-nanocrystal based MOSFET memory have been investigated numerically considering mainly hole-tunneling process. Owing to the advantages of a compound potential well and a higher band offset at the valence band compared with the p-channel Si nanocrystal based MOSFET memory and n-channel Ge/Si hetero-nanocrystal based MOSFET memory, the present structure shows that the holes have a longer retention time. Moreover, this kind of device keeps on having high-speed writing/erasing in the direct-tunneling ultrathin oxide regime. It would be expected to solve the contradictory problem between high-speed programming and long retention, therefore, the performance would be substantially improved.     

Asymmetric electric field enhancement in nanocrystal memories

The electrostatic model for nanocrystal memories is used to illustrate the fundamental difference of the metal nanocrystal memory in low-voltage program/erase (P/E) operations in comparison with semiconductor nanocrystal and trap-based memories. Due to repulsion of potential contours inside conductors, the metal nanocrystals will significantly enhance the electric field between the nanocrystal and the sensing channel set up by the control gate bias and, hence, can achieve much higher efficiency in low-voltage P/E. On the other hand, the electric field originated from the stored charge will only be slightly different for metal and semiconductor nanocrystal cases. We presented the electrostatic models by both approximate analytical formulation and three-dimensional numerical simulation in a nanocrystal array. Operations of P/E and read disturbance were analyzed for the cases of homogeneous charge distribution, silicon, and metal nanocrystals. In the P/E condition of +5/-5 V, the metal nanocrystal memory offers around 1.6 times higher peak fields than Si counterparts and almost three times higher than that from the one-dimensional model for homogeneous charge distribution. The field enhancement factor suggests the design criteria of oxide thickness, nanocrystal size, and spacing. The advantage of asymmetric field enhancement of metal nanocrystals will be even more prominent when high-K gate dielectrics are employed.     

纳米晶浮栅存储器的模拟、制备和电学特性

介绍了在纳米晶浮栅存储器数据保持特性方面的研究工作,重点介绍了纳米晶材料的选择与制备和遂穿介质层工程。研究证明,金属纳米晶浮栅存储器比半导体纳米晶浮栅存储器具有更好的电荷保持特性。并且金属纳米晶制备方法简单,通过电子束蒸发热退火的方法就能够得到质量较好的金属纳米晶,密度约4×1011cm-2,纳米晶尺寸约6～7nm。实验证明,高介电常数隧穿介质能够明显改善浮栅存储器的电荷保持特性,所以在引入金属纳米晶和高介电常数遂穿介质之后,纳米晶浮栅存储器可能成为下一代非挥发性存储器的候选者。