Optimization of a 250-GHz Schottky tripler using novel fabricationand design techniques

A technique for optimizing a diode waveguide mount for millimeter- and submillimeter-wave applications has been developed. The structure consists of a planar rectangular radiator for which an accurate derivation of impedance is available. The planar radiating probe incorporates the diode contacting tip, is fabricated integrally with the microstrip filter, and is used in a 230-290-GHz frequency tripler. Modification of the tripler using the described technique resulted in an improvement of ≈6 dB in available output power, compared to the authors' previous results for this device. Device output power exceeds 8.5 mW at 245 GHz for an input power of 132 mW. The best flange-to-flange efficiency (in excess of 11%) was achieved at 3.3-mW output power. This technique was then applied to a waveguide mount, incorporating two diodes contacted in parallel, so that greater input power could be handled. This resulted in a tripler with a maximum output power of 15 mW at 270 GHz for an input of 280 mW     

A 200 GHz tripler using a single barrier varactor

The authors present results for a tripler to 200 GHz using a single barrier varactor (SBV). The performance of the tripler, over an output frequency range from 186 to 207 GHz, has been measured in a crossed waveguide mount. The theoretical performance of the device and the tripler mount have been calculated using large signal analysis. An overall efficiency of 2% was achieved with efficiency at the device of above 5%. A comparison of theoretical and measured results and a discussion of various losses in the mount and the varactor are also presented     

V波段变容管三倍频器

设计制作了一个从22.8GHz到68.4GHz的封装型变容管三倍频器,这是目前报导的用封装型变容管所达到的最高频率。该倍频器在结构上实现了空闲回路独立可调,从而提高了倍频效率。当频率为22.8GHz而输入功率为47mW时,最大三次谐波输出为4.9mW,最大倍频效率为10.4％,输出频率至少在2GHz的范围内倍频效率不低于7％。     

Hybrid Integrated Frequency Multipliers at 300 and 450 GHz

300- and 450-GHz band doublers and triplers using thin-film integrated circuits have been developed. The multipliers are built with a GaAs honeycomb-type Schottky barrier diode designed to have a high cutoff frequency and transitions from microstrip to rectangular waveguides. A 450-GHz band tripler delivered an output power of -11.2 dBm with a corresponding conversion loss of 19.4 dB. The output power of the 300-GHz band doubler was -3.6 dBm, and its minimum conversion loss was 10.7dB. The hybrid integrated frequency multipliers are useful as solid-state sources in the short-millimeter-wave and subrnillimeter-wave regions.     

Fabrication and performance of InP-based heterostructure barriervaractors in a 250-GHz waveguide tripler

High-performance InGaAs-InAlAs-AlAs heterostructure barrier varactors (HBV's) have been designed, fabricated, and RF tested in a 250-GHz tripler block. The devices with two barriers stacked on the same epitaxy are planar integrated with coaxial-, coplanar-, and strip-type configurations. They exhibit state-of-the-art capacitance voltage characteristics with a zero-bias capacitance C₃⁰ of 1 fF/μm² and a capacitance ratio of 6:1. Experiments in a waveguide tripler mount show a 9.8-dBm (9.55-mW) output power for 10.7% conversion efficiency at 247.5 GHz. This is the highest output power and efficiency reported from an HBV device at J-band (220-325 GHz)     

G-band metamorphic HEMT-based frequency multipliers

Two monolithic G-band active frequency multipliers have been designed and fabricated using coplanar-waveguide technology. The monolithic microwave integrated circuits are a frequency tripler for an output frequency of 140 GHz and a 110-220-GHz frequency doubler. The tripler demonstrates a maximum conversion gain of -11 dB for an input power of 9 dBm, whereas the doubler achieves a conversion gain of -7 dB for a 2.5-dBm input signal. The circuits have been realized using two InAlAs/InGaAs-based metamorphic high electron-mobility transistor processes with different gate lengths of 100 and 50 nm, respectively.     

A 56–65 GHz Injection-Locked Frequency Tripler With Quadrature Outputs in 90-nm CMOS

A sub-harmonic injection-locked tripler multiplies a 20-GHz differential input to 60-GHz quadrature (I/Q) output signals. The tripler consists of a two-stage ring oscillator driven by a single-stage polyphase input filter and 50-$Omega$ I and Q-signal output buffers. Each gain stage incorporates a hard limiter to triple the input frequency for injection locking and a negative resistance cell with two positive feedback loops to increase gain. Regenerative peaking is also used to optimize the gain/bandwidth performance of the 50-$Omega$ output buffers. Fabricated in 90-nm CMOS, the tripler has a free-running frequency of 60.6 GHz. From a 0-dBm RF source, the measured output lock range is 56.5–64.5 GHz, and the measured phase noise penalty is 9.2 $ pm 1~$dB with respect to a 20.2-GHz input. The $0.3times 0.3~ hbox{mm}^{2}$ tripler (including passives) consumes 9.6 mW, while the output buffers consume 14.2 mW, all from a 1-V supply.      

Millimeter Wavelength Frequency Multipliers

Mechanically tuneable millimeter wavelength frequency doublers typically exhibiting 10-percent conversion efficiency at any output frequency in the range 100-260 GHz have been fabricated. Output power varies from 10 mW at 100 GHz to 6 mW at 260 GHz, with a fixed tuned instantaneous 1-dB bandwidth typically 5 percent of the center frequency. A frequency tripler to 215-GHz output frequency is also described. For this device, a mechanically tuneable 3-dB bandwidth of 210 to 240 GHz was obtained, with a peak conversion efficiency of 6 percent at 4.8-mW output power.     

A Novel Quasi-Optical Frequency Multiplier Design for Millimeter and Submillimeter Wavelengths

This paper describes a novel design for millimeter and sub-millimeter wavelength varactor frequency triplers and quadruplers. The varactor diode is coupled to the pump source via waveguide and stripline impedance matching and filtering structures. Output power at the various harmonics of the pump frequency is fed to quasi-optical filtering and tuning elements. The low-loss quasi-optical structures enable near-optimum control of the impedances seen by the varactor diode at the idler and output frequencies, resulting in efficient high-order harmonic conversion. A minimum efficiency of 4 percent with 30-mW input power has been obtained for a tripler operating between 200 and 280 GHz, with a peak efficiency of 8 percent between 250 and 280 GHz. Another tripler, designed for the 260-350-GHz band, gave a minimum conversion efficiency of 3 percent with 30-mW input power, with a peak efficiency of 5 percent at 340 GHz.     

A Silicon 60-GHz Receiver and Transmitter Chipset for Broadband Communications

A 0.13-mum SiGe BiCMOS double-conversion superheterodyne receiver and transmitter chipset for data communications in the 60-GHz band is presented. The receiver chip includes an image-reject low-noise amplifier (LNA), RF-to-IF mixer, IF amplifier strip, quadrature IF-to-baseband mixers, phase-locked loop (PLL), and frequency tripler. It achieves a 6-dB noise figure, -30 dBm IIP3, and consumes 500 mW. The transmitter chip includes a power amplifier, image-reject driver, IF-to-RF upmixer, IF amplifier strip, quadrature baseband-to-IF mixers, PLL, and frequency tripler. It achieves output P_1dB of 10 to 12dBm, P_sat of 15 to 17 dBm, and consumes 800 mW. The chips have been packaged with planar antennas, and a wireless data link at 630 Mb/s over 10 m has been demonstrated     

Single barrier varactors for submillimeter wave power generation

Theoretical work on single barrier varactor (SBV) diodes indicates that the efficiency of a tripler with a SBV diode has a maximum for a considerably smaller capacitance variation than previously thought. SBV diodes based on GaAs, InGaAs and InAs have been fabricated and their DC properties have been tested. Detailed modeling of the carrier transport properties of the SBV device is carried out in two steps. First, the semiconductor transport equations are solved simultaneously, using a finite difference scheme in one dimension. Second, the calculated I -V and C-V characteristics are used by a multiplier simulator to calculate the optimum impedances and output powers at the frequencies of interest. The authors have developed an analysis technique which complements the harmonic balance technique. Simulations for a case study of a 750-GHz multiplier show that InAs diodes perform favorably compared to GaAs diodes     

A 540-640-GHz high-efficiency four-anode frequency tripler

We report on the design and performance of a broad-band, high-power 540-640-GHz fix-tuned balanced frequency tripler chip that utilizes four planar Schottky anodes. The suspended strip-line circuit is fabricated with a 12-/spl mu/m-thick support frame and is mounted in a split waveguide block. The chip is supported by thick beam leads that are also used to provide precise RF grounding. At room temperature, the tripler delivers 0.9-1.8 mW across the band with an estimated efficiency of 4.5%-9%. When cooled to 120 K, the tripler provides 2.0-4.2 mW across the band with an estimated efficiency of 8%-12%.     

基于石英基片的二毫米频段三倍频器的研制

介绍了一个基于石英基片的二毫米频段三倍频器.采用反向并联变容二极管对结构实现倍频.建立了该二极管管对的等效电路模型并提取了模型参数.设计实现的倍频器输入为K型接头结构,输出为WR-8波导结构.获得的倍频器在输出频率为112.8～118.2 GHz范围内,输出功率大于0 dBm,最大输出功率超过2 dBm,最小倍频损耗为...     

Design of a W-band Frequency Tripler for Broadband Operation Based on a Modified Equivalent Circuit Model of GaAs Schottky Varistor Diode

This paper presents the design and experimental results of a W-band frequency tripler with commercially available planar Schottky varistor diodes DBES105a fabricated by UMS, Inc. The frequency tripler features the characteristics of tunerless, passive, low conversion loss, broadband and compact. Considering actual circuit structure, especially the effect of ambient channel around the diode at millimeter wavelength, a modified equivalent circuit model for the Schottky diode is developed. The accuracy of the magnitude and phase of S21 of the proposed equivalent circuit model is improved by this modification. Input and output embedding circuits are designed and optimized according to the corresponding embedding impedances of the modified circuit model of the diode. The circuit of the frequency tripler is fabricated on RT/Rogers 5880 substrate with thickness of 0.127 mm. Measured conversion loss of the frequency tripler is 14.5 dB with variation of ±1 dB across the 75?~?103 GHz band and 15.5?~?19 dB over the frequency range of 103?~?110 GHz when driven with an input power of 18 dBm. A recorded maximum output power of 6.8 dBm is achieved at 94 GHz at room temperature. The minimum harmonics suppression is greater than 12dBc over 75?~?110 GHz band.     

225–255-GHz InP DHBT Frequency Tripler MMIC Using Complementary Split-Ring Resonator

In this paper, a novel design of frequency tripler monolithic microwave integrated circuit (MMIC) using complementary split-ring resonator (CSRR) is proposed based on 0.5-μm InP DHBT process. The CSRR-loaded microstrip structure is integrated in the tripler as a part of impedance matching network to suppress the fundamental harmonic, and another frequency tripler based on conventional band-pass filter is presented for comparison. The frequency tripler based on CSRR-loaded microstrip generates an output power between ?8 and ?4 dBm from 228 to 255 GHz when the input power is 6 dBm. The suppression of fundamental harmonic is better than 20 dBc at 77–82 GHz input frequency within only 0.15?×?0.15 mm² chip area of the CSRR structure on the ground layer. Compared with the frequency tripler based on band-pass filter, the tripler using CSRR-loaded microstrip obtains a similar suppression level of unwanted harmonics and higher conversion gain within a much smaller chip area. To our best knowledge, it is the first time that CSRR is used for harmonic suppression of frequency multiplier at such high frequency band.     

A Broadband CMOS Frequency Tripler Using a Third-Harmonic Enhanced Technique

A third harmonic enhanced technique is proposed to implement a broadband and low-phase-noise CMOS frequency tripler. It nonlinearly combines a pair of differential fundamental signals to generate deep cuts at the peaks of the fundamental waveform, resulting in a strong third harmonic frequency output. This mechanism has inherent suppression on the fundamental and the other harmonics so that only a low-Q high-pass filter on the lossy silicon substrate is applied at the output to further reject the fundamental and the second harmonic frequencies, in contrast to the high-Q filters used in most of the previous tripler designs. The fabricated circuit using 0.18 m CMOS technology is compact and has an input frequency range from 1.7 GHz to 2.25 GHz, or an output frequency range from 5.1 GHz to 6.75 GHz, resulting in about 28% frequency bandwidth. The optimum conversion loss from the tripler is 5.6 dB (27.5% efficiency) at an input power of 2 dBm. The suppressions for the fundamental, second and fourth harmonics in the measurement are better than 11 dB, 9 dB, and 20 dB within an input power range from 2 dBm to 7 dBm.     

一种毫米波宽锁定范围的注入锁定倍频器设计

为提高毫米波段倍频器在低功耗下的工作带宽,采用IHP130 nm SiGe BiCMOS 工艺,设计了一种采用双端注入技术的毫米波宽锁定范围注入(DEI)锁定倍频器。该注入锁定倍频器主要由谐波发生器和带有尾电流源的振荡器构成,由巴伦产生差分信号双端注入振荡器的形式提高三次谐波注入强度,使其在E、W 等波段输出宽锁定范围和良好相位噪声性能的三倍频信号。仿真结果表明,注入锁定倍频器在工作电压为1.2 V,输入信号功率为0 dBm时,其锁定范围在57~105 GHz 内。在相同工作电压和输入信号功率下,输入频率为32 GHz 时,一次、二次和四次谐波抑制大于20 dBc,功耗为9.1 mW。     

210270GHz短毫米波3倍频器

本文描述了频率复盖210270GHz的3倍频器,最高的倍频效率为5.8%,最大的输出功率发生在输入功率为3050mW的范围内。3倍频器是由基波输入波导WR-12、输出波导WR-4和两波导之间的同轴低通滤波器组成。     

Improved frequency tripler with integrated single-barrier varactor

A monolithically integrated frequency tripler on semi-insulating GaAs substrate with a 210 GHz output frequency is presented. The measured conversion efficiency using a GaAs-GaAlAs single-barrier varactor is 13.5%, with an output power of >10 mW