Trap energetic and spatial localization in buried-gate 6H-SiC JFETsby means of numerical device simulation

Deep levels with activation energies up to 0.59 eV have been revealed in buried gate, n-channel 6H-silicon carbide JFETs, by means of capacitance- and current-mode deep level transient spectroscopy. Numerical device simulations of the drain-current transients following a gate-to-source voltage step have enabled us to localize the different deep levels both energetically and spatially     

High-transconductance β-SiC buried-gate JFETs

An improved performance buried-gate SiC junction field-effect transistor (JFET) has been fabricated and evaluated. This structure uses an n-type β-SiC film epitaxially grown by chemical vapor deposition on the Si(0001) face of a p-type 6H α-SiC single crystal. The current in the n-type channel was modulated using the p-type α-SiC layer as a gate. Electron-beam-evaporated Ti/Au was utilized as an ohmic contact to the n-type β-SiC layer, and thermally evaporated Al was used to contact the p-type gate. A maximum DC transconductance of 20 mS/mm was obtained, which is the highest reported for a β-SiC FET structure. The experimental data are analyzed using a charge-control model. Calculated drain current versus drain voltage characteristics for a buried-gate JFET are in good agreement with experimental data     

Detailed investigation of n-channel enhancement 6H-SiC MOSFETs

Basic MOSFET parameters like inversion layer mobility, threshold voltage, intrinsic mobility reduction factor and interface state density extracted from the subthreshold slope were examined in detail for 6H-SiC enhancement-mode n-channel MOSFETs. The inversion layer mobility and the threshold voltage were determined as a function of substrate doping concentration as well as device temperature. The interface state density was studied for different substrate doping concentrations. The inversion layer mobility was found to decrease strongly with increasing substrate doping. In contrast to earlier reports the inversion layer mobility decreases also with temperature. Furthermore, the threshold voltage depends more pronounced on substrate doping and temperature than theoretically expected. The interface state density extracted from the subthreshold slope increases significantly with substrate doping concentration. All these phenomena are consistently interpreted by the classical MOSFET behavior which is extended by acceptor like interface states. These states are located close to the conduction band and exhibit a density increasing drastically toward the band edge     

800 V 4H-SiC RESURF-type lateral JFETs

This letter proposes to show that a lateral switching device has some unique advantages, including little dependence on substrate defects, low on-resistance, and a simple design of heat radiation. A reduced surface field (RESURF) type SiC-JFET is one of candidate devices for an electric or hybrid automobile application. Small RESURF-type SiC-JFETs with gate width of 200 /spl mu/m and a blocking voltage of 800 V were fabricated. The fabrication and characteristics of the devices are described and discussed.     

存在界面陷阱的n沟6H-SiC MOSFET温度特性研究

利用二维器件仿真软件 MEDICI建立了具有指数分布界面陷阱的 n沟 6H-Si C场效应晶体管的结构模型和物理模型 ,通过模拟研究 ,分析和讨论了界面陷阱对器件阈值电压、跨导及其温度特性的影响。     

Accumulation-layer electron mobility in n-channel 4H-SiC MOSFETs

Accumulation-layer electron mobility in n-channel depletion-mode metal oxide semiconductor field effect transistors (MOSFETs) fabricated in 4H-SiC was investigated using Hall-measurements. The accumulation-layer mobility showed a smooth transition from the bulk value (~350 cm²/V-s) in the depletion regime into accumulation (~200 cm²/V-s). In contrast, the field-effect mobility, extracted from the transconductance, was found to be much lower (~27 cm²/V-s), due to the trapping of the field-induced carriers by interface states. Though the current in depletion/accumulation-mode MOSFETs can be high due to the contribution of bulk conduction resulting in low on-resistance, carrier trapping will cause the transconductance to be low in the accumulation regime     

Lateral n-channel inversion mode 4H-SiC MOSFETs

Advances in MOS devices on silicon carbide (SiC) have been greatly hampered by the low inversion layer mobilities. In this paper, the electrical characteristics of lateral n-channel MOSFETs fabricated on 4H-SiC are reported for the first time. Inversion layer electron mobilities of 165 cm²/V·s in 4H-SiC MOSFETs were measured at room temperature. These MOSFETs were fabricated using a low temperature deposited oxide, with subsequent oxidation anneal, as the gate dielectric     

Design criteria of high-Voltage lateral RESURF JFETs on 4H-SiC

Integrated power electronics on SiC have great potential in future power electronics applications. In this paper, a novel vertical channel lateral junction field-effect transistor structure with reduced surface electric field effect is proposed for the first time on 4 H-SiC to address existing challenges in lateral power devices on SiC. Based on an experimentally proven channel design, the detailed design procedure of such a device has been investigated. Design criteria to optimize device forward blocking as well as conduction characteristics are studied. Parameter tolerance and design windows are discussed considering practical issues in device fabrication. Designs that will lead to an optimized tradeoff between device breakdown voltage and specific on-resistance are shown. With an 8-/spl mu/m-long drift region, a 1535-V breakdown voltage and 3.24 m/spl Omega//spl middot/cm/sup 2/ specific on-resistance can be achieved. This represents a figure-of-merit of 737 MW/cm/sup 2/, about 100 times higher than that of the best normally off lateral power devices reported in the literature. The proposed device can be an attractive candidate for power integrated circuit on SiC.     

Reduced trapping effects and improved electrical performance in buried-gate 4H-SiC MESFETs

Surface effects on the current instability of 4H-SiC MESFETs were studied by comparing different surface structures. The current instability phenomenon was illustrated by bias sweeping methods and current recovery time measurements. A reduction in the current instability was observed for gate-recessed and buried-gate devices compared to the nonrecessed and channel-recessed devices. In addition, the buried-gate devices were found to have higher current density and breakdown voltage compared to the gate-recessed devices, resulting from their shorter effective gate length and lower electric field distribution under the gate, respectively. With high saturation current, high breakdown voltage, and much reduced surface effects, the buried-gate structure is a candidate for high-power SiC MESFETs.     

Fabrication of 4H-SiC n-channel IGBTs with ultra high blocking voltage

Owing to the conductivity modulation of silicon carbide (SiC) bipolar devices,n-channel insulated gate bipolar transistors (n-IGBTs) have a significant advantage over metal oxide semiconductor field effect transistors (MOSFETs) in ultra high voltage (UHV) applications.In this paper,backside grinding and laser annealing process were carried out to fabricate 4H-SiC n-IGBTs.The thickness of a drift layer was 120 μm,which was designed for a blocking voltage of 13 kV.The n-IGBTs carried a collector current density of 24 A/cm2 at a power dissipation of 300 W/cm2 when the gate voltage was 20 V,with a differential specific on-resistance of 140 mΩ·cm2.     

Fabrication and characterization of field-plated buried-gate SiC MESFETs

Silicon carbide (SiC) MESFETs were fabricated using a standard SiC MESFET structure with the application of the "buried-channel" and field-plate (FP) techniques in the process. FPs combined with a buried-gate are shown to be favorable concerning output power density and power-added efficiency (PAE), due to higher breakdown voltage and decreased output conductance. A very high power density of 7.8 W/mm was measured on-wafer at 3 GHz for a two-finger 400-/spl mu/m gate periphery SiC MESFET. The PAE for this device was 70% at class AB bias. Two-tone measurements at 3 GHz /spl plusmn/ 100 kHz indicate an optimum FP length for high linearity operation.     

4H-SiC MESFET表面陷阱效应研究

借助ISE TCAD,对4H-SiC MESFET进行二维数值模拟,研究分析了表面陷阱对直流和瞬态特性的影响。数值模拟表明,在直流特性上,由于表面陷阱电荷引入附加耗尽层,器件饱和电流下降,输出电阻增加,夹断电压向右偏移,跨导降低;在瞬态特性上,表面陷阱电荷的缓慢变化引起了栅延迟的出现。能级靠近价带、密度较高时,表面陷阱效应越明显。     

Al掺杂6H-SiC铁磁性研究(英文)

使用物理气象沉积法生长了轻Al掺杂6H-SiC样品,并使用超导量子干涉磁强计(SQUID)对无腐蚀及腐蚀后的样品进行了测试,发现了腐蚀后的样品在室温下表现出铁磁性。经过计算,样品磁信号并非来源于腐蚀剂KOH及K2CO3。同时腐蚀后的样品形貌表明杂质聚集在腐蚀后的缺陷附近从而形成了一定的铁磁性,因此缺陷被腐蚀放大是样品形成铁磁性的主要原因。     

6H-SiC MOS场效应晶体管的研制

报道了多晶硅栅 6 H- Si C MOS场效应器件的制造工艺和器件性能。 6 H- Si C氧化层的SIMS分析说明在氧化过程中 ,多余的 C以 CO的形式释放 ,铝元素逸出极少 ,氧化层中因有较多的铝而正电荷密度较大 ,Si C的氧化速率和掺杂类型关系不大。器件漏电流都有很好的饱和特性 ,最大跨导为 0 .36 m S/ mm ,沟道电子迁移率约为 14cm2 / V.s,但串联电阻效应明显。     

High-voltage double-implanted power MOSFET's in 6H-SiC

We report on the first planar high-voltage MOSFET's in 6H-SiC. A double-implant MOS (DIMOS) process is used. The planar structure ameliorates the high-field stressing encountered by SiC UMOS transistors fabricated by other groups. Blocking mode operation of up to 760 V is demonstrated, which is nearly three times higher than previously reported operating voltages for SiC MOSFET's     

Activation of nitrogen implants in 6H-SiC

We have studied the effect of anneal time and temperature on activation of high-dose nitrogen implants into 6H-SiC. At a fixed anneal temperature, a strong dependence on anneal time is seen. For short anneals, the resistivity initially decreases with anneal time. After a minimum resistivity is reached, resistivity increases with further anneal. The optimum anneal time for minimum resistiv-ity increases as anneal temperature is reduced. Successful activation has been achieved at temperatures as low as 900°C.     

Elevated temperature nitrogen implants in 6H-SiC

Elevated temperature (700°C) N ion implantations were performed into 6H-SiC in the energy range of 50 keV-4 MeV. By analyzing the as-implanted depth distributions, the range statistics of the N⁺ in 6H-SiC have been established over this energy range. Annealing at 1500 and 1600°C for 15 min resulted in Rutherford backscattering spectrometry scattering yields at the virgin crystal level, indicating a good recovery of the crystalline quality of the material without any redistribution of the dopant. A maximum electron concentration of 2 × 10¹⁹ cm⁻³, at room temperature, has been measured even for high-dose implants. The p-n junction diodes made by N ion implantation into a p-type substrate have a forward turn-on voltage of 2.2 V, an ideality factor of 1.90, and a reverse breakdown voltage of 125 V with nA range leakage current for -10 V bias at room temperature. By probing many devices on the same substrate we found uniform forward and reverse characteristics across the crystal.     

Low frequency noise in 6H-SiC MOSFET's

The noise spectra for n-channel, depletion-mode MOSFETs fabricated in 6H-SiC material were measured from 1-10⁵ Hz at room temperature. Devices were biased in the linear regime, where the noise spectra was found to be dependent upon the drain-to-source bias current density. At a drain-to-source current of 50 μA for MOSFETs with a W/L of 400 μm/4 μm, the measured drain-to-source noise power spectral density was found to be A/(f^λ), with A being 2.6×10^-12 V², and λ being between 0.73 and 0.85, indicating a nonuniform spatial trap density skewed towards the oxide-semiconductor interface. The measured Hooge parameter (α_H) was 2×10^-5. This letter represents the first reported noise characterization of 6H-SiC MOSFET's     

Electrical characterization of annealed Ti/TiN/Pt contacts onN-type 6H-SiC epilayer

We report results of the electrical characteristics of in vacuo deposited Ti/TiN/Pt contact metallization on n-type 6H-SiC epilayer as function of impurity concentration in the range of 3.3×10¹⁷ cm^-3 to 1.9×10¹⁹ cm^-3. The as-deposited contacts are rectifying, except for the highly doped sample. Only the lesser doped remains rectifying after samples are annealed at 1000°C between 0.5 and 1 min in argon. Bulk contact resistance ranging from factors of 10^-5 to 10^-4 Ω-cm² and Schottky barrier height in the range of 0.54-0.84 eV are obtained. Adhesion problems associated with metal deposition on pre-processed titanium is not observed, leading to excellent mechanical stability. Auger electron spectroscopy (AES) reveals the out diffusion of Ti-Si and agglomeration of Ti-C species at the epilayer surface. The contact resistance remains appreciably stable after treatment in air at 650°C for 65 h. The drop in SBH and the resulting stable contact resistance is proposed to be associated with the thermal activation of TiC diffusion barrier layer on the 6H-SiC epilayer during annealing     

High field-effect mobility in n-channel Si face 4H-SiC MOSFETs with gate oxide grown on aluminum ion-implanted material

We report investigations of Si face 4H-SiC MOSFETs with aluminum (Al) ion-implanted gate channels. High-quality SiO/sub 2/-SiC interfaces are obtained both when the gate oxide is grown on p-type epitaxial material and when grown on ion-implanted regions. A peak field-effect mobility of 170 cm/sup 2//V/spl middot/s is extracted from transistors with epitaxially grown channel region of doping 5/spl times/10/sup 15/ cm/sup -3/. Transistors with implanted gate channels with an Al concentration of 1/spl times/10/sup 17/ cm/sup -3/ exhibit peak field-effect mobility of 100 cm/sup 2//V/spl middot/s, while the mobility is 51 cm/sup 2//V/spl middot/s for an Al concentration of 5/spl times/10/sup 17/ cm/sup -3/. The mobility reduction with increasing acceptor density follows the same functional relationship as in n-channel Si MOSFETs.