Design and Evaluation of Adiabatic Arithmetic Units

Adiabatic design is an attractive approach to reducingenergy consumption in VLSI circuits after exhausting the potentialof conventional energy-saving techniques. Despite the plethoraof adiabatic logic architectures that have been proposed in recentyears, several practical considerations in the design of nontrivialadiabatic circuits remain largely unexplored. Moreover, it isstill unclear whether adiabatic circuits of significant sizeand complexity can achieve substantial savings in energy dissipationover corresponding conventional designs. We recently designedseveral low-power arithmetic units using a dual-rail adiabaticlogic design style. We also designed static CMOS versions ofthese units and compared their energy dissipation with theircorresponding adiabatic designs. In this paper we describe ourimplementations, discuss architecture and logic-level issuesrelated to our adiabatic designs, and present the findings ofour empirical comparison. Our results suggest that adiabaticlogic can be used for the implementation of relatively complexVLSI circuits that dissipate significantly less energy than theircorresponding CMOS designs.     

Low-Power Tunable Analog Circuit Blocks Based on Nanoscale Double-Gate MOSFETs

We illustrate unique examples of low-power tunable analog circuits built using independently driven nanoscale DG-MOSFETs, where the top gate response is altered by application of a control voltage on the bottom gate. In particular, we provide examples for a single-ended CMOS amplifier pair, a Schmitt trigger circuit and a operational transconductance amplifier C filter, circuit blocks essential for low-noise high-performance integrated circuits for analog and mixed-signal applications. The topologies and biasing schemes explored here show how the nanoscale DG-MOSFETs may be used for efficient, tolerant and smaller circuits with tunable characteristics.     

High-Precision Differential-Input Buffered and External Transconductance Amplifier for Low-Voltage Low-Power Applications

Recently, the demand for low-voltage low-power integrated circuits design has grown dramatically. For battery-operated devices both the supply voltage and the power consumption have to be lowered in order to prolong the battery life. This paper presents an attractive approach to designing a low-voltage low-power high-precision differential-input buffered and external transconductance amplifier, DBeTA, based on the bulk-driven technique. The proposed DBeTA possesses rail-to-rail voltage swing capability at a low supply voltage of ±400 mV and consumes merely 62 μW. The proposed circuit is a universal active element that offers more freedom during the design of current-, voltage-, or mixed-mode applications. The proposed circuit is particularly interesting for biomedical applications requiring low-voltage low-power operation capability where the processing signal frequency is limited to a few kilohertz. An oscillator circuit employing a minimum number of active and passive components has been described in this paper as one of many possible applications. The circuit contains only a single active element DBeTA, two capacitors, and one resistor, which is very attractive for integrated circuit implementation. PSpice simulation results using the 0.18 μm CMOS technology from TSMC are included to prove the unique results.     

A 0.8-V 0.25-mW Current-Mirror OTA With 160-MHz GBW in 0.18-μm CMOS

A low-voltage low-power CMOS operational transconductance amplifier (OTA) with near rail-to-rail output swing is presented in this brief. The proposed circuit is based on the current-mirror OTA topology. In addition, several circuit techniques are adopted to enhance the voltage gain. Simulated from a 0.8-V supply voltage, the proposed OTA achieves a 62-dB dc gain and a gain-bandwidth product of 160 MHz while driving a 2-pF load. The OTA is designed in a 0.18-mum CMOS process. The power consumption is 0.25 mW including the common-mode feedback circuit     

Low-power CMOS/BiCMOS drivers and receivers for on-chipinterconnects

Novel low-voltage swing CMOS and BiCMOS driver/receiver circuits for low-power VLSI applications are proposed. Interconnect wire drivers with low output signal swing are employed. Special receivers provide single and double level conversion while minimizing the total driver/receiver transmission delay. These level converters have no DC power dissipation. At 3.3 V power supply voltage, the proposed circuits consume less power without delay penalty. The power saving is observed to be as high as 30%. At lower supplies further power and delay improvements are observed     

A 200 MHz pipelined multiplier using 1.5 V-supply multiple-valuedMOS current-mode circuits with dual-rail source-coupled logic

A new multiple-valued current-mode MOS integrated circuit is proposed for high-speed arithmetic systems at low supply voltage. Since a multiple-valued source-coupled logic circuit with dual-rail complementary inputs results in a small signal-voltage swing while providing a constant driving current, the switching speed of the circuit is improved at low supply voltage. As an application to arithmetic systems, a 200 MHz 54×51-b pipelined multiplier using the proposed circuits with a 1.5 V supply voltage is designed with a 0.8-μm standard CMOS technology. The performance of the proposed multiplier is evaluated to be about 1.4 times faster than that of a corresponding binary implementation under the normalized power dissipation. A prototype chip is also fabricated to confirm the basic operation of the multiple-valued arithmetic circuit     

An all-band TV tuner IC with 10-GHz 100-V mixed analog/digital Sibipolar technology

An all-band TV tuner IC with an on-chip PLL and a high-voltage output stage is developed. The use of a self-aligned bipolar technology called high-voltage compatible sidewall base contact structure (HV-SICOS) allows the integration of 1-GHz analog circuits, 1-GHz low-power ECL-I²L PLL circuits, and a 0.5- to 30-V tuning diode bias current on the same chip. The analog block has a VCO and mixer pair for the VHF/CATV and another pair for the UHF bands, a UHF input amplifier, an IF amplifier, and a VCO signal switching circuit. To suppress the digital noise level for mixed analog/digital mode operation, the PLL is constructed with high-speed ECL circuits for divide-by-four and dual modulus prescalers, and low-power I²L circuits. An isolation area is placed between the analog and digital blocks. Conversion gain of 24 dB for VHF/CATV and 33 dB for UHF, a noise figure of 10 dB, and 1% cross modulation of 95 dB-μV are obtained. This IC operates with a total power dissipation of 200 mW on a 3-mm×4-mm chip     

LSI implementation of a low-power 4×4-bit array two-phase clocked adiabatic static CMOS logic multiplier

As the density and operating speed of complementary metal oxide semiconductor (CMOS) circuits increases, dynamic power dissipation has become a critical concern in the design and development—of personal information systems and large computers. The reduction of supply voltage, node capacitance, and switching activity are common approaches used in conventional CMOS. In adiabatic switching circuits, the current flow through transistors can be significantly reduced by ensuring uniform charge transfer over the entire available time. This paper presents the simulation of this current in two-phase clocked adiabatic static CMOS logic (2PASCL) and conventional CMOS. From the SPICE simulations, at transition frequencies from 1 to 12 MHz, a 4×4-bit array 2PASCL multiplier shows a maximum reduction in power dissipation of 77% relative to that of a static CMOS. The measurement results of a 4×4-bit array 2PASCL multiplier demonstrate a 57% reduction compared to a 4×4-bit array two-phase clocked adiabatic dynamic CMOS logic (2PADCL). These results indicate that 2PASCL technology can be advantageous when applied to low-power digital devices operated at low frequencies, such as radio-frequency identification (RFID) tags, smart cards, and sensors.     

An Adaptive Biased Single-Stage CMOS Operational Amplifier with a Novel Rail-to-Rail Constant-<Emphasis Type="Italic">g</Emphasis><Subscript><Emphasis Type="Italic">m</Emphasis></Subscript> Input Stage

Using rail-to-rail (R-R) swing analog circuits has become almost mandatory in the design of low supply voltage circuits. In this paper, a new architecture for constant-g_m rail-to-rail input stages is presented. The design features a less than 5% deviation in g_m over the entire range of the input common-mode voltage. Furthermore, a new structure for folded cascode amplifier based on the use of a floating current source is presented. By employing these techniques, a low-power operational amplifier (op-amp) with 100 MHz unity-gain bandwidth, 106 dB gain, 60^∘ phase margin, 2.65 V swing, and 6.4 nV/✓Hz input-referred noise with rail-to-rail input common-mode range is realized in a 0.8 μ m CMOS technology. This amplifier dissipates 10 mW from a 3 V power supply.     

Adiabatic-CMOS/CMOS-adiabatic logic interface circuit

This paper describes the design of an adiabatic-CMOS/CMOS-adiabatic logic interface circuit for a group of low-power adiabatic logic families with a similar clocking scheme. The circuit provides interfacing between several recently proposed low-power adiabatic logic circuits and traditional digital CMOS circuits. One advantage of this design is that it is insensitive to clock overlap. With the proposed interface circuit, both adiabatic and CMOS logic circuits are able to co-exist on a single chip, taking advantage of the strengths of each approach in the design of low power systems.     

A 2-V 10.7-MHz CMOS limiting amplifier/RSSI

This paper presents low-voltage low-power CMOS circuit design techniques for an intermediate frequency (IF) limiting amplifier and received signal strength indicator (RSSI). The architecture of the limiting amplifier and RSSI employed is determined by the optimal power consumption for a specified speed, overall gain, and accuracy. Each gain cell of the limiting amplifier employs folded diode load for low-voltage operation. Offset is reduced by a cross-connected source-coupled pair offset subtractor that is along the signal path. Full-wave current rectification and summation are employed in the RSSI circuit to achieve high precision while maintaining low voltage and low power. Using a single 2-V supply voltage, measured results demonstrate the input dynamic range is larger than 75 dB for 10.7-MHz IF application. The prototype occupies an active area of 0.4 mm² using a 0.6-μm digital CMOS technology. The power dissipation is 6.2 mW     

Low-Power Area-Efficient Pipelined A/D Converter Design Using a Single-Ended Amplifier

This paper presents a new scheme of a low-power area-efficient pipelined A/D converter using a single-ended amplifier. The proposed multiply-by-two single-ended amplifier using switched capacitor circuits has smaller DC bias current compared to the conventional fully-differential scheme, and has a small capacitor mismatch sensitivity, allowing us to use a smaller capacitance. The simple high-gain dynamic-biased regulated cascode amplifier also has an excellent switching response. These properties lead to the low-power area-efficient design of high-speed A/D converters. The estimated power dissipation of the 10-b pipelined A/D converter is less than 12 mW at 20 MSample/s.     

A Locally Adaptive Multimode Photodetector Circuit

Photodetection circuits form the first stage of the artificial image acquisition process. The image acquisition circuits discussed in this paper pertain to circuits fabricated in a standard CMOS process. Such circuits offers advantages such as random access to a pixel, faster readout, integration of processing circuitry on the same die, low voltage and low power dissipation, and lower cost over the conventional Charge Coupled Device (CCD) process. We describe a new locally adaptive multimode photodetector circuit. The advantages of the circuit are local adaptation, wide dynamic range, excellent sensitivity, and large output voltage swing. The circuit was fabricated in the 2 CMOS process through MOSIS. Simulation and experimental results of the circuit are given.     

Exploring the design space of mixed swing quadrail for low-powerdigital circuits

This paper describes and explores the design space of a mixed voltage swing methodology for lowering the energy per switching operation of digital circuits in standard submicron complementary metal-oxide-semiconductor (CMOS) fabrication processes. Employing mixed voltage swings expands the degrees of freedom available in the power-delay optimization space of static CMOS circuits. In order to study this design space and evaluate the power-delay tradeoffs, analytical polynomial formulations for power and delay of mixed swing circuits are derived and HSPICE simulation results are presented to demonstrate their accuracy. Efficient voltage scaling and transistor sizing techniques based on our analytical formulations are proposed for optimizing energy/operation subject to target delay constraints; up to 2.2× improvement in energy/operation is demonstrated for an ISCAS'85 benchmark circuit using these techniques. Experimental results from HSPICE simulations and measurements from an And-Or-Invert (AO1222) test chip fabricated in the Hewlett-Packard 0.5 μm process are presented to demonstrate up to 2,92× energy/operation savings for optimized mixed swing circuits compared to static CMOS     

A low-power 16×16-b parallel multiplier utilizingpass-transistor logic

This paper describes a low-power 16×16-b parallel very large scale integration multiplier, designed and fabricated using a 0.8 μm double-metal double-poly BiCMOS process. In order to achieve low-power operation, the multiplier was designed utilizing mainly pass-transistor (PT) logic circuits. The inherent nonfull-swing nature of PT logic circuits were taken full advantage of, without significantly compromising the speed performance of the overall circuit implementation. New circuit implementations for the partial product generator and the partial-product addition circuitry have been proposed, simulated, and fabricated. Experimental results showed that the worst case multiplication time of the test chip is 10.4 ns at a supply voltage of 3.3 V, and the average power dissipation is 38 mW at a frequency of 10 MHz     

Low-voltage, low-power BiCMOS digital circuits

A new BiCMOS buffer circuit, for low-voltage, low-power environment, is presented. The circuit is based on the deep submicron technology and utilizes the parasitic bipolar transistors associated with the CMOS structure. The analysis, simulations and SPICE results confirm the functionality of the circuit and its speed and voltage swing superiority, compared with conventional BiCMOS circuits at low supply voltages     

0.4-V bulk-driven differential-difference amplifier

A new solution for an ultra-low-voltage, low-power, bulk-driven fully differential-difference amplifier (FDDA) is presented in the paper. Simulated performance of the overall FDDA for a 50 nm CMOS process and supply voltage of 0.4 V, shows dissipation power of 31.8 μW, the open loop voltage gain of 58.6 dB and the gain-bandwidth product (GBW) of 2.3 MHz for a 20 pF load capacitance. Despite the very low supply voltage, the FDDA exhibits rail-to-rail input/output swing. The circuit performance has also been tested in two applications; the differential voltage follower and the second-order band-pass filter, showing satisfactory accuracy and dynamic range.     

A 3.5-ns, 500-mW, 16-kbit BiCMOS ECL RAM

A 16-kbit BiCMOS ECL SRAM with a typical address access time of 3.5 ns and 500-mW power dissipation was developed. The RAM was fabricated using half-micrometer, triple-poly, and triple-metal BiCMOS technology. The fast access time with moderate power dissipation has been achieved using new circuit techniques: a grounded-gate, nonlatching-type level converter with a wired-OR predecoder and a direct column sensing scheme having a cascode differential amplifier. As a result of extensive use of high-speed bipolar ECL circuits with self-aligned bipolar transistors, the RAM attains high-speed performance without degrading the low-power BiCMOS RAM characteristics.<>     

A wide-band high-voltage monolithic amplifier

A monolithic amplifier capable of 80-V swing and 1.7-V/NS slew rate has been fabricated using standard integrated circuit techniques. The amplifier is intended for capacitive loads such as in electrostatic deflection applications. The totem-pole technique is combined with active feedback to produce this large voltage swing without excessive power consumption. A new output circuit linked with a floating current source is used to supply large accurate positive and negative charging currents over a large dynamic range. The amplifier voltage range is extendable by increasing the degree of stacking in the totem-pole arrangement.     

Phase assignment for synthesis of low-power domino circuits

High performance circuit techniques such as domino logic have migrated from the microprocessor world into more mainstream ASIC designs but domino logic comes at a heavy cost in terms of total power dissipation. A set of results related to automated phase assignment for the synthesis of low-power domino circuits is presented: (1) it is demonstrated that the choice of phase assignment at the primary outputs of a circuit can significantly impact lower dissipation in the domino block, and (2) a method to determine a phase assignment that minimises power consumption in the final circuit implementation is proposed. Preliminary experimental results on a mixture of public domain benchmarks and real industry circuits show potential power savings as high as 34% over the minimum area realisation of the logic. Furthermore, the low-power synthesised circuits still meet timing constraints