Electrodepositing ZnxMnyOz alloys from zinc oxide to manganese oxide

Electrodeposition has emerged as a practical and simple method to synthesise semiconductor materials under different forms, thin films or nanostructured layers. This work reports on the cathodic electrodeposition of ZnMnO thin layers using both zinc and manganese chlorides as precursors. The composition of thin films can be varied from binary zinc oxide to manganese oxide varying the Mn/(Mn+Zn) ratio between 0 and 1. The composition of Zn_xMn_yO_z films was obtained by energy dispersive spectroscopy. Zn_1−xMn_xO films with Mn/Zn ratio less than 10% exhibit a crystalline wurtzite structure typical of ZnO fully oriented in the (0 0 2) direction. Higher Mn content leads to deformation of the ZnO lattice and the wurtzite structure is no longer maintained. X-ray photoelectron spectroscopy points out that Mn₃O₄ tends to be deposited when a high Mn/Zn ratio is used in the starting solution. Magnetic measurements on films with Mn/(Zn+Mn) ratio near 1 reveal magnetic characteristics similar to Mn₃O₄ compounds. The transmission spectra of Zn_xMn_yO_z show the typical absorption edge of crystalline ZnO while the wurtzite structure is maintained and it shifts to higher wavelengths when Mn content increases.     

Integration of HfxTayN metal gate with SiO2 and HfOxNy gate dielectrics for MOS device applications

Interaction of Hf_xTa_yN metal gate with SiO₂ and HfO_xN_y gate dielectrics has been extensively studied. Metal-oxide-semiconductor (MOS) device formed with SiO₂ gate dielectric and Hf_xTa_yN metal gate shows satisfactory thermal stability. Time-of-flight secondary ion mass spectroscopy (TOF-SIMS) analysis results show that the diffusion depths of Hf and Ta are less significant in SiO₂ gate dielectric than that in HfO_xN_y. Compared to HfO_xN_y gate dielectric, SiO₂ shows better electrical properties, such as leakage current, hysteresis, interface trap density and stress-induced flat-band voltage shift. With an increase in post metallization annealing (PMA) temperature, the electrical characteristics of the MOS device with SiO₂ gate dielectric remain almost unchanged, indicating its superior thermal and electrical stability.     

Electroluminescence of SrAl2O4:Eu phosphor

The SrAl₂O₄:Eu²⁺ phosphor powders have been synthesized by sol-gel process. Electroluminescent (EL) properties of the SrAl₂O₄:Eu²⁺ phosphor were investigated using a convenient thick film device. Green light emitting at a peak of 508 nm was obtained when driven by sine alternating current (AC). The color coordinate of the emission was x=0.148 and y=0.635. Luminance-voltage and afterglow characteristics of the SrAl₂O₄:Eu²⁺ EL devices were studied. The results show that SrAl₂O₄:Eu²⁺ can be used as green phosphor for EL displays.     

Annealing effect on physical and electrical characteristics of thin HfO2, HfSixOy and HfOyNz films on Si

We report the effect of annealing on electrical and physical characteristics of HfO₂, HfSi_xO_y and HfO_yN_z gate oxide films on Si. Having the largest thickness change of 0.3 nm after post deposition annealing (PDA), HfO_yN_z shows the lowest leakage current. It was found for both as-grown and annealed structures that Poole-Frenkel conduction is dominant at low field while Fowler-Nordheim tunneling in high field. Spectroscopic ellipsometry measurement revealed that the PDA process decreases the bandgap of the dielectric layers. We found that a decreasing of peak intensity in the middle HfO_yN_z layer as measured by Tof-SIMS may suggest the movement of N toward the interface region between the HfO_yN_z layer and the Si substrate during the annealing process.     

Kinetic Studies of the Interfacial Reaction of the Ba2YCu3O6+x Superconductor with a CeO2 Buffer

Interfacial reactions between the Ba₂YCu₃O_6+x superconductor and the CeO₂ buffer layers employed in coated conductors have been modeled experimentally by investigating the kinetics of the reaction between Ba₂YCu₃O_6+x films and CeO₂ substrates. At 810°C, the Ba₂YCu₃O_6+x -CeO₂ join within the BaO-Y₂O₃-CeO₂-CuO _x quaternary system is nonbinary, thereby establishing the phase diagram topology that governs the Ba₂YCu₃O_6+x /CeO₂ reaction. At a mole ratio of Ba₂YCu₃O_6+x :CeO₂ of 40:60, a phase boundary was found to separate two four-phase regions. On the Ba₂YCu₃O_6+x -rich side of the join, the four-phase region consists of Ba₂YCu₃O_{6 +x} , Ba(Ce_1−z Y _z )O_3−x , BaY₂CuO₅, and CuO _x ; on the CeO₂ rich side, the four phases were determined to be Ba(Ce_1−z Y _z ) O_3−x , BaY₂CuO₅, CuO _x and CeO₂. The Ba₂YCu₃O_6+x /CeO₂ reaction is limited by solid-state diffusion, and the reaction kinetics obey the parabolic rule, x = Kt ^1/2, where x = thickness of the reaction layer, t = time, and K = a constant related to the rate constant; K was determined to be 1.6 × 10⁻³ μm/s^1/2 at 790°C and 4.7 × 10⁻³ μm/s^1/2 at 830°C. The activation energy for the reaction was determined to be E _act = 2.67 × 10⁵ J/mol using the Arrhenius equation.     

First investigation of metal–insulator–metal (MIM) capacitor using Pr2O3 dielectrics

Metal–insulator–metal (MIM) capacitors with Pr₂O₃ as high-k material have been investigated for the first time. We varied the thickness of the Pr₂O₃ layers as well as the bottom electrode material. The layers are characterised using X-ray photoelectron spectroscopy (XPS), X-ray diffraction (XRD), transmission electron microscopy (TEM) and secondary ion mass spectroscopy (SIMS). Preliminary information on the interaction of water with the films was obtained from XPS and ab initio pseudopotential calculations. The electrical characterisation shows that Pr₂O₃ MIM capacitors can provide higher capacitance densities than Si₃N₄ MIM capacitors while still maintaining comparable voltage coefficients of capacitance. The Pr₂O₃ dielectric material seems to be suitable for use in silicon RF applications.     

Effect of a silicon nitride buffer layer on the electrical properties of tantalum pentoxide films

Ta₂O₅ films with a buffer layer of silicon nitride of various thicknesses were deposited on Si substrate by reactive sputtering and submitted to annealing at 700 °C in nitrogen atmosphere. The microstructure and the electrical properties of thin films were studied. It was found that with a buffer layer of silicon nitride the electrical properties of Si_xN_y/Ta₂O₅ film can be improved than Ta₂O₅ film. When the thickness of the buffer layer was 3 nm, the Si_xN_y/Ta₂O₅ film has the highest dielectric constant of 27.4 and the lowest leakage current density of 4.61 × 10⁻⁵ A/cm² (at −1 V). For the Si_xN_y (3 nm)/Ta₂O₅ film, the conduction mechanism of leakage current was also analyzed and showed four types of conduction mechanisms at different applied voltages.     

Superior suppression of gate current leakage in Al<Subscript>2</Subscript>O<Subscript>3</Subscript>/Si<Subscript>3</Subscript>N<Subscript>4</Subscript> bilayer-based AlGaN/GaN insulated gate heterostructure field-effect transistors

AlGaN/GaN-based metal-insulator-semiconductor heterostructure field-effect transistors (MIS-HFETs) with Al₂O₃/Si₃N₄ bilayer as insulator have been investigated in detail, and compared with the conventional HFET and Si₃N₄-based MIS-HFET devices. Al₂O₃/Si₃N₄ bilayer-based MIS-HFETs exhibited much lower gate current leakage than conventional HFET and Si₃N₄-based MIS devices under reverse gate bias, and leakage as low as 1×10⁻¹¹ A/mm at −15 V has been achieved in Al₂O₃/Si₃N₄-based MIS devices. By using ultrathin Al₂O₃/Si₃N₄ bilayer, very high maximum transconductance of more than 180 mS/mm with ultra-low gate leakage has been obtained in the MIS-HFET device with gate length of 1.5 μm, a reduction less than 5% in maximum transconductance compared with the conventional HFET device. This value was much smaller than the more than 30% reduction in the Si₃N₄-based MIS device, due to the employment of ultra-thin bilayer with large dielectric constant and the large conduction band offset between Al₂O₃ and nitrides. This work demonstrates that Al₂O₃/Si₃N₄ bilayer insulator is a superior candidate for nitrides-based MIS-HFET devices.     

Mechanism of selective Si3N4 etching over SiO2 in hydrogen-containing fluorocarbon plasma

This paper describes the mechanism of selective Si₃N₄ etching over SiO₂ in capacitively-coupled plasmas of hydrogen-containing fluorocarbon gas, including CHF₃, CH₂F₂ and CH₃F. The etch rate of Si₃N₄ and SiO₂ is investigated as a function of O₂ percentage in all plasma gases. Addition of O₂ in feed gases causes plasma gas phase change especially H density. The SiO₂ etch rate decreases with increase of O₂ percentage due to the decline of CF_x etchant. The Si₃N₄ etch rate is found to be strong correlated to the H density in plasma gas phase. H can react with CN by forming HCN to reduce polymer thickness on Si₃N₄ surface and promote the removal of N atoms from the substrate. Thus the Si₃N₄ etch rate increases with H intensity. As a result, a relative high selectivity of Si₃N₄ over SiO₂ can be achieved with addition of suitable amount of O₂ which corresponds to the maximum of H density.     

Materials characterization of WNxCy, WNx and WCx films for advanced barriers

A ternary WN_xC_y system was deposited in a thermal ALD (atomic layer deposition) reactor from ASM at 300 °C in a process sequence using tungsten hexafluoride (WF₆), triethyl borane (TEB) and ammonia (NH₃) as precursors. The WC_x layers were deposited by a novel ALD process at a process temperature of 250 °C. The WN_x layers were deposited at 375 °C using bis(tert-butylimido)-bis-(dimethylamido)tungsten (^tBuN)₂(Me₂N)₂W (imido-amido) and NH₃ as precursors. WN_x grows faster on plasma enhanced chemical vapor deposition (PECVD) oxide than WC_x does on chemical oxide. WN_xC_y grows better on PECVD oxide than on thermal oxide, which is opposite of what is seen for WN_x. In the case of the ternary WN_xC_y system, the scalability towards thinner layers and galvanic corrosion behavior are disadvantages for the incorporation of the layer into Cu interconnects. ALD WC_x based barriers have a low resistivity, but galvanic corrosion in a model slurry solution of 15% peroxide (H₂O₂) is a potential problem. Higher resistivity values are determined for the binary WN_x layers. WN_x shows a constant composition and density throughout the layer.     

Analysis of interface trap density of metal-oxide-semiconductor devices with Pr2O3 gate dielectric using conductance method

In this study, the interface trap density of metal-oxide-semiconductor (MOS) devices with Pr₂O₃ gate dielectric deposited on Si is determined by using a conductance method. In order to determine the exact value of the interface trap density, the series resistance is estimated directly from the impedance spectra of the MOS devices. Subsequently, the dispersion characteristics are numerically analyzed on the basis of a statistical model. Lastly, the process-dependent interface trap density of Pr₂O₃ is evaluated. It is concluded that high-pressure annealing and a superior quality interfacial SiO₂ layer are of crucial importance for achieving a sufficiently low interface trap density.     

Characterization of a rapid thermal anneal TiNxOy/TiSi2 contact barrier

In this paper, the physical and electrical properties of a TiN_xO_y/TiSi₂ dual layer contact barrier are reported. The TiN_xO_y/TiSi₂ barrier was formed by rapidly annealing a Ti thin film on Si in an N₂ ambient. During this process, the Ti film surface reacts with N₂ to form a TiN_xO_y skin layer and the bulk of the Ti film reacts with Si to form an underlying TiSi₂ layer. The influences of rapid thermal anneal (RTA) conditions on the TiN_xO_y layer were investigated by varying the RTA temperature from 600 to 1100° C and cycle duration from 30 to 100 s. It is found that the resulting TiN_xO_y and TiSi₂ layer thicknesses are dependent on RTA temperature and the starting Ti thickness. For a starting Ti thickness of 500Å, 150Å thick TiN_xO_y and 800Å thick TiSi₂ are obtained after an RTA at 900° C for 30 s. The TiN_xO_y thickness is limited by a fast diffusion of Si into Ti to form TiSi₂. When a Ti film is deposited on SiO₂, Ti starts to react with SiO₂ from 600° C and a significant reduction of the SiO₂ thickness is observed after an RTA at 900° C. The resulting layer is composed of a surface TiN_xO_y layer followed by a complex layer of titanium oxide and titanium suicide. In addition, when Ti is depos-ited on TiSi₂, thicker TiN_xO_y and TiSi₂ layers are obtained after RTA. This is because the TiSi₂ layer retards the diffusion of Si from the underlying substrate into the Ti layer. NMOSFETs were fabricated using the TiN_xO_y/TiSi₂ as a contact barrier formed by RTA at 900° C for 30 s and a significant reduction of contact resistance was obtained. In addition, electromigration test at a high current density indicated that a significant improvement in mean time to failure (MTF) has been obtained with the barrier.     

Influence of the deposition parameters on the growth of SiGe nanocrystals embedded in Al2O3 matrix

Si_1−xGe_x nanocrystals (NCs), embedded in Al₂O₃ matrix, were fabricated on Si (100) substrates by RF-magnetron sputtering technique with following annealing procedure at 800 °C, in nitrogen atmosphere. The presence of Si_1−xGe_x NCs was confirmed by grazing incidence X-ray diffraction (GIXRD), grazing incidence small angle X-ray scattering (GISAXS) and Raman spectroscopy. The influence of the growth conditions on the structural properties and composition of Si_1−xGe_x NCs inside the alumina matrix was analyzed. Optimal conditions to grow Si_1−xGe_x (x∼ 0.8) NCs sized between 3 and 4 nm in Al₂O₃ matrix were established.     

Fabrication of high-Ge-fraction strained Si1−xGex/Si hole resonant tunneling diode using low-temperature Si2H6 reaction for nanometer-order ultrathin Si barriers

Low-temperature Si barrier growth with atomically flat heterointerfaces was investigated in order to improve negative differential conductance (NDC) characteristics of high-Ge-fraction strained Si_1−xGe_x/Si hole resonant tunneling diode with nanometer-order thick strained Si_1−xGe_x and unstrained Si layers. Especially to suppress the roughness generation at heterointerfaces for higher Ge fraction, Si barriers were deposited using Si₂H₆ reaction at a lower temperature of 400 °C instead of SiH₄ reaction at 500 °C after the Si_0.42Ge_0.58 growth. NDC characteristics show that difference between peak and valley currents is effectively enhanced at 11-295 K by using Si₂H₆ at 400 °C, compared with that using SiH₄ at 500 °C. Non-thermal leakage current at lower temperatures below 100 K tends to increase with decrease of Si barrier thickness. Additionally, thermionic-emission dominant characteristics at higher temperatures above 100 K suggests a possibility that introduction of larger barrier height (i.e. larger band discontinuity) enhances the NDC at room temperature by suppression of thermionic-emission current.     

Effects of CH2F2 and H2 flow rates on process window for infinite etch selectivity of silicon nitride to ArF PR in dual-frequency CH2F2/H2/Ar capacitively coupled plasmas

The process window for the infinite etch selectivity of silicon nitride (Si₃N₄) layers to ArF photoresist (PR) and ArF PR deformation were investigated in a CH₂F₂/H₂/Ar dual-frequency superimposed capacitive coupled plasma (DFS-CCP) by varying the process parameters, such as the low frequency power (P_LF), CH₂F₂ flow rate, and H₂ flow rate. It was found that infinitely high etch selectivities of the Si₃N₄ layers to the the ArF PR on both the blanket and patterned wafers could be obtained for certain gas flow conditions. The H₂ and CH₂F₂ flow rates were found to play a critical role in determining the process window for infinite Si₃N₄/ArF PR etch selectivity, due to the change in the degree of polymerization. The preferential chemical reaction of hydrogen with the carbon in the hydrofluorocarbon (CH_xF_y) layer and the nitrogen on the Si₃N₄ surface, leading to the formation of HCN etch by-products, results in a thinner steady-state hydrofluorocarbon layer and, in turn, in continuous Si₃N₄ etching, due to enhanced SiF₄ formation, while the hydrofluorocarbon layer is deposited on the ArF photoresist surface.     

Heteroepitaxial silicon-carbide nitride films with different carbon sources on silicon substrates prepared by rapid-thermal chemical-vapor deposition

Cubic crystalline silicon-carbon nitride (Si_1−x−yC_xN_y) films have been grown successfully using various carbon sources by rapid-thermal chemical-vapor deposition (RTCVD). The characteristics of the Si_1−x−yC_xN_y films grown with SiH₃CH₃, C₂H₄, and C₃H₈ are examined and compared by x-ray photoelectron spectroscopy (XPS) spectra, scanning electron microscopy (SEM) images, and transmission electron microscopy (TEM) patterns. The XPS spectra show that the differences of chemical composition and chemical-bonding state are co-related to the C bonding type of the different carbon source. The SEM images and TEM analysis indicate that the better Si_1−x−yC_xN_y film can be obtained using C₃H₈ gas as the carbon source. In addition, correlations between the growing stages to the microstructure of the cubic-crystalline Si_1−x−yC_xN_y films have been illustrated in detail.     

Nickel silicidation techniques for strained Si1?xGex, Si1?x?yGexCy, and Si1?yCy alloys material-device applications

A nickel silicide process for Si_1-xGe_x, Si_1-x-yGe_xC_y, and Si_1-yC_y alloy materials compatible with Si technology has been developed. Low-resistivity-phase (12–20 μΘ cm) nickel silicides have been obtained for these alloys with different low sheet-resistance temperature windows. The study shows that thin (15–18 nm) silicide layers with high crystalline quality, smooth silicide surface, and smooth interface between silicide and the underlying material are achievable. The technique could be used to combine the benefits of Ni silicide and Si_1-xGe_x, Si_1-x-yGe_xC_y, and Si_1-yC_y alloys. The technique is promising for Si or Si_1-xGe_x, Si_1-x-yGe_xC_y, and Si_1-yC_y alloy-based metal-oxide semiconductor, field-effect transistors (MOSFETs) or other device applications.     

Leakage currents and dielectric breakdown of Si1−x−yGexCy thermal oxides

A detailed study of the leakage currents and dielectric wear-out of thermal oxides grown on Si_1−xGe_x, Si_1−yC_y and Si_1−x−yGe_xC_y epilayers to determine their quality and reliability for Si_1−x−yGe_xC_y MOS technology is presented. After applying electrical stress to the samples, we have determined the conduction mechanisms and the dependence of leakage currents upon epilayer composition (Ge and C content). Conduction takes place mainly via Fowler-Nordheim tunneling injection. Ge and C introduce traps in the oxide which assist injection and thus lower the effective height of the tunneling barrier. We have also monitored the oxide reliability, focusing on time-dependent dielectric breakdown (TDDB). The nature of trapped charge in the oxide depends on the initial epilayer composition. We have found that the formation of defects induced by the presence of C leads to extrinsic oxide failure. While the presence of Ge in the oxide does not seem to introduce significant differences with respect to Si breakdown statistics, C in the oxide truly modifies the statistical profile.     

Effect of Hf and Hf-Ca substitution on the superconductivity of GdBa2Cu3O7 − δ

The structural and superconducting properties of (Gd_1−x−yCa_yHf_x)Ba₂Cu₃O_z samples are investigated using X-ray diffraction, resistivity, AC susceptibility and oxygen content measurements. The effect of increasing Hf concentration in (Gd_1−xHf_x)Ba₂Cu₃O_z lowers the oxygen content and decreases T_c which is attributed to hole filling by Hf. The substitution of Ca for Gd in (Gd_0.85−yCa_yHf_0.15)Ba₂Cu₃O_z provides proper matching between the ionic radius and valence of Gd³⁺ (0.94 Å) and the average ionic radius and valence of Hf⁴⁺ (0.78 Å) and Ca²⁺ (0.99 Å). As the Ca content increases, the T_c increases from 81 K (y = 0.05) to 86.5 K (y = 0.20, compensated oxide), closer to the value of 91 K for pure GdBa₂Cu₃O_7−δ due to the balance between the hole filling by Hf and hole doping by Ca. A comparative study of Hf doped samples of (R_1−xHf_x)Ba₂Cu₃O_z (R = Y, Er, Gd) indicates that the magnetic moment carried by R-ion plays an important role in the suppression of superconductivity and T_c.     

Influence of post deposition annealing on Y2O3-gated GaAs MOS capacitors and their reliability issues

The feasibility of employing yttrium oxide (Y₂O₃) as high-k gate dielectrics for GaAs metal-oxide-semiconductor (MOS) devices has been investigated. MOS capacitors were fabricated using RF-sputtered deposited Y₂O₃ films on NH₄OH treated n-GaAs substrate. Indeed high-k (Y₂O₃)/GaAs MOS capacitors exhibiting fairly good electrical characteristics, for instance, especially low leakage current density, low hysteresis and allowable density of interface states, have been achieved. The effects of several annealing treatments on Y₂O₃-gated GaAs MOS capacitors have been investigated in order to optimize the process conditions. A decrease in accumulation capacitance (C_acc) following PDA effectively increases the equivalent oxide thickness (EOT), which is predicted to be correlated with the growth and continuous increase in the physical thickness of a lower-k inter-layer sandwiched between Y₂O₃ and GaAs. However, leakage currents and interface trap densities are reduced with higher values of annealing temperature. The variation of current density with an equivalent oxide thickness (EOT) has also been investigated.