A flip-chip packaged 80-nm In0.7Ga0.3As MHEMT for millimeter-wave low-noise applications

In this paper, we present a flip-chip 80-nm In_0.7Ga_0.3As MHEMT device on an alumina (Al₂O₃) substrate with very little decay on device RF performance up to 60 GHz. After package, the device exhibited high I_DS = 435 mA/mm at V_DS = 1.5 V, high g_m = 930 mS/mm at V_DS = 1.3 V, the measured gain was 7.5 dB and the minimum noise figure (NF_min) was 2.5 dB at 60 GHz. As compared to the bare chip, the packaged device exhibited very small degradation in performance. The result shows that with proper design of the matching circuits and packaging materials, the flip-chip technology can be used for discrete low noise FET package up to millimeter-wave range.     

InAs/AlSb HEMTs for cryogenic LNAs at ultra-low power dissipation

Properties of the InAs/AlSb high electron mobility transistor, essential for the design of a cryogenic low-noise amplifier (LNA) operating at low power dissipation, have been studied. Upon cooling from 300 K to 77 K, the dc transconductance g_m was enhanced by 30% at a drain-source voltage V_DS of 0.1 V. The gate current leakage showed a strong reduction of the Schottky current component at 77 K. Compared to 300 K, the cut-off frequency f_T and maximum oscillation frequency f_max showed a significant improvement at 77 K with a peak f_T (f_max) of 167 (142) GHz at V_DS = 0.2 V. The suitability of the Sb HEMT for a cryogenic LNA design up to 50 GHz, operating at low dc power dissipation, was investigated through the extraction of the NF_tot,min figure of merit. It was found that the best device performance in terms of noise and gain is achieved at a low V_DS of 0.16 V resulting in a minimum NF_tot,min of 0.6 dB for a frequency of 10 GHz when operating at 77 K. A benchmarking between the Sb HEMT and an InP HEMT has been conducted highlighting the device improvement in noise and gain required to reach today’s state-of-the-art cryogenic LNAs.     

AlGaN/GaN self-aligned MODFET with metal oxide gate for millimeter wave application

As promising candidates for future microwave power devices, GaN-based high-electron mobility transistors (HEMTs) have attracted much research interest. An investigation of the operation of AlGaN/GaN n type self-aligned MOSFET with modulation doped GaN channels is presented. Liquid phase deposited (LPD) SiO₂ is used as the insulating material. An analytical model based on modified charge control equations is developed. The investigated critical parameters of the proposed device are the maximum drain current (I_Dmax), the threshold voltage (V_th), the peak DC trans-conductance (g_m), break down voltage (V_br) and unity current gain cut-off frequency (f_T). The typical DC characteristics for a gate length of 1 μm with 100 μm gate width are following: I_max=800 mA/mm, V_break-down=50 V, g_{m_extrinsic}=200 mS/mm, V_pinchoff=−10 V. The analysis and simulation results on the transport characteristics of the MOS gate MODFET structure is compared with the previously measured experimental data. The calculated values of f_T (20-130 GHz) suggest that the operation of the proposed device effectively, has sufficiently high current gain cutoff frequencies over a wide range of drain voltage, which is essential for high-power performance at microwave frequencies. The proposed device offers lower on-state resistance. The results so obtained are in close agreement with the experimental data.     

Control of threshold voltage and improved subthreshold swing in enhancement-mode InGaP/InGaAs metal-oxide-semiconductor pseudomorphic high-electron-mobility transistor

The InGaP/InGaAs metal-oxide-semiconductor pseudomorphic high-electron-mobility transistor (MOS-PHEMT) with an oxidized GaAs gate by liquid phase oxidation (LPO) is demonstrated. With the help of the LPO, the threshold voltage (V_th) can be shifted positively to 0.07 V, and enhancement-mode MOS-PHEMT is fabricated. The device with a gate metal of 1 × 100 μm² shows a maximum transconductance of 171 mS/mm at V_DS = 5 V and a maximum drain current density of 182 mA/mm at V_GS = 2 V. It also exhibits a lower leakage current and an improved subthreshold swing compared to the referenced Schottky-gate InGaP/InGaAs PHEMT.     

RF power performance evaluation of surface channel diamond MESFETs

We experimentally investigate the large-signal radio frequency performances of surface-channel p-type diamond MESFETs fabricated on hydrogenated polycrystalline diamond. The devices under examination have a coplanar layout with two gate fingers, total gate periphery of 100 μm; in DC they exhibit a hole accumulation behavior with threshold voltage V_t ≈ 0-0.5 V and maximum drain current density of 120 mA/mm. The best small-signal radio frequency performances (maximum cutoff or transition frequency f_T and oscillation frequency f_max) were obtained close to the threshold and were of the order of 6 and 15 GHz, respectively. The power radio frequency response was characterized by driving the devices in class A at an operating frequency of 2 GHz and identifying through the active load-pull technique the optimum load for maximum power added efficiency. A power gain in linearity of 8 dB and an output power of approximately 0.2 W/mm with 22% power added efficiency were obtained on the optimum load impedance at a bias point V_DS = −14 V, V_GS = −1 V. To the best of our knowledge, these are the first large signal measurements ever reported for surface MESFET on polycrystalline diamond, and show the potential of such technology for the development of microwave power devices.     

14.2 W/mm internally-matched AlGaN/GaN HEMT for X-band applications

High-performance X-band AlGaN/GaN high electron mobility transistor (HEMT) has been achieved by Γ-gate process in combination with source-connected field plate. Both its Schottky breakdown voltage and pinch-off breakdown voltage are higher than 100 V. Beside, excellent superimposition of direct current (DC) I-V characteristics in different V_ds sweep range indicates that our GaN HEMT device is almost current collapse free. As a result, both outstanding breakdown characteristics and reduction of current collapse effect guarantee high microwave power performances. Based upon it, we have developed an internally-matched GaN HEMT amplifier with single chip of 2.5 mm gate periphery, which exhibits power density of 14.2 W/mm with 45.5 dBm (35.5 W) output power and a power added efficiency (PAE) of 48% under V_ds = 48 V pulse operating condition at 8 GHz. To the best of our knowledge, it is the highest power density at this power level.     

Electrical characteristics of a vertically integrated field-effect transistor using non-intentionally doped Si nanowires

In this paper, we report the fabrication and the electrical characterization of Vertical Gate All Around Field-Effect Transistors (GAA-FET) using nonintentionally doped Silicon NanoWires (SiNWs) grown by Chemical Vapour Deposition (CVD) using the Vapour-Liquid-Solid (VLS) mechanism as conduction channel. The SiNWs GAA-FET devices exhibited n-channel type semiconductor behaviour whereas the as-grown SiNW FET present p-type behaviour. This effect may be due to positive fixed charge located in the oxide shell or at the Si/SiO₂ interface. Moreover we show that the threshold voltage at room temperature is around −0.95 V, a high I_ON/I_OFF ratio up to 10⁶ with a low I_OFF current about 1 pA, a maximum transconductance (g_m,max ∼ 0.9 μS at V_GS = −0.65 V and V_DS = 1 V) and a minimum inverse subthreshold slope around 145 mV/decade. In light of these characteristics, these devices can be suitable for high performance, low power consumption components and especially for high density integration in integrated circuits (ICs) interconnections regarding to their 3D architecture.     

5–11 GHz CMOS PA with 158.9 ± 41 ps group delay and low power using current-reused technique

This paper proposes the design of a low group delay and low power ultra-wideband (UWB) power amplifier (PA) in 0.18 μm CMOS technology. The PA design employs two stages cascade with inductive peaking technique to provide broad bandwidth characteristic and higher gain while gain flatness can be achieved by connecting inter-stage circuit. A common gate current-reused technique is adopted at the first stage amplifier to achieve good input matching, low group delay and low power. The simulation results show that the proposed PA design has an average gain of 11.5 dB with flatness of ±0.4 dB from 5–11 GHz, while maintaining bandwidth of 4.2–12.3 GHz. An input return loss (S₁₁) less than −10.4 dB and output return loss (S₂₂) less than −9.5 dB, respectively are obtained. The PA design achieves excellent phase linearity (i.e., group delay variation) of ±41 ps and only consuming 17 mW power from 1.2 V supply voltage. A good output 1-dB compression point OP1 dB of 3.7 dBm is obtained. By using this method, the proposed design has low group delay variation and lowest power among the recently reported UWB CMOS PAs applications.     

Ultra low voltage, ultra low power low noise amplifier for 2 GHz applications

In this paper, a 0.29 V, 2 GHz CMOS low noise amplifier (LNA) intended for ultra low voltage and ultra low power applications is developed. The circuit is simulated in standard 0.18 μm CMOS MOSIS. A two-stage architecture is then used to simultaneously optimize the gain and noise performance. Using forward-body-biased, the proposed LNA can operate at 0.29 V supply voltage, successfully demonstrating the application potential of dynamic threshold voltage technology in the radio frequency region. The LNA provides a good gain of 26.25 dB, a noise figure of 2.202 dB, reverse isolation (S₁₂) of −59.04 dB, input return loss (S₁₁) of −122.66 dB and output return loss (S₂₂) of -11.61 dB, while consuming only 0.96mW dc power with an ultra low supply voltage of 0.29 V. To the best of authors’ knowledge this is the lowest voltage supply and the lowest power consumption CMOS LNA design reported for 2 GHz to date.     

Improvement on the noise performance of InAs-based HEMTs with gate sinking technology

Improvement on the RF and noise performance for 80 nm InAs/In_0.7Ga_0.3As high-electron mobility transistor (HEMT) through gate sinking technology is presented. After gate sinking at 250 °C for 3 min, the device exhibited a high transconductance of 1900 mS/mm at a drain bias of 0.5 V with 1066 mA/mm drain-source saturation current. A current-gain cutoff frequency (f_T) of 113 GHz and a maximum oscillation frequency (f_max) of 110 GHz were achieved at extremely low drain bias of 0.1 V. The 0.08 × 40 μm² device with gate sinking demonstrated 0.82 dB minimum noise figure and 14 dB associated gain at 17 GHz with only 1.14 mW DC power consumption. Significant improvement in RF and noise performance was mainly attributed to the reduction of gate-to-channel distance together with the parasitic source resistance through gate sinking technology.     

Low power and high gain current reuse LNA with modified input matching and inter-stage inductors

In this paper we present a fully integrated current reuse CMOS LNA (low noise amplifier) with modified input matching circuitry and inductive inter-stage architecture in 0.18 μm CMOS technology. To reduce the large spiral inductors that actually require larger surface area for their fabrication, two parallel LC circuits are used with two small spiral on-chip inductors. Using cascode configuration equipped by parallel inter-stage LCs, we achieved lower power consumption with higher power gain. In this configuration we used two cascoded transistors to have a good output swing suitable for low voltage technology compared to other current reuse configurations. This configuration provides better input matching, lower noise figure and more reverse isolation which is vital in LNA design. Complete analytical simulation of the circuit results in center frequency of 5.5 GHz, with 1.9 dB NF, 50 Ω input impedance, 1 GHz 3 dB power bandwidth, 20.5 dB power gain (S₂₁), high reverse isolation (S₁₂)<−48 dB, −18.5 dB input matching (S₁₁) and −21.3 dB output matching (S₂₂), while dissipating as low power as 2 mW at 1.8 V power supply.     

Ultra-low-power temperature compensated voltage reference generator

A CMOS voltage reference generator, based on the difference between the gate-source voltages of two NMOS transistors, has been implemented with AMS 0.35 μm CMOS technology (V_thn=0.45 and at 0 °C). The minimum and maximum supply voltages that ensure the correct operation of the reference voltage generator, are 1.5 and 4.3 V, respectively. The supply current at the maximum supply voltage and at 80 °C is 2.4 μA. A temperature coefficient of 25 ppm/°C and a line sensitivity of 1.6 mV/V are achieved. The power supply rejection ratios without any filtering capacitor at 100 Hz and 10 MHz are larger than −74 and −59 dB, respectively. The occupied chip area is 0.08 mm².     

Influence of rapid thermal annealing temperature on structure and electrical properties of high permittivity HfTiO thin film used in MOSFET

HfTiO thin films were prepared by r.f. magnetron co-sputtering on Si substrate. To improve the electrical properties, HfTiO thin films were post heated by rapid thermal annealing (RTA) at 400 °C, 500 °C, 600 °C and 700 °C in nitrogen. It was found that the film is amorphous below 700 °C and at 700 °C monoclinic phase HfO₂ has occurred. With the increase of the annealing temperature, the film becomes denser and the refractive index increases. By electrical measurements, we found at 500 °C annealed condition, the film has the best electrical property with the largest dielectric constant of 44.0 and the lowest leakage current of 1.81 × 10⁻⁷ A/cm², which mainly corresponds to the improved microstructure of HfTiO thin film. Using the film annealed at 500 °C as the replacement of SiO₂ dielectric layer in MOSFET, combining with TiAlN metal electrode, a 10 μm gate-length MOSFET fabricated by three-step photolithography processes. From the transfer (I_DS–V_G) and output (I_DS–V_DS) characteristics, it shows a good transistor performance with a threshold voltage (V_th) of 1.6 V, a maximum drain current (I_ds) of 9 × 10⁻⁴ A, and a maximum transconductance (G_m) of 2.2 × 10⁻⁵ S.     

High thermal stability AlGaAs/InGaAs enhancement-mode pHEMT using palladium-gate technology

The dc, flicker noise, power, and temperature dependence of AlGaAs/InGaAs enhancement-mode pseudomorphic high electron mobility transistors (E-pHEMTs) were investigated using palladium (Pd)-gate technology. Although the conventional platinum (Pt)-buried gate has a high metal work function, which is beneficial for increasing the Schottky barrier height of the E-pHEMT, the high rate of intermixing of the Pt-GaAs interface owing to the effect of the continuous production of PtAs₂ on the device influenced the threshold voltage (V_th) and transconductance (g_m) at high temperatures or over the long-term operation. Variations in these parameters make Pt-gate E-pHEMT-related circuits impractical. Furthermore, a PtAs₂ interlayer caused a serious gate leakage current and unstable Schottky barrier height. This study presents the Pd-GaAs Schottky contact because Pd, an inert material with high work function of 5.12 eV. Stable Pd inhibited the less diffusion at high temperatures and simultaneously suppressed device flicker noise. The V_th of Pd/Ti/Au Schottky gate E-pHEMT was 0.183 V and this value shifted to 0.296 V after annealing at 200 °C. However, the V_th shifted from 0.084 to 0.231 V after annealing of the Pt/Ti/Au Schottky gate E-pHEMT because the Pt sunk into a deeper channel. The slope of the curve of power gain cutoff frequency (f_max) as a function of temperature was −5.76 × 10⁻² GHz/°C for a Pd/Ti/Au-gate E-pHEMT; it was −9.17 × 10⁻² GHz/°C for a Pt/Ti/Au-gate E-pHEMT. The slight variation in the dc and radio-frequency characteristics of the Pd/Ti/Au-gate E-pHEMT at temperatures from 0 to 100 °C revealed that the Pd-GaAs interface has great potential for high power transistors.     

Evolution of a CMOS Based Lateral High Voltage Technology Concept

This work describes the evolution of a CMOS based lateral high voltage (HV) technology concept, where the HV part is integrated in a low voltage (LV) CMOS technology. The starting point is an existing substrate related state of the art 0.35 μm LV CMOS technology (C35) which is optimized for digital and analog applications. The technology covers two different gate oxide thicknesses which allow to control two LV logic levels with different gate voltages and drain voltages (max.V_GS=max.V_DS=3.3V, max.V_GS=max.V_DS=5.5 V). The key requirement for the HV integration is to preserve the LV design rules (DR) and the LV transistor parameters. Only in this case it is possible to reuse the digital and analog intellectual property (IP) blocks. The major challenge of this integration is to overcome the relatively high surface concentration of the 0.35 μm CMOS process which defines the threshold voltages and the short channel effects. Because the HV devices use the same channel formation like the LV devices, a process concept for the drift region connection to the channel is the key point in this integration approach. A benchmark for the process complexity is given by the mask count (low volume production) and the number of alignments (high volume production). Starting from a very simple approach n-channel HV transistors are described which can be integrated in the substrate related LV CMOS concept without adding additional masks. During the next steps the LV CMOS process is modified continuously using additional masks and alignment steps. From each step to step the new HV properties are explained and the trade-off between process complexity and device performance is discussed.     

Enhanced characteristics in gate-recessed and sidewall-recessed AlGaAs/InGaAs PHEMTs by citric-based selective wet etching

Improved device performance in Al_0.2Ga_0.8As/In_0.15Ga_0.85As gate-recessed enhancement-mode pseudomorphic high electron mobility transistors (E-PHEMTs) and sidewall-recessed depletion-mode PHEMTs (D-PHEMTs) using a newly developed citric buffer etchant are reported. The innovated etchant near room temperature (23°C) possesses a high GaAs/Al_0.2Ga_0.8As or In_0.15Ga_0.85As/Al_0.2Ga_0.8As etching selectivity (>250) applied to an etched stop surface. For E-PHEMTs, the transconductance (G_m) of 315?mS/mm and high linearity of 0.46?V-wide gate voltage swing (drop of 10% peak G_m), corresponding to 143?mA/mm-wide I_DS, even at a gate length of 1?µm is obtained. For microwave operation, this 1?µm-gate E-PHEMT shows the f_max (maximum operation frequency) of 29.2?GHz and the f_T (cut-off frequency) of 11.2?GHz, respectively. The measured minimum noise figure (NF_min), under V_DS?=?3?V and I_DS?=?7.5?mA, is 0.56?dB at 1?GHz with the associated gain of 10.86?dB. The NF_min is less than 1.5?dB in the frequency range from 1 to 4?GHz. In addition, an effective and simple method of selective gate sidewall recess is utilized to etch the low barrier in In_0.15Ga_0.85As channel at mesa sidewalls for D-PHEMTs. For D-PHEMTs with 1?×?100?µm² exhibit a very low gate leakage current of 2.4?μA/mm even at V_GD?=??10?V and high gate breakdown voltage over 25?V. As compared to that of no sidewall recess, nearly two orders of reduction in magnitude of gate leakage current and 100% improvement in gate breakdown voltage are achieved.     

Accurate modeling of nanoscale gate underlap SOI MOSFET and design of low noise amplifier for RF applications

Paper presents an accurate model by accounting non-quasi-static and extrinsic parasitic effects for 90 nm gate underlap SOI MOSFETs for RF applications. Generated Y-parameters from the model up to 20 GHz matched very well with 2D ATLAS (with an average error of ～5%), whereas results from quasi-static predictive technology model differ significantly (>20%). Calculated transit frequency f _T and maximum frequency of oscillation f _max have been found as ～108 and ～130 GHz respectively. Simulated noise figure at drain-to-source current I _DS ≈ 0.64mA and drain-to-source voltage V _DS=1 V was found to be ≈2.8 dB with gate resistance R _ge = 3 Ω. A low noise amplifier (LNA) designed at operating frequency of 5.8 GHz using the model has shown good match at input (S ₁₁ ≈ ?15 dB), output (S ₂₂ ≈ ?16 dB) and gain (S ₂₁ ≈ 15 dB). A new figure-of-merit of LNA (FoM_LNA) involving signal power gain G, noise factor F and dc power consumption P _dc has been proposed. By comparing with limited available measured data of 180 nm bulk, it has been found that underlap LNA (simulated using the developed model) gives almost three times improvement in the proposed FoM_LNA.     

Effects of active area and gate doping method on program threshold voltage in an EEPROM cell

In this paper, we investigate dependency of program threshold voltage (V_T) in EEPROM cell on active area and doping method of floating gate. With in situ doped floating gate, it is found that there is a sharp drop of program V_T from 4 to 2.25 V when the channel width is reduced from 0.30 to 0.22 μm, while doping by ion implantation results in slight reduction of program V_T from 3.95 to 3.69 V. It also appears that channel length is another critical factor to affect on reduction of program V_T. In case of in situ doped floating gate, the program V_T is reduced from 3.9 to 2.7 V when the channel length is reduced from 0.20 to 0.18 μm. TEM analysis reveals that thermal oxidation in tunnel oxide region occurs during subsequent high temperature oxidation due to oxidant penetration via interface of silicon surface and sidewall silicon nitride.     

Design and fabrication of 94 GHz MMIC single balanced resistive mixer without IF balun

In this paper, a 94 GHz microwave monolithic integrated circuit (MMIC) single balanced resistive mixer affording high LO-to-RF isolation was designed without an IF balun. The single balanced resistive mixer, which does not require an external IF balun, was designed using a 0.1 μm InGaAs/InAlAs/GaAs metamorphic high electron mobility transistor (HEMT). The designed MMIC single balanced resistive mixer was fabricated using the 0.1 μm MHEMT MMIC process. From the measurement, conversion loss of the single balanced resistive mixer was 14.7 dB at an LO power of 10 dBm. The P_1 dB (1 dB compression point) values of the input and output were 10 dBm and −5.3 dBm, respectively. The LO-to-RF isolation of the single balanced resistive mixer was −35.2 dB at 94.03 GHz. The single balanced resistive mixer in this work provided high LO-to-RF isolation without an IF balun.     

Current saturation effect for pentacene-based static induction transistor under negative drain-source and gate voltages

Usually, the drain-source current (I_DS) increases with positive drain-source voltage (V_DS) for pentacene-based organic static induction transistor (OSIT) ITO(Source)/Pentacene/Al(Gate)/Pentacene/Au(Drain) and it shows an inherent rectifying property under negative gate voltages (V_G), i.e. the slope of I_DS vs. V_DS curve increases with V_DS but without any current saturation effect. In this paper, we investigated the electrical characteristics of pentacene-based OSIT ITO/Pentacene(80 nm)/Al(15 nm)/Pentacene(80 nm)/Au under negative V_DS and V_G, and found that I_DS changed from rectifying property to saturation effect when the magnitude of negative V_DS was increased from 0 V to −6 V under negative V_G, and the turn-on voltage (V_ON) moved to larger negative voltages when the magnitude of negative V_G increased and the movement step of V_ON gets smaller after keeping the device for a long time, and the possible mechanisms for such a kind of current modulation were discussed.