A comparative study of depth profiling of interface states using charge pumping and low frequency noise measurement in SiO2/HfO2 gate stack nMOSFETs

Charge pumping and low frequency noise measurements for depth profiling have been studied systematically using a set of gate stacks with various combinations of IL and HfO₂ thicknesses. The distribution of generated traps after HCI and PBTI stress was also investigated. The drain-current power spectral density made up all of the traps of IL in 0 < z < T_IL and the traps of HfO₂ in T_IL < z < T_HK. The traps near the Si/SiO₂ interface dominated the 1/f noise at higher frequencies, which is common in SiO₂ dielectrics. For the HfO₂/SiO₂ gate stack, however, the magnitude of the 1/f noise did not significantly change after HCI and PBTI because of more traps in the bulk HfO₂ film than at the bottom of the interface.     

The effect of oxide layer thickness on the quantification of 1.5 MeV γ–radiation induced interface traps in the Ag/SiO2/Si MOS devices

This work presents the effect of varied thickness of oxide layer and radiation dose on electrical characteristics of Ag/SiO₂/Si MOS devices irradiated by 1.5 MeV γ–radiations of varied doses. SiO₂ layers of 50, 100, 150 and 200 nm thickness were grown on Si substrates using dry oxidation and exposed to radiation doses of 1, 10 and 100 kGy. The exposure to radiation resulted in generation of fixed charge centers and interface traps in the SiO₂ and at the Si/SiO₂ interface. Capacitance-conductance-voltage (C-G-V) and capacitance-conductance-frequency (C-G-f) measurements were performed at room temperature for all MOS devices to quantify the active traps and their lifetimes. It is shown that accumulation and minimum capacitances decreased as the thickness of SiO₂ layer increased. For the unexposed MOS devices, the flat band voltage V_FB decreased at a rate of −0.12 V/nm, density of active traps increased by 4.5 times and depletion capacitance C_DP, increased by 2.5 times with the increase of oxide layer thickness from 50 to 200 nm. The density of active traps showed strong dependence on the frequency of the applied signal and the thickness of the oxide layer. The MOS device with 200 nm thick oxide layer irradiated with 100 kGy showed density of active interface traps was high at 50 kHz and was 3.6×10¹⁰ eV⁻¹ cm⁻². The relaxation time of the interface traps also increased with the exposure of γ–radiation and reached to 9.8 µs at 32 kHz in 200 nm thick oxide MOS device exposed with a dose of 100 kGy. It was inferred that this was due to formation of continuum energy states within the band gap and activation of these defects depended on the thickness of oxide layer, applied reverse bias and the working frequency. The present study highlighted the role of thickness of oxide layer in radiation hard environments and that only at high frequency, radiation induced traps remain passivated due to long relaxation times.     

Tunneling component suppression in charge pumping measurement and reliability study for high-k gated MOSFETs

Although charge pumping (CP) is a powerful technique to measure the energy and spatial distributions of interface trap and oxide trap in MOS devices, the parasitic gate leakage current in it is the bottleneck. A CP method was modified and applied to high-k gate dielectric in this work to separate the CP current from the parasitic tunneling component in MOS devices. The stress-induced variations of electrical parameters in high-k gated MOS devices were investigated and the physical mechanism was studied by the modified CP technique. The stress-induced trap generation for devices with HfO₂-dominated high-k gate dielectrics is like mobile defect; while that with SiO₂-dominated ones is similar to the near-interface/border trap.     

Detailed analysis of charge pumping and IdVg hysteresis for profiling traps in SiO2/HfSiO(N)

By scanning 1/3 nm SiO₂/HfSiO(N) gate dielectrics with variable t_charge−t_discharge amplitude charge pumping technique (VT²ACP) and slow rate I_dV_g hysteresis, we study in detail the energy profile and estimate the spatial position (within SiO₂ or HKs layer) of pre-stress and stress-induced electron traps. Pre-stress traps are mainly at shallow energy levels while stress-induced traps are at deeper energy levels. We demonstrate that due to incomplete discharge of bulk traps, the commonly-used base level charge pumping (CP) sweep is not suited for trap energy profiling. Further, we show that in CP measurements, due to the non-negligible tail of the filling probability of traps, even at short charge times, a fraction of HK-bulk traps is scanned in addition to interfacial traps. When the trap density in the HK is significantly higher than in the IL, this fraction might dominate the CP signal and can cause misinterpretation of data. Finally, we point out the possible contribution of the initially-present traps in the formation of a percolation path causing the dielectric breakdown.     

Study of nitrogen impact on VFB-EOT roll-off by varying interfacial SiO2 thickness

Flat band voltage (V_FB) roll-off in long channel devices at thin equivalent oxide thickness (EOT) is studied on SiO₂/nitrided-HfSiO stacks. V_FB increases when SiO₂ interfacial layer thickness decreases, and charges pumping (CP) frequency sweep analysis shows higher trap density near Si/SiO₂ interface. Based on this observation, an atomic diffusion model is introduced. Higher concentration of nitrogen atom in the HfSiO(N) layer diffuses to the Si/SiO₂ interface through the SiO₂ layer in thinner SiO₂ device, and accumulates near Si/SiO₂ interface which can introduce higher density of interfacial traps. Lifetime extracted from negative bias temperature instability (NBTI), and mobility are also degraded in thinner SiO₂ devices due to the higher interfacial trap density.The V_FB roll-off can be improved by lowering nitrogen concentration in the HfSiO(N) layer from optimizing plasma nitridation pressure, decreasing post deposition anneal temperature, or using defect absorbing layer on the high-k oxide.     

1.2 nm capacitance equivalent thickness gate stacks on Si-passivated GaAs

Experiments to increase the specific capacitance of MOS capacitors consisting of HfO₂ on a passivating interfacial layer (IL) of amorphous Si (a-Si) on GaAs are described. XPS analysis of the layers and electrical measurements on the capacitors are combined to study the evolution of the gate stack during deposition and subsequent heat treatments. It is shown that oxidation of the a-Si IL is a major factor in preventing the attainment of a scaled capacitance equivalent thickness (CET). By controlling the deposition of the layers, the gate metal and the heat treatments, a highly scaled gate stack with a CET of 1.2 nm and a leakage reduction of more than 4 orders of magnitude with respect to SiO₂/Si was realized.     

Profiling of traps in SiO2/Al2O3 gate stack by the charge pumping technique

In this paper, we present our results on the distribution and generation of traps in a SiO₂/Al₂O₃ transistor. The investigation has been carried out by using charge pumping measurements, both variable voltage and frequency techniques, and constant voltage stress.By increasing the amplitude of the gate pulse we observe an increase of the charge recombined per cycle closely related to the contribution of shallow traps near the SiO₂/Al₂O₃ interface. By reducing the pulse frequency we measure an increase in the charge pumping current due to traps located deeper in the Al₂O₃. By combining charge pumping and constant voltage stress measurements, we found that the traps are mostly generated near the Si/SiO₂ interface.     

Optical characteristics of Si/SiO2 multilayers prepared by magnetron sputtering

Si/SiO₂ multilayers have been successfully prepared by magnetron sputtering and subsequently thermal annealed in an Ar atmosphere at a temperature of more than 500 °C. The surface of the as-deposited films is compact and smooth, and the distribution of grain size estimated to be 20 nm is uniform. For Si/SiO₂ multilayers annealed at 1100 °C, the Si sublayer sandwiched between potential barrier SiO₂ is crystalline structure by means of the analysis of Raman spectra and XRD data. The visible PL peak accompanying to a blue-shift with the decrease of Si sublayer thickness has been observed, and the intensity of this peak enhances with the increase of annealing temperature. The visible luminescence properties of Si/SiO₂ multilayers can be ascribed to quantum confinement of electron-hole pairs in quantum wells with grain size lower than 4.5 nm. In Si/SiO₂ multilayers, not only quantum confinement but also Si-SiO₂ interface states play an important role in the optical transition. The PL peak located at 779 nm is independent of the thickness of Si sublayer, so it may be ascribed to interface mediated transition. Typical Si dangling bonds defect could be a dominating obstacle to high luminescence efficiencies.     

Atomic-layer-deposited silicon-nitride/SiO2 stack––a highly potential gate dielectrics for advanced CMOS technology

An extremely thin (2 monolayers) silicon nitride layer has been deposited on thermally grown SiO₂ by an atomic-layer-deposition (ALD) technique and used as gate dielectrics in metal–oxide–semiconductor (MOS) devices. The stack dielectrics having equivalent oxide thickness (T_eq=2.2 nm) efficiently reduce the boron diffusion from p⁺ poly-Si gate without the pile up of nitrogen atoms at the SiO₂/Si interface. The ALD silicon nitride is thermally stable and has very flat surface on SiO₂ especially in the thin (<0.5 nm) thickness region.An improvement has been obtained in the reliability of the ALD silicon-nitride/SiO₂ stack gate dielectrics compared with those of conventional SiO₂ dielectrics of identical thickness. An interesting feature of soft breakdown free phenomena has been observed only in the proposed stack gate dielectrics. Possible breakdown mechanisms are discussed and a model has been proposed based on the concept of localized physical damages which induce the formation of conductive filaments near both the poly-Si/SiO₂ and SiO₂/Si-substrate interfaces for the SiO₂ gate dielectrics and only near the SiO₂/Si-substrate interface for the stack gate dielectrics.Employing annealing in NH₃ at a moderate temperature of 550 °C after the ALD of silicon nitride on SiO₂, further reliability improvement has been achieved, which exhibits low bulk trap density and low trap generation rate in comparison with the stack dielectrics without NH₃ annealing.Because of the excellent thickness controllability and good electronic properties, the ALD silicon nitride on a thin gate oxide will fulfill the severe requirements for the ultrathin stack gate dielectrics for sub-0.1 μm complementary MOS (CMOS) transistors.     

The effects of gamma irradiation on low-pressure chemical-vapor-deposited silicon dioxide metal-oxide-silicon structures

The effects of gamma irradiation on as-deposited, oxygen-annealed, and dual-dielectric gate (undoped polysilicon/oxide) low-pressure chemical-vapor-deposited (LPCVD) silicon dioxide (SiO₂) metal-oxide-silicon (MOS) structures were investigated. As-deposited LPCVD SiO₂ MOS structures exhibit the largest shift in flatband voltage with gamma irradiation. This is most likely due to the large number of bulk oxide traps resulting from the nonstochiometric nature of as-deposited LPCVD SiO₂. Dual-dielectric (undoped polysilicon/annealed LPCVD SiO₂) MOS structures exhibit the smallest shift in flatband voltage and increase in interface state density compared to as-deposited and oxygen-annealed LPCVD SiO₂ MOS structures. The interface state density of dual-dielectric MOS structures increases from 5 × 10¹⁰ eV cm⁻² to 2–3 × 10¹¹ eV cm⁻² after irradiation to a gamma total dose level of 1 Mrads(Si). This result suggests that the recombination of atomic hydrogen atoms with silicon dangling bonds, either along grain boundaries or in crystallites of the undoped polysilicon layer in dual-dielectric (undoped polysilicon/annealed LPCVD SiO₂) MOS structures, probably reduces the number of atomic hydrogen atoms reaching the Si/SiO₂ interface to generate interface states.     

On the SILC mechanism in MOSFET’s with ultrathin oxides

In this paper, n-channel MOSFET’s with oxides 1.2, 1.5 and 1.8 nm thick are studied. In such devices the trap assisted tunnelling (TAT) current required to fit the gate current vs. gate voltage, I_g(V_g), characteristics is thought to flow through Si–SiO₂ interface traps. After stress, it becomes a stress induced leakage current (SILC) which should allow to obtain interface trap density variations with stress. The TAT mechanism is discussed. Then, the Si–SiO₂ interface trap densities extracted using the SILC and charge pumping (CP) are compared. Much larger trap creation rates are viewed by the SILC with regard to CP, questioning the occurrence of the SILC through interface traps. To answer this question the interaction between SILC and CP measurements is investigated.     

Charge pumping spectroscopy: HfSiON defect study after substrate hot electron injection

Spectroscopic charge pumping (CP) is used to study the evolution of the energy distribution of trapped electrons within HfSiON/SiO₂ gate stacks under substrate hot electron injection (SHEI). Base level CP measurements with large pulse amplitude allow an efficient charging/discharging of traps and reaching two defect bands in the HfSiON situated at 0.40 and 0.85 eV above the Si conduction band, respectively. Unlike standard constant voltage stress (CVS), SHEI enables full control of the stress by separately controlling the applied gate field, the injected electron energy, and the fluence. During CVS, HfSiON defects at 0.40 eV are generated. Conversely, during SHEI, either the shallow or the deep defects are preferentially created depending on the gate field as well as electron energy.     

Characterization of defect traps in SiO2 thin films influence of temperature on defects

In order to improve the electrical operation of very thin gate oxide metal-oxide-semiconductor (MOS) devices, it is necessary to understand generated defects in the non-stoichiometric SiO_x area and at the Si–SiO₂ interface. For this purpose, we extended our new measurement technique, which is a temperature dependent method, to MOSFETs and Al-gate MOS devices to investigate slow-state traps and their relationship with fast-state traps (influence of technology, temperature and field dependence). With this method, activation energies for slow-state traps can be determined. Hydrogen species have been characterized. These defects are created when the MOS capacity is under a strong electric field that induces injection of electrons by tunnel effect through the silicon dioxide, SiO₂.     

Distribution and generation of traps in SiO2/Al2O3 gate stacks

In this work we combine charge-pumping measurements with positive constant voltage stress to investigate trap generation in SiO₂/Al₂O₃ n-MOSFET. Trap density has been scanned either in energy or in position based on charge-pumping (CP) measurements performed under different operating conditions in terms of amplitude and frequency of the gate pulse. Our results have revealed that the traps are meanly localized shallow in energy level, deeper in spatial position and they are mostly generated near the Si/SiO₂ interface.     

Transients during pre-breakdown and hard breakdown of thin gate oxides in metal–SiO2–Si capacitors

Time–resolved electrical measurements show transient phenomena occurring during degradation and intrinsic dielectric breakdown of gate oxide layers under constant voltage Fowler–Nordheim stress. We have studied such transients in metal/oxide/semiconductor (MOS) capacitors with an n⁺ poly-crystalline Si/SiO₂/n-type Si stack and with oxide thickness between 35 and 5.6 nm. The data adds new information concerning the intrinsic breakdown mechanism and these are shown and discussed together with the adopted measurement techniques.     

MOS device fabrication using sputter-deposited gate oxide and polycrystalline silicon layers

For applications in the MOS device fabrication the interface properties of sputtered SiO₂ and SiO₂-polycrystalline silicon layers on silicon substrates were investigated and improved to a quality which is equivalent to those of thermally grown SiO₂ with pyrolytical polycrystalline silicon (polySi). For testing these layers as gate oxide and Si electrodes of MOS transistors the well known Si gate process was varied to include sputter deposition and the optimal deposition, annealing and diffusion parameters were integrated.MOS transistors with sputtered SiO₂ and Si gate material layers and for comparison Al gate devices with sputtered SiO₂ have been fabricated and their threshold voltage behavior was tested.     

Light emission from Si/SiO2 superlattices fabricated by RPECVD

Si/SiO₂ superlattices that exhibit intense luminescence properties were fabricated by remote plasma enhanced chemical vapor deposition. (RPECVD) and subsequent rapid thermal annealing for silicon crystallization. The effects of charge carrier confinement like blue shifting of the PL spectra and intensity increase with decreasing Silicon quantum well thickness are observed in low temperature photoluminescence experiments. The Si/SiO₂ interface quality is calculated from capacitance voltage (CV) measurements on metal oxide semiconductor teststructures showing excellent layer and Si/SiO₂ interface properties. The Si crystallization process is investigated and analyzed by Raman and transmission electron microscopy. Decreasing the Si quantum well thickness to 2 nm leads to light emission at room temperature.     

Charge carrier generation/trapping mechanisms in HfO2/SiO2 stack

We have investigated electrical stress-induced charge carrier generation/trapping in a 4.2 nm thick (physical thickness T_phy) hafnium oxide (HfO₂)/silicon dioxide (SiO₂) dielectric stack in metal-oxide-semiconductor (MOS) capacitor structures with negative bias on the gate. It is found that electron trapping is suppressed in our devices having an equivalent oxide thickness (EOT) as low as 2.4 nm. Our measurement results indicate that proton-induced defect generation is the dominant mechanism of generation of bulk, border and interface traps during stress. In addition, we have shown that constant voltage stress (CVS) degrades the dielectric quality more than constant current stress (CCS).     

Thermal annealing effect on electrical properties of metal nitride gate electrodes with hafnium oxide gate dielectrics in nano-metric MOS devices

Electrical properties of hafnium oxide (HfO₂) gate dielectric with various metal nitride gate electrodes, i.e., tantalum nitride (TaN), molybdenum nitride (MoN), and tungsten nitride (WN), were studied over a range of HfO₂ thicknesses, e.g., 2.5-10 nm, and post-metal annealing (PMA) temperatures, e.g., 600 °C to 800 °C. The work function of the nitride gate electrode was dependent on the material and the post-metal annealing (PMA) temperature. The scanning transmission electron microscopy technique is used to observe the effect of PMA on the interfacial gate dielectric thickness. After high-temperature annealing, the metal nitride gates were suitable for NMOS. At the same PMA temperature, the oxide-trapped charges increased and the interface state densities decreased with the increase of the HfO₂ thickness for TaN and WN gate electrodes. However, for MoN gate electrode the interface state density is almost independent of film thickness. Therefore, dielectric properties of the HfO₂ high-k film depend not only on the metal nitride gate electrode material but also the post-metal annealing condition as well as the film thickness. During constant voltage stress of the MOS capacitors, an increase in the time-dependent gate leakage current is also observed.     

Full-band tunneling in high-κ dielectric MOS structures

High-κ oxides such as ZrO₂ and HfO₂ have attracted great interest, due to their physical properties, suitable to replacement of SiO₂ as gate dielectric materials. In this work, we investigate the tunneling properties of ZrO₂ and HfO₂ high-κ oxides, by applying quantum mechanical methods that include the full-band structure of Si and oxide materials. Semiempirical sp³s*d tight-binding parameters have been determined to reproduce ab initio band dispersions. Transmission coefficients and tunneling current have been calculated for Si/ZrO₂/Si and Si/HfO₂/Si MOS structures, showing a very low gate leakage current in comparison to SiO₂-based structures with equivalent oxide thickness.