A wafer-level 3D packaging structure with Benzocyclobutene as a dielectric for multichip module fabrication

A new wafer-level 3D packaging structure with Benzocyclobutene (BCB) as interlayer dielectrics (ELDs) for multichip module fabrication is proposed for application in the Ku-band wave. The packaging structure consists of two layers of BCB films and three layers of metallized films, in which the monolithic microwave IC (MMIC), thin film resistors, striplines and microstrip lines are integrated. Wet etched cavities fabricated on the silicon substrate are used for mounting active and passive components. BCB layers cover the components and serve as ILDs for interconnections. Gold bumps are used as electric interconnections between different layers, which eliminates the need to prepare vias by costly dry etching and deposition processes. In order to get high-quality BCB films for the subsequent chemical mechanical planarization (CMP) and multilayer metallization processes, the BCB curing profile is optimized and the roughness of the BCB film after the CMP process is kept lower than 10 nm. The thermal, mechanical and electrical properties of the packaging structure are investigated. The thermal resistance can be controlled below 2 ℃/W. The average shear strength of the gold bumps on the BCB surface is around 70 N/mm~2. The performances of MMIC and interconnection structure at high frequencies are optimized and tested. The 5 -parameters curves of the packaged MMIC shift slightly showing perfect transmission character. The insertion loss change after the packaging process is less than 1 dB range at the operating frequency and the return loss is less than -8 dB from 10 to 15 GHz.     

Polishing behaviors of single crystalline ceria abrasives on silicon dioxide and silicon nitride CMP

The effects of single crystalline ceria (CeO₂) abrasives in chemical mechanical polishing (CMP) slurries were investigated for silicon dioxide (SiO₂) and silicon nitride (Si₃N₄) CMP process. The size of ceria abrasives was controlled by varying hydrothermal reaction conditions. Polishing removal rate was measured with four slurries, with different mean primary particle size of 62, 116, 163 and 232 nm. The polishing results showed that the single crystalline ceria abrasives were not easily broken-down by mechanical force during CMP process. It was found that the removal rate of oxide and nitride film strongly depend upon abrasive size, whereas the surface uniformity deteriorates as abrasive size increases. The observed polishing results confirmed that there exists an optimum abrasive size (163 nm) for maximum removal selectivity between oxide and nitride films. The polishing behavior of the single crystalline ceria abrasives was discussed in terms of morphological properties of the abrasive particle.     

ULSI电路层间SiO_2介质CMP工艺与抛光液

阐明了化学机械抛光(CMP)工艺在集成电路制造中所发挥的关键作用,介绍了作为IC多层布线层间介质SiO2的化学机械抛光机理及其抛光液在化学机械抛光中扮演的重要角色,着重分析了影响SiO2介质化学机械抛光质量的主要因素并在此基础上提出CMP工艺的优化工艺条件以及今后SiO2介质CMP研究重点。     

Interfacial adhesion of spin-coated thin adhesive film on silicon substrate for the fabrication of polymer optical waveguide

An investigation was carried out to study the interfacial adhesion of spin-coated polymeric adhesive thin film on a silicon substrate for fabrication of a polymeric optical waveguide. An adhesive shear button was made on a silicon substrate by using a photolithography process, and interfacial adhesion was measured with a Dage D2400 shear tester. Different adhesion strengths were found at different portions of the same sample. Higher adhesion strength was observed at the center of the substrate than at other locations of spin-coated adhesive films. Adhesion strength was also measured after heat exposure of the deposited and cured adhesive layer to evaluate the heat resistance of the adhesive film. After heat exposure, adhesion strength decreased substantially from all locations of the substrate due to the thermal degradation. Again, the adhesion was measured for different plasma-treated substrate conditions. The surface morphology of plasma-treated and untreated silicon substrates before deposition were characterized by atomic force microscopy. Lower adhesion strength was unexpectedly observed for all plasma-treated substrates, even for higher surface roughness. The fracture surfaces after shear testing were also characterized by optical microscopy. The complete study provides important indications for the fabrication of better-performing polymeric optical waveguides for photonic devices.     

Chemical mechanical polishing of polymeric materials for MEMS applications

Polymeric materials such as polycarbonate (PC) and poly-methyl methacryate (PMMA) are replacing silicon as the major substrate in microfluidic system fabrication due to their outstanding features such as low cost and good chemical resistance. In this study, chemical mechanical polishing (CMP) of PC and PMMA substrates was investigated. Four types of slurry were tested on CMP of the polymers under the same process conditions. The slurry suitable for polishing PC and PMMA was then chosen, and further CMP experiments were carried out under different process conditions. Experimental results showed that increasing table speed or head load increased the material removal rates of the polymers. The polymeric surface quality after CMP was acceptable to most MEMS applications. Analysis of variance was also carried out, and it was found that the interaction of head load and table speed had a significant (95% confidence) effect on surface finish of polished PMMA. On the other hand, table speed had a highly significant (99% confidence) effect on surface finish of polished PC.     

Chemical mechanical polishing of polycarbonate and poly methyl methacrylate substrates

In recent years, polymeric materials such as polycarbonate (PC) and poly methyl methacrylate (PMMA) are replacing silicon as major substrates in microfluidic system fabrication due to the outstanding features like low cost and good chemical resistance. In this study, chemical mechanical polishing (CMP) of PC and PMMA substrates was investigated. First, four types of slurry were tested. Then, the slurry producing relatively high material removal rate (MRR) and low surface roughness was chosen, and experiments were designed and carried out to investigate the effects of key process parameters. The experimental results show impacts of key CMP process parameters on MRR and surface finish of PC and PMMA substrates. An increase in head load or table speed would cause an increase in surface roughness heights and MRR. The surface quality of the polymers after CMP appeared to be acceptable for most of microelectromechanical system applications as the process conditions were restrained within the process window.     

Screen‐printed Emitter‐Wrap‐Through solar cell with single step side selective emitter with 18.8% efficiency

A fabrication process for Emitter‐Wrap‐Through solar cells on monocrystalline material with high quality gap passivation by wet thermal silicon dioxide is investigated. Masking and structuring steps are performed by screen‐printing technology. Via‐holes are created by an industrially applicable high‐speed laser drilling process. The cell structure features a selective emitter structure fabricated in a single high temperature step: a highly doped emitter at the via‐holes and the rear side, allowing for a low via‐hole resistivity as well as a low resistivity contact to screen‐printed pastes, and a moderately doped front side emitter exhibiting high quantum efficiency in the low wavelength range. Therefore a novel approach is applied depositing either doped or undoped PECVD silicon dioxide layers on the front side. It is shown that doping profiles advantageous for the EWT‐cell structure can be achieved. The screen‐printed aluminum paste is found to penetrate the underlying thermal dioxide layer at appropriate contact firing conditions leading to a zone of high recombination in the overlap region of aluminum and silicon dioxide. It is shown that conventional PECVD‐anti‐reflection silicon nitride acts as effective protection layer reducing the recombination in this region. Designated area conversion efficiencies up to 18.8% on FZ material are obtained applying the single step side selective emitter fabrication technique. Copyright © 2010 John Wiley & Sons, Ltd.     

Charge trapping in ion-sputtered silicon dioxide films on silicon

Charge trapping in thermal silicon dioxide has been previously studied in great detail. Recently there has been an interest in depositing silicon dioxide films at lower temperatures to be compatible with device technologies that are not compatible with the higher temperature. This paper discusses the electron and hole trapping behavior in room temperature, ion-sputtered silicon dioxide thin films. Generally, these films are observed to trap both carriers much more efficiently then thermal silicon dioxide films. The trapping parameters such as the trap cross-section, location, density and the trapping efficiency are reported.     

Investigation on the controllable growth of monodisperse silica colloid abrasives for the chemical mechanical polishing application

With the rapid development of chemical mechanical polishing technique as well as its increasing application in IC foundry, the abrasives of slurry are required to have different specifications in terms of size and size’s distribution, which play a vital role in the material removal and defect control. In this study, we monitor in detail the growth process of colloidal silica abrasives changing from the tiny nuclei to large nanoparticles by means of the electron microscopy images. Using the procedure we develop, we are capable of producing monodisperse colloidal silica nanoparticles ranging from 60 to 130 nm in diameter, which are mostly often applied as abrasives in chemical mechanical planarization/polishing (CMP) process of integrated circuit (IC) manufacturing. The physicochemical properties of the silica synthesized by our procedure are also characterized by the X-ray diffraction (XRD) patterns and thermal analysis. The polishing test adopting the colloidal silica as abrasives is performed on silicon wafer to evaluate the CMP properties.     

Fabrication of high-quality p-MOSFET in Ge grown heteroepitaxially on Si

We have successfully demonstrated high-performance p-MOSFETs in germanium grown directly on Si using a novel heteroepitaxial growth technique, which uses multisteps of hydrogen annealing and growth to confine misfit dislocations near the Ge-Si interface, thus not threading to the surface as expected in this 4.2% lattice-mismatched system. We used a low thermal budget process with silicon dioxide on germanium oxynitride (GeO/sub x/N/sub y/) gate dielectric and Si/sub 0.75/Ge/sub 0.25/ gate electrode. Characterization of the device using cross-sectional transmission electron microscopy and atomic force microscopy at different stages of the fabrication illustrates device-quality interfaces that yielded hole effective mobility as high as 250 cm/sup 2//Vs.     

以BCB为介电材料的硅基集成微带贴片天线的制备

This paper demonstrates a technique for microstrip patch antenna fabrication using a benzocyclobutene(BCB) dielectric.The most distinctive feature of this method is that the antenna is integrated on a low-resistance silicon wafer,and is fully compatible with the microwave multi-chip module packaging process.Low-permittivity dielectric BCB with excellent thermal and mechanical stability is employed to enhance the performance of the antenna.The as-fabricated antenna is characterized,and the experimental results show that the antenna resonates at 14.9 GHz with a 1.67% impedance bandwidth.     

VB-GaAs抛光片表面粗糙度研究

将表面粗糙度作为评价垂直布里奇曼法砷化镓(VB-GaAs)抛光片表面质量的一项技术指标,研究了不同粒径的抛光液对VB-GaAs抛光片表面粗糙度的影响.通过试验对比,对于不同抛光阶段(包括粗抛、细抛及精抛三个阶段)进行了分析,粗抛阶段应采用较大粒径的抛光液,细抛阶段应采用稍小粒径的抛光液,而精抛阶段应采用小粒径的抛光液.     

铝薄膜CMP影响因素分析

提出了在碱性抛光液中铝薄膜化学机械抛光的机理模型,对抛光液的pH值、磨料、氧化剂浓度对过程参数的影响做了一些试验分析。试验结果表面粗糙度的铝薄膜所需的最优化CMP过程参数:硅溶胶粒径为15～20nm,pH值为10.8～11.2,氧化剂浓度为2.5%～3%。     

Surface planarization of ZnO thin film for optoelectronic applications

In this paper, surface morphology and optical properties are investigated to find the optimum microstructure of zinc oxide (ZnO) thin films deposited by radio frequency (RF) magnetron sputtering. To achieve a high transmittance and a low resistivity, we examined various film deposition conditions. The transmittance and surface morphology of ZnO thin films were measured by an ultraviolet (UV)-visible spectrometer and atomic force microscopy (AFM), respectively. In order to improve the surface quality of ZnO thin films, we performed chemical mechanical polishing (CMP) by change of process parameters, and compared the optical properties of polished ZnO thin films. As an experimental result, we were able to obtain good uniformity and improved transmittance efficiency by the CMP technique.     

Novel abrasive-free planarization of 4H-SiC (0001) using catalyst

A new abrasive-free planarization method for silicon carbide (SiC) wafers was proposed using the catalytic nature of platinum (Pt). We named it catalyst-referred etching (CARE). The setup equipped with a polishing pad made of Pt is almost the same as the lapping setup. However, CARE chemically removes SiC with an etching agent activated by a catalyst in contrast to mechanical removal by the lapping process. Hydrofluoric acid which is well known as an etchant of silicon dioxide (SiO₂) that cannot etch SiC, was used as the source of the etching agent to SiC. The processed surfaces were observed by Nomarski differential interference contrast (NDIC) microscopy, atomic force microscopy (AFM), and optical interferometry. Those observations presented a marked reduction in surface roughness. Moreover, low-energy electron diffraction (LEED) images showed that a crystallographically well-ordered surface was realized.     

Selective chemical etching of polycrystalline SiGe alloys with respect to Si and SiO2

Polycrystalline SiGe etches that are selective to silicon dioxide as well as silicon are needed for flexibility in device fabrication. A solution of NH₄OH, H₂O₂, and H₂O has been found to selectivity etch polycrystalline silicon-germanium alloys over both silicon and silicon dioxide. Optimum composition of the solution was determined by maximizing etch rates for SiGe films with several germanium compositions. The dependence of etch rates on germanium content, etching temperature, and doping concentration are reported. The etch rate and selectivity are approximately exponentially proportional to the germanium content. Etching was found to be insensitive to deposition method, doping method, and annealing conditions of the SiGe films. In addition, etching leaves a smooth silicon substrate surface after removal of SiGe films.     

Processing and Characterization of Dry-Etch Benzocyclobutene as Substrate and Packaging Material for Neural Sensors

Electrode substrate is one of the most important factors affecting the recording or stimulation efficiency and long-term stability of chronically implanted neural sensors for laboratory research. Various biocompatible polymers have been investigated as potential substrate and packaging material for neural sensors in neuroscience research applications. Dry-etch benzocyclobutene (BCB) is one candidate due to its desirable combination of electrical, mechanical, and thermal properties and its biocompatibility. In this paper, processing techniques were investigated to control the uniformity and pin-pole density of dry-etch BCB film. Dry-etch BCB film as thick as 25 mum with a surface roughness less than 1000 A and a pinhole density less than 1.5 x 10^-3 mm^-2 has been acquired using an optimized coating and curing recipe. A traditional surface micro-machining technique was used to form the metallization and etch masks during the fabrication of the neural electrode based on dry-etch BCB substrate. Special consideration was given to the study of dry-etch BCB thin film patterning using plasma reactive ion etching dry etching. The optimized plasma etch condition shows that greater than 1 mum etch rate and 65deg via angle are the most suitable for the packaging and patterning of the neural probes. The results show that this fabrication process is optimal for chronically implantable neural sensors based on dry-etch BCB thin film as substrate. The process may find applications in other devices using BCB as substrate.     

Low-Roughness Plasma Etching of HgCdTe Masked with Patterned Silicon Dioxide

A novel mask technique utilizing patterned silicon dioxide films has been exploited to perform mesa etching for device delineation and electrical isolation of HgCdTe third-generation infrared focal-plane arrays (IRFPAs). High-density silicon dioxide films were deposited at temperature of 80°C, and a procedure for patterning and etching of HgCdTe was developed by standard photolithography and wet chemical etching. Scanning electron microscopy (SEM) showed that the surfaces of inductively coupled plasma (ICP) etched samples were quite clean and smooth. Root-mean-square (RMS) roughness characterized by atomic force microscopy (AFM) was less than 1.5 nm. The etching selectivity between a silicon dioxide film and HgCdTe in the samples masked with patterned silicon dioxide films was greater than 30:1. These results show that the new masking technique is readily available and promising for HgCdTe mesa etching.     

Effects of substrate surface preparation on chemical vapor deposition growth of 4H-SiC epitaxial layers

The effects of chemical mechanical polish (CMP) and pre-growth oxidation and etching of vicinal 4H−SiC substrates on the quality of epitaxial films have been investigated. Samples with and without a collodial silica CMP and oxidation/etch treatment were studied with optical microscopy, cross section transmission electron microscopy (TEM) and atomic force microscopy (AFM) before and after chemical vapor deposition. Evidence of polishing damage was evident prior to growth in all samples without CMP treatment. Oxidation and etching appeared to generate defects by preferential etching of bulk defects such as dislocations and low angle grain boundaries. Evidence of the polishing damage remained after chemical vapor deposition (CVD) growth on the samples without CMP and the defect density was worse for the oxidized samples compared to the unoxidized ones. The unoxidized CMP wafer had the lowest defect density and rms roughness of the samples studied.     

Annealing-temperature dependence of the thermal conductivity ofLPCVD silicon-dioxide layers

The authors point out that the reliability and performance of electronic circuits are influenced by heat conduction in low-pressure chemical-vapor-deposited (LPCVD) silicon dioxide layers. Here, the effective thermal conductivity k_eff for conduction normal to films of LPCVD silicon dioxide layers as a function of annealing temperature, as well as for films of thermal and SIMOX oxides, is measured. The LPCVD oxide thermal conductivity increases by 23% due to annealing at 1150°C. The conductivities k_eff of LPCVD layers of thicknesses between 0.03 and 0.7 μm are higher than those reported previously for CVD layers, and vary between 50% and 90% of the conductivities of bulk fused silicon dioxide. The values of SIMOX and thermal oxide layers are within the experimental error of the values for bulk fused silicon dioxide