A 4-in.-based single-step UV-NIL tool using a low vacuum environment and additive air pressure

Ultraviolet nanoimprint lithography (UV-NIL) is a promising technology for the fabrication of sub-10-nm features. Research has focused on employing a large-area stamp to improve UV-NIL throughput, but a large-area stamp makes it difficult to obtain an acceptable uniform residual layer thickness and/or avoid defects such as air entrapment. This paper presents the development of a single-step UV-NIL tool in which a 4-in. Pyrex stamp is first used to imprint coated resin against a 4-in. Si wafer in a low vacuum environment. Pressurized N₂ is subsequently applied to the wafer bottom to improve the quality of imprint results. This UV-NIL tool was used to successfully imprint a 4-in. stamp with recessed patterns engraved over the entire stamp areas onto a 4-in. Si wafer.     

Wafer deformation in ultraviolet-nanoimprint lithography using an element-wise patterned stamp

Nanoimprint lithography is a promising method for high-resolution, low-cost nanopatterning. In particular, ultraviolet-nanoimprint lithography (UV-NIL), which requires low imprint pressure, is effective for multi-layer processes. In this study, we investigated the non-uniformity of the residual layer thickness caused by wafer deformation in an experiment that examined different wafer thicknesses using UV-NIL with an element-wise patterned stamp (EPS). The EPS consisted of a number of elements, each separated by a channel. Experiments using the EPS were performed on an EVG620-NIL. Severe deformation of the wafer served as an obstacle to the spread of resin drops, which caused non-uniformity of the residual layer thickness. We also simulated the imprint process using a simplified model and finite element method to analyze the non-uniformity.     

Fabrication of nickel stamp with improved sidewall roughness for optical devices

We proposed the simple and attractive fabrication method of nickel stamp with improved sidewall roughness for polymeric optical devices. For this, the imprinted optical devices patterns under optimum imprinting conditions were annealed to improve the sidewall roughness generated by the DRIE process in the silicon stamp fabrication. The annealed sidewall roughness is reduced to 24.6 nm, nearly decreasing by 76% compared with the result before the annealing. Then, low cost and durable nickel stamp with improved sidewall roughness was fabricated by the annealed polymeric patterns being used as original master for electroforming process. And, we verified the superiority of the improved nickel stamp by comparing the optical propagation losses for optical waveguides to be fabricated, respectively, using the nickel stamp and original silicon stamp. The optical waveguides fabricated by the imprint lithography using the improved nickel stamp was demonstrated that their optical losses were reduced as 0.21 dB/cm, which was less than the propagation loss for polymeric waveguides using the conventional original silicon stamp. This result could show the effectiveness of the fabricated nickel stamp with improved sidewall roughness. Furthermore, we were able to successfully fabricate a polymeric 1 × 8 beam splitter device using the improved nickel stamp. And, the insertion loss for eight channels obtained to be from 10.02 dB to 10.91 dB.     

Large area nanosize array stamp for UV-based nanoimprint lithography fabricated by size reduction process

A novel size reduction process using electron beam lithography (EBL) combining with wet etching technique is developed as a possible solution for producing large area and low cost nanopattern stamp for UV-based nanoimprint lithography (UV-NIL). In the first step, a microstructure stamp with 1.4 μm periodical pore array and aspect ratio of 1:1 was formed over a 1 inch² area on a quartz substrate. This process was carried out using common electron beam lithography (EBL) equipment, which was easily available in the modern integrated circuits (IC) semiconductor factory. Afterwards, with a controlled wet etching technique, the pore array was changed into tip patterns with the line width below 100 nm and the period keeping as before. The uniformities and nanopattern accuracies were investigated to identify its possibility as a UV-NIL stamp by AFM and SEM. Finally, as a demonstration, the as obtained stamp was used as a positive stamp to replicate the nanotips into UV-curable resist successfully by a UV-NIL process. The method developed for the mold of nanoimprint lithography would be a simple and low price approach to fabricate large area UV-NIL stamp and the nanotip array structures would be widely used in two dimensional (2D) photonic crystal application.     

Compact LED based nanoimprinter for UV-NIL

UV-based nanoimprint lithography (UV-NIL) is a cheap and fast way to imprint patterns ranging from nanometres to micrometres. However, commonly used equipment can be expensive and require a clean room infrastructure. Here we present the design and testing of a simple UV-NIL system based on a light emitting diode. The current design permits imprints of 10 × 10 mm² in size using a 25 × 25 mm² master. This printer can be used in a semi-clean environment such as a laminar flow bench. The imprinter was used to imprint photoresists as well as UV sensitised hydrogels. The best results were obtained using SU-8 photoresist with features down to 50 nm in size, only limited by the imprint master. Patterns in SU-8 resist were also transferred into silicon substrates by reactive ion etching demonstrating its full potential as a lithographic tool.     

Study of X-ray lithographic conditions for SU-8 by Fourier transform infrared spectroscopy

There is growing interest in the use of chemically-amplified resists (CARs) such as SU-8 in the field of microelectromechanical systems (MEMS) research. This is due to its outstanding lithographic performance and its ability for use in the fabrication of stable structures with very high aspect ratio. However, it is important to control the processing conditions for optimum results in the desired application. In this investigation, the thickness (10-25 μm) of SU-8 resist film, due to different spin coating speeds on silicon wafers, was measured using Fourier transform infrared (FT-IR) spectroscopy. The effect of thermal-initiated cross-linking at various temperatures (95-160 °C) for 15 min baking time on the 25 μm SU-8 resist was studied by monitoring the 914 cm⁻¹ absorption peak in the FT-IR spectrum. Results of the experiments showed that the onset of thermal-initiated cross-linking begins at about 120 °C. Furthermore, 25 μm SU-8 resist was optimized for X-ray lithographic applications by studying the cross-linking process of the resist under different conditions of post-exposure bake (PEB) temperatures. The exposure dose of soft X-ray (SXR) irradiation with energies about 1 keV from a dense plasma focus (DPF) device was fixed at 2500 mJ/cm² on the resist surface. Results showed that the optimum processing conditions consisted of an intermediate PEB at 65 °C for 5 min, with the PEB temperature ramped up to 95 °C over 1.5 min and then followed by a final PEB at 95 °C for 5 min. The scanning electron microscopy (SEM) images showed SU-8 test structures successfully imprinted, without affecting the resolution, and with aspect ratios of up to 20:1 on 25 μm SU-8 resist.     

Direct soft UV-NIL with resist incorporating carbon nanotubes

As a potential candidate for the next generation of nanolithography, nanoimprint lithography (NIL) has drawn ever-increasing worldwide attention. It involves physical contact to overcome the optical limits occurring in sub-100 nm photolithography. Affordable tool cost is one of major attractive points of NIL. This work proposes the idea of incorporating carbon nanotubes (CNTs) in the resin used for ultraviolet nanoimprinting (UV-NIL). CNTs can make the resin electrically conductive when mixed with it. Patterns imprinted in the CNT-mixed resist can then be used to replace conductive metal structures directly. This enhances the productivity of basic UV-NIL where the imprinted patterns are used as sacrificial etch masks. In this work, several types of CNTs were purified chemically and dispersed before being mixed with UV-NIL resin using ultrasonic vibration. On drops of CNT-mixed resin, soft UV-NIL was performed using a polydimethylsiloxane (PDMS) stamp with a minimum feature size in the range of 200 nm. Even with increased resin viscosity due to the addition of CNTs, UV imprinting down to 200 nm was successfully done with moderate pattern fidelity. The loading rate of nanotubes should be minimized to prevent the increased viscosity from degrading the pattern transfer resolution. The electrical conductivity of CNT-mixed resist increases with the loading of CNTs. Therefore, the trade-off between the electrical properties and pattern transfer resolution needs to be optimized carefully.     

Imprinted polymer stamps for UV-NIL

Thermal step and stamp nanoimprint lithography (SSIL) offers an alternative to fabricate transparent polymer stamps for UV-imprinting. The fabrication process does not require any other subsequent steps, e.g. dry etching or anti adhesive coating.In this work, we have manufactured UV-stamp by combining patterns of two different silicon masters. The patterns of the silicon masters were transferred into resin coated quartz plate by sequential imprinting. The first master consisted gratings with 50 nm features and the second master consisted dot arrays of 350 nm diameter features. The novel idea is the ability to create a large UV-stamp using a combination of small masters. Thus fabricated UV-stamps were used for demonstrating step and repeat UV-imprinting. The quality of the UV-stamps and imprints were analyzed by AFM. High fidelity patterns were achieved in respect to patterns in the original silicon master.     

Soft UV-nanoimprint lithography on non-planar surfaces

We report on a simple and effective process that allows direct UV-imprinting of micro- and nanostructures on non-planar surfaces, even at sharp edges such as step surfaces. The key for the process is the use of a thin flexible polymer stamp, which was fabricated by spin-coating poly(dimethylsiloxane) (PDMS) on a pre-patterned Si or poly(methyl methacrylate) (PMMA) master and releasing the thin PDMS layer after curing. The thin PDMS stamp was used to conformally mold a UV resist layer coated on various non-planar substrates with different radii of curvature. With this method, we have successfully demonstrated micro- and nanopatterns down to 63 nm on curved surfaces as well as sharp step-like structures. The process so developed will improve the versatility and applicability of molding technologies in many applications that require patterning non-planar substrates, considering that most molding technologies allow for patterning only on planar substrates or surfaces with large curvature radii.     

Residue-free room temperature UV-nanoimprinting of submicron organic thin film transistors

In this study we report on an innovative nanoimprint process for the fabrication of entirely patterned submicron OTFTs in a bottom-gate configuration. The method is based on UV-Nanoimprint Lithography (UV-NIL) combined with a novel imprint resist whose outstanding chemical and physical properties are responsible for the excellent results in structure transfer. In combination with a pretreated stamp the UV-curable resist enables residue-free imprinting thus making etching obsolete. A subsequent lift-off can be done with water. The UV-NIL process implies no extra temperature budget, is time saving due to short curing times, eco-friendly due to a water-based lift-off, simple because it is etch-free and completely r2r compatible. It works perfectly even if ultra-thin organic and hybrid films are used as gate dielectrics. On this basis entirely patterned functional submicron OTFTs with pentacene as the semiconductor are fabricated showing clear saturation, low switch-on voltage (～3 V) and a sufficiently high on–off ratio (10³).     

144 Channel measurement IC for CdZnTe sensors with energy and time resolution

A 144 channel measurement IC for CdZnTe detectors, used for PET, is presented. Each channel consists of a charge sensitive amplifier, a fast and a slow shaper, a peak sampler for the energy acquisition and an event detector based on a time to digital converter to generate an accurate time stamp for each event. The channels are multiplexed to a fast pipeline ADC on demand. Measurement results for the ASIC showed a noise equivalent input charge of 800 e⁻ rms and a time resolution of 737 ps rms. Evaluation results with a CdZnTe detector yielded an energy resolution of 4.4% full width half maximum at 662 keV with a ¹³⁷Cs radiation source. The IC is implemented on a 180 nm CMOS process with a total chip size of 100 mm².     

Innovative scheme for selective carbon nanotubes integration in via structures

Thanks to their outstanding electrical properties [1] and [2], carbon nanotubes (CNTs) are promising candidate to replace Cu in advanced interconnects [3], [4], [5], [6], [7] and [8]. In damascene based CNT via integration scheme, CNTs growth occurs on the whole surface of the wafers: in vias, but also on top surfaces [5]. CNTs on top are subsequently removed by polishing. In this paper, an alternative integration scheme is proposed which avoids CNTs on top. Thanks to careful choice of top surface (TiN) and bottom electrode (doped silicon) materials, CNT growth occurs only in vias. Dense growth (6 × 10¹¹ CNTs/cm²) of small multi wall CNTs is achieved in vias over doped poly-silicon lines. Good encapsulation of CNTs is obtained with SACVD SiO₂ or ALD Al₂O₃ materials. Thanks to polishing of emerging CNTs, planarized CNT vias are obtained. Initial electrical measurements by conductive AFM show the conductivity of these CNT vias.     

UV enhanced substrate conformal imprint lithography (UV-SCIL) technique for photonic crystals patterning in LED manufacturing

The global LED (light emitting diode) market reached 5 billion dollors in 2008 and will be driven towards 9 billion dollors by 2011 [1]. The current applications are dominated by portable device backlighting, e.g. cell phones, PDAs, GPS, laptop etc. In order to open the general lighting market doors the luminous efficiency needs to be improved significantly. Photonic crystal (PhC) structures in LEDs have been demonstrated to enhance light extraction efficiency on the wafer level by researchers [2]. However, there is still a great challenge to fabricate PhC structures on LED wafers cost-effectively. Nanoimprint lithography (NIL) [3] has attracted considerable attentions in this field due to its high resolution, high throughput and low cost of ownership (CoO). However, the current NIL techniques with rigid stamps rely strongly on the substrate flatness and the production atmosphere. Those factors hinder the integration of NIL into high volume production lines. UV-NIL with flexible stamps [4], e.g. PDMS stamps, allows the large-area imprint in a single step and is less-sensitive to the production atmosphere. However, the resolution is normally limited due to stamp distortion caused by imprint pressure.A novel NIL technique developed by Philips Research and Süss MicroTec, substrate conformal imprint lithography (SCIL), bridges the gap between UV-NIL with rigid stamp for best resolution and soft stamp for large-area patterning. Based on a cost-effective upgrade on Süss mask aligner, the capability can be enhanced to nanoimprint with resolution of down to sub-10 nm on an up to 6 inch area without affecting the established conventional optical lithographic processes on the machine. Benefit from the exposure unit on the mask aligners, the SCIL process is now extended with UV-curing option, which can help to improve the throughput dramatically. In this paper, the fabrication of photonic crystal structures with SCIL technique on Süss MA6 mask aligner is demonstrated. In addition, the industrialization considerations of UV-SCIL process in high volume manufacturing are briefly discussed.     

Metal-organic vapor-phase epitaxial growth of HgCdTe device heterostructures on three-inch-diameter substrates

A new metal-organic vapor-phase epitaxial (MOVPE) reactor-cell design has been developed to grow on 3-in.-diameter substrates. This was required to produce uniform, fully doped heterostructures needed for array producibility and wafer-scale processing compatibility. The reactor has demonstrated epitaxial growth of HgCdTe (MCT) with good morphology onto both GaAs and GaAs on Si wafers. The density of surface-growth defects, typical of MOVPE growth, has been reduced to <5 cm⁻² at a sufficient yield to make the production of low cluster-defect, two-dimensional (2-D) arrays possible. The new horizontal reactor cell uses substrate rotation to achieve improved uniformity and is able to incorporate substrates up to 4-in. diameter. Good compositional and thickness uniformity was achieved on epilayers grown on 3-in.-diameter, low-cost GaAs and GaAs on Si wafers. Sufficient uniformity has been achieved to produce 12 sites of full-TV format 2-D arrays per slice. To yield the benefits of heterostructure design, the MCT epilayers also needed to demonstrate efficient and uniform activation of both arsenic (acceptor) and iodine (donor) dopants. Secondary ion mass spectrometry (SIMS) and Hall assessment showed that the uniformity of As and I doping was ±10%. Fully doped heterostructures have been grown to investigate the device performance in the 3–5 μm and 8–12 μm infrared bands. The 2-D array performance has shown that at 180 K near-background-limited performance (BLIP) diodes have been produced in the 3–5 μm band.     

A non-fluorine mold release agent for Ni stamp in nanoimprint process

This study presents a novel material as an anti-adhesive layer between Ni mold stamps and polymethyl methacrylate (PMMA) substrate in nanoimprint process. A polybenzoxazine ((6,6’-bis(2,3-dihydro-3-methyl-4H-1,3-benzoxazinyl))) molecule self-assembled monolayer (PBO-SAM) considering as anti-adhesive coating agent demonstrates that non-fluorine-containing compounds can be improve the nanoimprint process in Ni/PMMA substrates. In this work, the nanostructure-based Ni stamps and the imprinted PMMA mold are performed by electron-beam lithograph (EBL) and our homemade nanoimprint equipment, respectively. To control the forming of fabricated nanopatterns, the simulation can be analyzed their effect of temperature distributions on the deformation of PBO-SAM/PMMA substrate during hot embossing lithography (HEL) process. Herein the diameter of pillar patterns is 200 nm with and 400 nm pitch on Ni stamp surface. Based on the hydrophobic PBO-SAM surface in this conforming condition, the results of Ni mold stamps infer over 90% improvement in controlling quality and quantity.     

High quality relaxed Ge layers grown directly on a Si(0 0 1) substrate

After a long period of developing integrated circuit technology through simple scaling of silicon devices, the semiconductor industry is now embracing technology boosters such as strain for higher mobility channel material. Germanium is the logical supplement to enhance existing technologies, as its material behaviour is very close to silicon, and to create new functional devices that cannot be fabricated from silicon alone (Hartmann et al. (2004) [1]). Germanium wafers are, however, both expensive and less durable than their silicon counterparts. Hence it is highly desirable to create a relaxed high quality Ge layer on a Si substrate, with the provision that this does not unduly compromise the planarity of the system. The two temperature method, proposed by Colace et al. (1997) [2], can give smooth (RMS surface roughness below 1 nm) and low threading dislocation density (TDD <10⁸ cm⁻²) Ge layers directly on a Si(0 0 1) wafer (Halbwax et al. (2005) [3]), but these are currently of the order of 1-2 μm thick (Hartmann et al. (2009) [4]).We present an in depth study of two temperature Ge layers, grown by reduced pressure chemical vapour deposition (RP-CVD), in an effort to reduce the thickness. We report the effect of changing the thickness, of both the low temperature (LT) and the high temperature (HT) layers, emphasising the variation of TDD, surface morphology and relaxation.Within this study, the LT Ge layer is deposited directly on a Si(0 0 1) substrate at a low temperature of 400 °C. This low temperature is known to generate monolayer islands (Park et al. (2006) [5]), but is sufficiently high to maintain crystallinity whilst keeping the epitaxial surface as smooth as possible by suppressing further island growth and proceeding in a Frank-van der Merwe growth mode. This LT growth also generates a vast number of dislocations, of the order of 10⁸-10⁹ cm⁻², that enable the next HT step to relax the maximum amount of strain possible. The effect of varying the HT layer thickness is studied by depositing on a LT layer of fixed thickness (100 nm) at a higher growth temperature of 670 °C. We find that the HT layer allows Ge-on-Ge adatom transport to minimise the surface energy and smooth the layer. The final step to the technique is annealing at a high temperature that allows the dislocations generated to glide, increasing the degree of relaxation, and annihilate. We find that annealing can reduce the TDD to the order of 10⁷ cm⁻², but at a cost of a significantly roughened surface.     

Fabrication and characterization of Co-Pt nanodot arrays by nanoimprint lithography and electrodeposition

Co-Pt nanodot arrays of 50 nm in diameter and 100 nm pitch were fabricated by nanoimprint lithography and electrodeposition process. A polymer mold used was replicated from a Si master mold with nanopatterns which were fabricated by EBL and ICP-RIE, where hydrophobic surface of these was achieved by FOTS coating. UV-NIL was successfully performed under pressures of 5 MPa for 5 min with an UV exposure time of 30 s, where the substrate was Ru (30 nm)/NiFe (10 nm)/Ta (5 nm)/Si (1 0 0). The size of patterns was measured at 53 nm in diameter, 25 nm in height, 100 nm in pitch. Finally, Co-Pt nanodot arrays were galvanostatically electrodeposited and characterized. The size and the composition of these arrays were measured to be 50 nm in diameter and 100 nm in pitch and Co-23.6 at.% Pt, respectively. According to MFM analysis, these arrays for the remnant states represent a single domain structure of perpendicular direction with a magnetic field, where a field of 15 kOe was applied perpendicular to the sample plane. These results show that for the Co-Pt dot arrays of 50 nm diameter perpendicular magnetic signal can be recorded and switched.     

Development of reliable low temperature wafer level hermetic bonding using composite seal joint

A reliable composite metal seal comprising both intermetallic compounds (IMC) and solder joints, which are formed by transient liquid phase bonding and soldering respectively, is proposed and demonstrated in wafer level bonding experiments. Hermetic sealing is demonstrated on 8-in. wafers using low volume Cu/Sn materials at process temperatures as low as 280 °C. It is shown that the composite seal is stable when subjected to temperatures of 250 °C, and that it provides better hermeticity and reliability than an IMC seal alone.     

Polymer film deposition with fine pitch openings by stencil printing

It is confirmed that stencil printing with a novel developed printable polyimide paste can be used for polymer film deposition on LSI wafers. A thick polyimide film with openings for solder ball bumping can be deposited on all of the LSIs on a wafer by stencil printing at one time. This stencil printing process does not need an expensive lithography process, providing cost-effective wafer-level chip scale packages (WLCSPs). In this study, a novel polyimide paste was tailored to have a higher thixotropy ratio than conventional printable polyimide materials. The novel printable polyimide paste shows that the viscosity ratio of more than 3.5 at the shear rate of 1 to 10 s⁻¹ and that the viscosity increases rapidly after the shear rate is lowered. Fine spaces of 40 μm between 250 μm openings were obtained for 10 μm thick polyimide films on Si wafers. It has been also confirmed that the new paste shows the variation range of 30 μm at the opening size of 385 μm within 100 continuously printed wafers. Even after the new paste was shear-thinned repeatedly, rheological behavior of the new paste was not changed. This robustness leads to higher efficiency of the materials for mass-producing. From the reliability viewpoint of the printed polyimide films, no peelings were observed on plasma-CVD SiN films after the pressure cooker test under the condition of 127 °C and 0.25 MPa with the humidity of 100% for 300 h. The optimal stencil printing process using the novel developed paste will lead to significant cost reduction of a patterned polymer deposition process. Finally, WLCSPs using the stencil printing of the new polyimide paste have been demonstrated for SRAM LSIs on 8-in. wafers.