100-nm n-/p-channel I-MOS using a novel self-aligned structure

We have fabricated a 100-nm n-/p-channel I-MOS by adopting a novel structure. The proposed structure shows some advantages over the conventional one in terms of self-alignment and reduced number of photolithography masks. It leads to low fabrication cost, accelerated scaling down, and enhanced performance due to reduced parasitic elements. It shows a normal transistor operation with small subthreshold swing less than 11.8 mV/dec at room temperature. The n- and p-channel I-MOS have an ON/OFF current of 81.1/2.8 and 78.2/3.4 /spl mu/A per /spl mu/m, respectively. The device performance provides a promise for near-ideal switch application.     

A new nonlinear capacitance model of millimeter wave power PHEMT for accurate AM/AM-AM/PM simulations

A new one-dimensional (1-D) nonlinear gate-source Cgs and gate-drain Cgd capacitance model designed for power-PHEMT transistors is presented. The capacitance values are extracted from measured [S] parameters, along a load-line corresponding to a power performance of an optimum amplifier design. The reliable resulting model predicts adequate power performances with small or large signals in reduced CPU time. This new model is validated by comparisons between load-pull power measurements at 25.5 GHz and harmonic balance simulations. It reveals good accuracy for AM/AM and AM/PM predictions.     

Numerical Estimation of Yield in Sub-100-nm SRAM Design Using Monte Carlo Simulation

This paper describes a method to numerically calculate the design margin and to estimate the yield associated with the read access failure for sub-100-nm SRAM. Process variations at sub-100 nm not only affect SRAM cells but also periphery circuits, such as the sense amplifier (SA) and the tracking scheme. Simulation that incorporates both SRAM cells and surrounding circuits is either accurate but computationally expensive (comprehensive Monte Carlo simulation), or overly simple (fixed corner design) and unable to capture crucial statistical variation concern, dominant in sub-100-nm designs. By mathematically combining the separate Monte Carlo simulation results of SRAM cells and each peripheral block, we show that the distribution of the SA input voltage can be estimated accurately in a case where fixed corner simulation underestimates by 19%. We also present the yield equation by combining the SA input voltage and the SA offset distribution, which can be used to choose the design point. In addition, yield sensitivities are derived from the yield data to make sure that the yield has good dependence to design variables.      

点云边界快速精确提取算法

点云边界提取是点云三维重建中极其关键的一步, 现有的边界提取算法大多采用一种 判别准则进行边界点提取,导致提取的效率低或者提取效果不理想。针对上述问题,本文提 出一种快速精确的点云边界提取算法,其包括粗提取与精提取两个步骤。粗提取中对任意点 ,利用Kdtree搜索其近邻点,对该点与其近邻点构成的单位法向量进行叠加,依据叠加后 向量的模长与近邻数的比值粗提取出边界点;精提取中对于粗提取出的边界点,搜索其近邻 点并依据近邻点拟合成平面,再将近邻点投影到该平面上,根据判断点的投影点与近邻点的 投影点连线间的最大夹角精确提取出边界点。使用地面与机载两类不同的点云数据验证本算 法,实验结果表明:本算法均可以准确提取出这两种点云的边界点,同时在提取机载点云边 界上效率提高了6.8倍,在地面点云中提高了2倍。本文算法可用于快 速提取边界点,有利用后续点云重建。     

Inversion MOS capacitance extraction for high-leakage dielectricsusing a transmission line equivalent circuit

Accurate measurement of MOS transistor inversion capacitance with a physical silicon dioxide thickness less than 20 Å requires correction for the direct tunneling leakage. This work presents a capacitance model and extraction based on the application of a lossy transmission line model to the MOS transistor. This approach properly accounts for the leakage current distribution along the channel and produces a gate length dependent correction factor for the measured capacitance that overcomes discrepancies produced through use of previously reported discrete element based models. An extraction technique is presented to determine the oxide's tunneling and channel resistance of the transmission line equivalent circuit. This model is confirmed by producing consistent C_0x measurements for several different gate lengths with physical silicon dioxide thickness of 9, 12, and 18 Å     

A generalized algorithm for the capacitance extraction of 3D VLSIinterconnects

In this paper, a generalized algorithm based upon the nonoverlapping domain decomposition method (NDDM) is presented for the capacitance extraction of three-dimensional (3-D) VLSI interconnects. The subdomains with conductors are analyzed by the finite-difference method, while the subdomains with pure dielectric layers are analyzed with the eigenmode expansion technique. The central processing unit time and memory size used by the NDDM are unrelated to the thickness of pure dielectric layers. NDDM's computing time grows as O(n) if the number of domain iterations is bounded. Also, benchmarks show that it is approximately 15 times less than those used by Ansoft's Maxwell SpiceLink. In addition, only a two-dimensional mesh is needed to analyze 3-D structures. This greatly reduces the algorithm complexity and makes it easy and straightforward to interface with layout automation software     

热壁LPCVD设备TEOS工艺炉管的使用与维护

通过介绍热壁LPCVD的TEOS工艺淀积SiO2薄膜的原理,分析了在淀积薄膜的过程中经常遇到的薄膜均匀性等方面的问题。重点分析了硅片中心与石英管轴心所处的相对位置对片内薄膜均匀性的影响关系、石英舟的位置以及恒温区的温度控制对片间均匀性的影响关系,并详细地分析、给出了具体的调整方法。对于该工艺炉管在实际的使用过程中经常遇到的一些故障现象,分析了产生故障的原因并提出了解决方法。最后对TEOS工艺炉管在日常使用过程中的保养和维护给出了一些建议。     

Low- and high-frequency capacitance of aluminum gallium nitride/gallium nitride heterostructures with interface traps

We have studied frequency dependence of capacitance properties of aluminum gallium nitride/gallium nitride (AlGaN/GaN) heterostructures with interface traps at the AlGaN/GaN interface. We have shown that ability of charge in interface traps to respond to external measuring signal is responsible for the frequency dispersion of capacitance curves. The difference between capacitance curves measured at low and high frequencies in experimental structures is similar to the difference between simulated capacitances of the heterostructures with interface traps measured at low and high frequencies. At a high frequency when the charge in interface traps does not follow the measuring signal, the capacitance curves are only shifted in voltage compared to the curve of the structure without interface traps. But for low frequency a capacitance peak is observed. Interface traps hence contribute to experimentally observed capacitance dispersion.     

面向制导律设计的目标信息估计方法研究

针对制导律对目标信息的需求问题,利用超球体单形sigma采样平方根UKF滤波方法估计出弹目相对运动信息,提高了制导精度。首先基于变结构控制方法设计了滑模制导律,其次,针对制导信息的需求,建立了超球体单形sigma采样平方根UKF滤波系统,该滤波方法在处理弹目非线性关系时,采用对非线性函数的概率分布进行近似而不是对非线性函数进行近似,在估计弹目状态信息时比扩展卡尔曼滤波更加精确,并且保证了数值的稳定性。最后通过数学仿真,不仅验证了该滤波算法的有效性,而且提高了对大机动目标的制导精度。     

Enhanced QMM-BEM solver for three-dimensional multiple-dielectric capacitance extraction within the finite domain

The computational time and memory of three-dimensional capacitance extraction have been greatly reduced by using a quasi-multiple medium (QMM) technology, because it enlarges the matrix sparsity produced by the direct boundary element method. In this paper, an approach to automatically determining the QMM cutting pair number and a preconditioning technique are proposed to enhance the QMM-based capacitance extraction. With these two enhancements, the capacitance extraction can achieve much higher speed and adaptability. Experimental results examine the efficiency of two enhancements and show over 10/spl times/ speed-up and memory saving over the multipole approach with comparable accuracy.     

Optimization and realization of sub-100-nm channel length singlehalo p-MOSFETs

Single halo p-MOSFETs with channel lengths down to 100 nm are optimized, fabricated, and characterized as part of this study. We show extensive device characterization results to study the effect of large angle V_T adjust implant parameters on device performance and hot carrier reliability. Results on both conventionally doped and single halo p-MOSFETs have been presented for comparison purposes     

Comparison of deposition models for a TEOS LPCVD process

We present a comparison of models describing the pyrolytic deposition of SiO₂ with a low pressure chemical vapor deposition process. In order to meet industrial simulation requirements, e.g. accuracy and fast delivery of results, we present an overview of established and new models, their use within TCAD applications, and their best results which have been obtained by calibrations according to SEM measurements.     

Applicability limits of the two-frequency capacitance measurementtechnique for the thickness extraction of ultrathin gate oxide

Reliable techniques for extracting the gate dielectric layer thickness from capacitance-voltage (C-V) characteristics are essential for manufacturing process quality control. Continued reduction of the dielectric layer thickness has brought about a need for new measurement procedures which can account for the direct tunneling currents through the gate insulator. We present a guideline for performing two-frequency C-V analysis of sub-2 nm gate oxides and show that it is possible to extract the dielectric layer thickness with an error of less than 4%. We show that in order to achieve this level of accuracy, it is necessary to choose the measurement frequencies and the test device size so that the dissipation remains below 1.1 at least at one of the two measurement frequencies     

Measurement method for accurate extraction of the base-to-emitterintrinsic and peripheral capacitances of bipolar transistors

A simple measurement method to determine the intrinsic and peripheral emitter junction capacitances is described. The method is based on measurements of BJT's with different emitter geometries and is demonstrated on transistors of an advanced BiCMOS technology. The method can be applied directly to standard deep-submicrometer devices. No special test devices are required. By determining peripheral capacitance for different processes, the method enables the examination of process schemes designed to suppress the effect of the peripheral emitter on the transistor action. The method also provides a useful approach to monitor the scaling behavior of the intrinsic and peripheral capacitances. Results indicate the peripheral capacitance starts dominating the total capacitance as the emitter is scaled into the submicrometer range. For devices with quarter micron emitter widths, the peripheral capacitance is found to be 3 to 4 times higher than the intrinsic capacitance, and puts a fundamental limitation on device design     

Analysis of leakage currents and impact on off-state powerconsumption for CMOS technology in the 100-nm regime

Off-state leakage currents have been investigated for sub-100 nm CMOS technology. The two leakage mechanisms investigated in this work include conventional off-state leakage due to short channel effects and gate leakage through ultrathin gate oxides. The conventional off-state leakage due to short channel effects exhibited the similar characteristics as previously published; however, gate leakage introduces two significant consequences with respect to off-state power consumption: (1) an increase in the number of transistors contributing to the total off-state power consumption of the chip and (2) an increase in the conventional off-state current due to gate leakage near the drain region of the device. Using experimentally measured data, it is estimated that gate leakage does not exceed the off-state specifications of the National Technology Roadmap for Semiconductors for gate oxides as thin as 1.4 to 1.5 nm for high performance CMOS. Low power and memory applications may be limited to an oxide thickness of 1.8 to 2.0 nm in order to minimize the off-state power consumption and maintain an acceptable level of charge retention. The analysis in this work suggests that reliability will probably limit silicon oxide scaling for high performance applications whereas gate leakage will limit gate oxide scaling for low power and memory applications     

The First Fully Integrated Quad-Band GSM/GPRS Receiver in a 90-nm Digital CMOS Process

We present the receiver in the first single-chip GSM/GPRS transceiver that incorporates full integration of quad-band receiver, transmitter, memory, power management, dedicated ARM processor and RF built-in self test in a 90-nm digital CMOS process. The architecture uses Nyquist rate direct RF sampling in the receiver and an all-digital phase-locked loop (PLL) for generating the local oscillator (LO). The receive chain uses discrete-time analog signal processing to down-convert, down-sample, filter and analog-to-digital convert the received signal. A feedback loop is provided at the mixer output and can be used to cancel DC-offsets as well to study linearization of the receive chain. The receiver meets a sensitivity of$-$110 dBm at 60mA in a 1.4-V digital CMOS process in the presence of more than one million digital gates.     

Direct sub-100-nm patterning of an organic low-k dielectric for electrical and optical interconnects

Low-k dielectric materials compatible with copper interconnect fabrication processes extending to the sub-50-nm technology nodes are desired for high speed integrated circuit (IC) fabrication. We demonstrate that bisbenzocyclobutene (BCB), an organic low-k dielectric material, can be patterned with sub-100-nm resolution using electron beam lithography, providing new avenues for nanoscale electrical and optical interconnect fabrication.     

ICCAP-a linear time sparsification and reordering algorithm for 3-D BEM capacitance extraction

This paper presents an efficient, simple, hierarchical, and sparse three-dimensional capacitance extraction algorithm, i.e., ICCAP. Most previous capacitance extraction algorithms, such as FastCap and HiCap, introduce intermediate variables to facilitate the hierarchical potential calculation, but still preserve the basic panels as basis. In this paper, we discover that those intermediate variables are a fundamentally much better basis than leaf panels. As a result, we are able to explicitly construct the sparse potential coefficient matrix and solve it with linear memory and linear run time in comparison with the most recent hierarchical O(nlogn) approach in PHiCap. Furthermore, the explicit sparse formulation of a potential matrix not only enables the usage of preconditioned Krylov subspace iterative methods, but also the reordering technique. A new reordering technique, i.e., level-oriented reordering (LOR), is proposed to further reduce over 20% of memory consumption and run time compared with no reordering techniques applied. In fact, LOR is even better than the state-of-the-art minimum degree reordering and more efficient. Without complicated orthonormalization matrix computation, ICCAP is very simple, efficient, and accurate. Experimental results demonstrate the superior run time and memory consumption over previous approaches while achieving similar accuracy.     

Application features of the error correction coding in sub-100-nm memory microcircuits for cosmic systems

The studies performed in the process of designing error correction coding elements in sub-100-nm memory and microprocessor microcircuits confirm that the most efficiency of increasing upset tolerances of commercial RHBD memory microcircuits can be ensured by combining modern circuit solutions for memory elements and algorithmic data encoding and protection methods. Among the circuit methods, the following methods are urgent: the application of DICE memory cells for checking (reference) data files; the introduction of additional columns and multiplexers, intended to replace any column with an additional one, if a multiple incurable upset arises in this column; the implementation of data interleaving with a degree of no more than 8 s to minimize adjacent upsets in the code word. Algorithmic encoding approaches of (SEC-DED-DAEC) classes (single-error correction, double-error-detection, and double-adjacent-error-correction) are efficient for ensuring the upset tolerance of sub-100-nm very-largescale integration (VLSI) circuits under the external action of single nuclear particles. The encoding algorithm based on these recommendations demonstrated up to 27% better efficiency of correction of nonadjacent double errors at a slightly slower speed of operation and occupied on-chip area, as compared with Datta and Choi codes, thus allowing one to implement different implementation versions of upset tolerant VLSI circuits, depending on the solved problem.     

Gate-source-drain architecture impact on DC and RF performance of sub-100-nm elevated source/drain NMOS transistors

It has been known that using selective epitaxial growth (SEG) of silicon, to elevate source/drain regions, is beneficial to digital CMOS by reducing the junction leakage. In addition, this architecture also reduces the gate resistance by enabling a T-shape gate and allowing thicker silicides, which is beneficial for RF-CMOS regarding increased maximum oscillation frequency (f/sub max/) and lowering of the noise figure (NF). In this paper, we report the impact of the SEG-deep source/drain implant (DSDI) process sequence and Co silicide thickness on DC and RF performance of NMOS transistors. Up to a 28%-45% improvement in f/sub max/ is achievable due to a T-shaped gate and thicker Co, made possible by an elevated source/drain (/sup E/S/D) architecture. The maximum transconductance (g/sub m/) of the /sup E/S/D device reaches a value of 1100 mS/mm, which in turn gives a very high f/sub T/ of 150 GHz. The low gate sheet resistance obtained with this architecture is also very beneficial for suppressing noise figure in the low-noise amplifier (LNA) circuit demonstrated in this paper. Furthermore, it is shown by simulation that the noise performance of an RF LNA improves due to the SEG and the Co thickness in the T-shaped gate of the NMOS transistor.