A low-voltage low-power CMOS voltage reference based on subthreshold MOSFETs

This paper describes a CMOS voltage reference using only resistors and transistors working in weak inversion,without the need for any bipolar transistors.The voltage reference is designed and fabricated by a 0.18μm CMOS process.The experimental results show that the proposed voltage reference has a temperature coefficient of 370 ppm/℃at a 0.8 V supply voltage over the temperature range of-35 to 85℃and a 0.1%variation in supply voltage from 0.8 to 3 V.Furthermore,the supply current is only 1.5μA at 0.8 V supply voltage.     

闭环曲率补偿的低电源电压带隙基准源

A new low-voltage CMOS bandgap reference （BGR） that achieves high temperature stability is proposed. It feeds back the output voltage to the curvature compensation circuit that constitutes a closed loop circuit to cancel the logarithmic term of voltage VBE. Meanwhile a low voltage amplifier with the 0.5 μm low threshold technology is designed for the BGR. A high temperature stability BGR circuit is fabricated in the CSMC 0.5μm CMOS technology. The measured result shows that the BGR can operate down to 1 V, while the temperature coefficient and line regulation are only 9 ppm/℃ and 1.2 mV/V, respectively.     

一种应用于RFID的低功耗温度传感器

This paper presents the design and implement of a CMOS smart temperature sensor,which consists of a low power analog front-end and a 12-bit low-power successive approximation register(SAR) analog-to-digital converter(ADC).The analog front-end generates a proportional-to-absolute-temperature(PTAT) voltage with MOSFET circuits operating in the sub-threshold region.A reference voltage is also generated and optimized in order to minimize the temperature error and the 12-bit SAR ADC is used to digitize the PTAT voltage.Using 0.18 m CMOS technology,measurement results show that the temperature error is0.69/C0.85 °C after one-point calibration over a temperature range of40 to 100 °C.Under a conversion speed of 1K samples/s,the power consumption is only 2.02 W while the chip area is 230225 m2,and it is suitable for RFID application.     

一种应用于能量攫取系统的低功耗的工作于亚阈值区域的基准电压源的设计

We propose a bandgap reference, which works in sub-threshold regions to the reduce power consumption in applications such as those in energy harvesting systems that stimulate the development of power management for low power consumption applications.Measurements shows that the supply current of the proposed bandgap reference is only 6.87 μA, including a voltage buffer consuming 3.6 μA of supply current, when the supply voltage is 5 V.The supply voltage can vary from 3 to 11 V and the line regulation of the proposed bandgap reference output voltage is 0.875 mV/V at room temperature.The temperature coefficiency is 88.9 ppm from 10 to 100° C when the supply voltage is 5 V.     

An inherent curvature-compensated voltage reference using non-linearity of gate coupling coefficient

A novel current-mode voltage reference circuit which is capable of generating sub-1 V output voltage is presented. The proposed architecture exhibits the inherent curvature compensation ability. The curvature compensation is achieved by utilizing the non-linear behavior of gate coupling coefficient to compensate non-linear temperature dependence of base-emitter voltage. We have also utilized the developments in CMOS process to reduce power and area consumption. The proposed voltage reference is analyzed theoretically and compared with other existing methods. The circuit is designed and simulated in 180 nm mixed-mode CMOS UMC technology which gives a reference level of 246 mV. The minimum required supply voltage is 1 V with maximum current drawn of 9.24 μA. A temperature coefficient of 9 ppm/℃ is achieved over -25 to 125 ℃ temperature range. The reference voltage varies by ±11 mV across process corners. The reference circuit shows the line sensitivity of 0.9 mV/V with area consumption of 100 × 110 μm².     

A 14-bit wide temperature range differential SAR ADC with an on-chip multi-segment BGR

A 14-bit low power self-timed differential successive approximation(SAR) ADC with an on-chip multisegment bandgap reference(BGR) is described.An on-chip multi-segment BGR,which has a temperature coefficient of 1.3 ppm/℃and a thermal drift of about 100μV over the temperature range of -40 to 120℃is implemented to provide a high precision reference voltage for the SAR ADC.The Gray code form is utilized instead of binary form mode control to reduce substrate noise and enhance the linearity of the whole system.Self-timed bit-cycling is adopted to enhance the time efficiency.The 14-bit ADC was fabricated in a TSMC 0.13μm CMOS process. With the on-chip BGR,the SAR ADC achieves an SNDR of 81.2 dB(13.2 ENOB) and an SFDR of 85.2 dB with a conversion rate of 2 MS/s at room temperature and can keep an ENOB of more than 12 bits at a conversion rate of 2 MS/s over the temperature range from -40 to 120℃.     

一种带热滞回保护的高精度高电源抑制比带隙基准源

To meet the accuracy requirement for the bandgap voltage reference by the increasing data conversion precision of integrated circuits, a high-order curvature-compensated bandgap voltage reference is presented employing the characteristic of bipolar transistor current gain exponentially changing with temperature variations. In addition, an over-temperature protection circuit with a thermal hysteresis function to prevent thermal oscillation is proposed. Based on the CSMC 0.5 μ m 20 V BCD process, the designed circuit is implemented; the active die area is 0.17 × 0.20 mm². Simulation and testing results show that the temperature coefficient is 13.7 ppm/K with temperature ranging from –40 to 150 ℃, the power supply rejection ratio is –98.2 dB, the line regulation is 0.3 mV/V, and the power consumption is only 0.38 mW. The proposed bandgap voltage reference has good characteristics such as small area, low power consumption, good temperature stability, high power supply rejection ratio, as well as low line regulation. This circuit can effectively prevent thermal oscillation and is suitable for on-chip voltage reference in high precision analog, digital and mixed systems.     

一种新颖的片内高压转低压电源转换方案

A novel power supply transform technique for high voltage IC based on the TSMC 0.6μm BCD process is achieved. An adjustable bandgap voltage reference is presented which is different from the traditional power supply transform technique. It can be used as an internal power supply for high voltage IC by using the push-pull output stage to enhance its load capability. High-order temperature compensated circuit is designed to ensure the precision of the reference. Only 0.01 mm^2 area is occupied using this novel power supply technique. Compared with traditional technique, 50% of the area is saved, 40% quiescent power loss is decreased, and the temperature coefficient of the reference is only 4.48 ppm/℃. Compared with the traditional LDO （low dropout） regulator, this power conversion architecture does not need external output capacitance and decreases the chip-pin and external components, so the PCB area and design cost are also decreased. The testing results show that this circuit works well.     

A sub-1 V high-precision CMOS bandgap voltage reference

A third-order, sub-1 V bandgap voltage reference design for low-power supply, high-precision applications is presented. This design uses a current-mode compensation technique and temperature-dependent resistor ratio to obtain high-order curvature compensation. The circuit was designed and fabricated by SMIC 0.18 μm CMOS technology. It produces an output reference of 713.6 mV. The temperature coefficient is 3.235 ppm/℃ in the temperature range of -40 to 120 ℃, with a line regulation of 0.199 mV/V when the supply voltage varies from 0.95 to 3 V. The average current consumption of the whole circuit is 49 μA at the supply voltage of 1 V.     

A fast transient response low dropout regulator with current control methodology

A transient performance optimized CCL-LDO regulator is proposed.In the CCL-LDO,the control method of the charge pump phase-locked loop is adopted.A current control loop has the feedback signal and reference current to be compared,and then a loop filter generates the gate voltage of the power MOSFET by integrating the error current.The CCL-LDO has the optimized damping coefficient and natural resonant frequency, while its output voltage can be sub-l-V and is not restricted by the reference voltage.With a 1μF decoupling capacitor,the experimental results based on a 0.13μm CMOS process show that the output voltage is 1.0 V;when the workload changes from 100μA to 100 mA transiently,the stable dropout is 4.25 mV,the settling time is 8.2μs and the undershoot is 5.11 mV;when the workload changes from 100 mA to 100μA transiently,the stable dropout is 4.25 mV,the settling time is 23.3μs and the overshoot is 6.21 mV.The PSRR value is more than -95 dB.Most of the attributes of the CCL-LDO are improved rapidly with a FOM value of 0.0097.     

Resolution Enhancement Technology:Integrated Process Solutions using OPC

DUV lithography, using the 248 nm wavelength, is a viable manufacturing option for devices with features at 130 nm and less. Given the low kl value of the lithography, integrated process development is a necessary method for achieving acceptable process latitude. The application of assist features for rule based OPC requires the simultaneous optimization of the mask, illumination optics and the resist.Described in this paper are the details involved in optimizing each of these aspects for line and space imaging.A reference pitch is first chosen to determine how the optics will be set. The ideal sigma setting is determined by a simple geometrically derived expression. The inner and outer machine settings are determined, in turn,with the simulation of a figure of merit. The maximum value of the response surface of this FOM occurs at the optimal sigma settings. Experimental confirmation of this is shown in the paper.Assist features are used to modify the aerial image of the more isolated images on the mask. The effect that the diffraction of the scattering bars (SBs) has on the image intensity distribution is explained. Rules for determining the size and placement of SBs are also given.Resist is optimized for use with off-axis illumination and assist features. A general explanation of the material' s effect is discussed along with the affect on the through-pitch bias. The paper culminates with the showing of the lithographic results from the fully optimized system.     

Cost-effective test solutions for smart card and other integrated flash applications

From its emergence in the late 1980s as a lower cost alternative to early EEPROM technologies, flash memory has evolved to higher densities and speedsand rapidly growing acceptance in mobile applications.In the process, flash memory devices have placed increased test requirements on manufacturers. Today, as flash device test grows in importance in China, manufacturers face growing pressure for reduced cost-oftest, increased throughput and greater return on investment for test equipment. At the same time, the move to integrated flash packages for contactless smart card applications adds a significant further challenge to manufacturers seeking rapid, low-cost test.     

Theoretical analysis of the relationship between the Brillouin gain coefficient and the strain in the optical-fiber sensors

The relation between the power of the Brillouin signal and the strain is one of the bases of the distributed fiber sensors of temperature and strain. The coefficient of the Bfillouin gain can be changed by the temperature and the strain that will affect the power of the Brillouin scattering. The relation between the change of the Brillouin gain coefficient and the strain is thought to be linear by many researchers. However, it is not always linear based on the theoretical analysis and numerical simulation. Therefore, errors will be caused if the relation between the change of the Brillouin gain coefficient and the strain is regarded as to be linear approximately for measuring the temperature and the strain. For this reason, the influence of the parameters on the Brillouin gain coefficient is proposed through theoretical analysis and numerical simulation.     

An improved parallel thinning algorithm with two subiterations

The parallel thinning algorithm with two subiterations is improved in this paper. By analyzing the notions of connected components and passes, a conclusion is drawn that the number of passes and the number of eight-connected components are equal. Then the expression of the number of eight-connected components is obtained which replaces the old one in the algorithm. And a reserving condition is proposed by experiments, which alleviates the excess deletion where a diagonal line and a beeline intersect. The experimental results demonstrate that the thinned curve is almost located in the middle of the original curve connectivelv with single pixel width and the processing speed is high.     

Novel fiber-optical interferometer with miniaturized probe for in-hole measurements

Today, micro-system technology and the development of new MEMS （Micro-Electro-Mechanical Systems） are emerging rapidly. In order for this development to become a success in the long run, measurement systems have to ensure product quality. Most often, MEMS have to be tested by means of functionality or destructive tests. One reason for this is that there are no suitable systems or sensing probes available which can be used for the measurement of quasi inaccessible features like small holes or cavities. We present a measurement system that could be used for these kinds of measurements. The system combines a fiber optical, miniaturized sensing probe with low-coherence interferometry, so that absolute distance measurements with nanometer accuracy are possible.     

Development of the readout system for waveguide multilayer optical card

Waveguide multilayer optical card （WMOC） is a novel storage device of three-dimensional optical information. An advanced readout system fitting for the WMOC is introduced in this paper. The hardware mainly consists of the light source for reading, WMOC, motorized stages addressing unit, microscope imaging unit, CCD detecting unit and PC controlling ＆ processing unit. The movement of the precision motorized stage is controlled by the computer through Visual Basic （VB） language in software. A control panel is also designed to get the layer address and the page address through which the position of the motorized stages can be changed. The WMOC readout system is easy to manage and the readout result is directly displayed on computer monitor.     

Study of waveguide coupling efficiency in hybrid silicon lasers

This paper presents a new method to increase the waveguide coupling efficiency in hybrid silicon lasers. We find that the propagation constant of the InGaAsP emitting layer can be equal to that of the Si resonant layer through improving the design size of the InP waveguide. The coupling power achieves 42% of the total power in the hybrid lasers when the thickness of the bonding layer is 100 nm. Our result is very close to 50% of the total power reported by Intel when the thickness of the thin bonding layer is less than 5 nm. Therefore, our invariable coupling power technique is simpler than Intel＇s.     

Collinear phase-matching study of terahertz-wave generation via difference frequency mixed in GaAs and Inp

The collinearly phase-matching condition of terahertz-wave generation via difference frequency mixed in GaAs and InP is theoretically studied. In collinear phase-matching, the optimum phase-matching wave hands of these two crystals are calculated. The optimum phase-matching wave bands in GaAs and lnP are 0.95-1.38μm and 0.7-0.96μm respectively. The influence of the wavelength choice of the pump wave on the coherent length in THz-wave tuning is also discussed. The influence of the temperature alteration on the phase-matching and the temperature tuning properties in GaAs crystal are calculated and analyzed. It can serve for the following experiments as a theoretical evidence and a reference as well.     

Effects of the alloy compositions on the phonon-polaritons in ternary mixed crystals

Composition dependence of bulk and surface phonon-polaritons in ternary mixed crystals are studied in the framework of the modified random-element-isodisplacement model and the Bom-Huang approximation. The numerical results for Several Ⅱ - Ⅵ and Ⅲ- Ⅴ compound systems are performed, and the polariton frequencies as functions of the compositions for ternary mixed crystals AlxGa1-xAs, GaPxAS1-x, ZnSxSe1-x, GaAsxSb1-x, GaxIn1-xP, and ZnxCd1-xS as examples are given and discussed. The results show that the dependence of the energies of two branches of bulk phonon-polaritons which have phonon-like characteristics, and surface phonon-polaritons on the compositions of ternary mixed crystals are nonlinear and different from those of the corresponding binary systems.     

New insert layer structure OLEDs

An insert layer structure organic electroluminescent device（OLED） based on a new luminescent material （Zn（salen）） is fabricated. The configuration of the device is ITO/CuPc/NPD/Zn（salen）/Liq/LiF/A1/CuPc/NPD/Zn（salen）/Liq/LiF/A1. Effective insert electrode layers comprising LiF（1nm）/Al（5 nm） are used as a single semitransparent mirror, and bilayer cathode LiF（1 nm）/A1（100 nm） is used as a reflecting mirror. The two mirrors form a Fabry-Perot microcavity and two emissive units. The maximum brightness and luminous efficiency reach 674 cd/m^2 and 2.652 cd/A, respectively, which are 2.1 and 3.7 times higher than the conventional device, respectively. The superior brightness and luminous efficiency over conventional single-unit devices are attributed to microcavity effect.