A 77 GHz mHEMT MMIC Chip Set for Automotive Radar Systems

A monolithic microwave integrated circuit (MMIC) chip set consisting of a power amplifier, a driver amplifier, and a frequency doubler has been developed for automotive radar systems at 77 GHz. The chip set was fabricated using a 0.15 µm gate‐length InGaAs/InAlAs/GaAs metamorphic high electron mobility transistor (mHEMT) process based on a 4‐inch substrate. The power amplifier demonstrated a measured small signal gain of over 20 dB from 76 to 77 GHz with 15.5 dBm output power. The chip size is 2 mm × 2 mm. The driver amplifier exhibited a gain of 23 dB over a 76 to 77 GHz band with an output power of 13 dBm. The chip size is 2.1 mm × 2 mm. The frequency doubler achieved an output power of –6 dBm at 76.5 GHz with a conversion gain of ?16 dB for an input power of 10 dBm and a 38.25 GHz input frequency. The chip size is 1.2 mm × 1.2 mm. This MMIC chip set is suitable for the 77 GHz automotive radar systems and related applications in a W‐band.     

具有正斜率增益的GaAs MMIC宽带放大器芯片设计

介绍了一种宽带放大器芯片,该放大器的工作频率覆盖了2～12 GHz,采用砷化镓(GaAs)赝配高电子迁移率晶体管(PHEMT)单片电路工艺实现。在一个宽带负反馈放大器的前面集成了一个幅度均衡器,使放大器的增益在整个带内具有7 dB的正斜率,频率低端(2 GHz)增益为3 dB,高端(12 GHz)为10 dB,输入输出电压驻波比为1.6∶1,饱和输出功率为20 dBm,芯片尺寸为2.0 mm×1.5 mm×0.1 mm。详细描述了电路的设计流程,并对最终的测试结果进行了分析。该芯片具有频带宽、体积小、使用方便的特点,可作为增益块补偿微波系统中随着频率升高而产生的增益损失。     

A W-band InAs/AlSb low-noise/low-power amplifier

The first W-band antimonide based compound semiconductor low-noise amplifier has been demonstrated. The compact 1.4-mm/sup 2/ three-stage co-planar waveguide amplifier with 0.1-/spl mu/m InAs/AlSb high electron mobility transistor devices is fabricated on a 100-/spl mu/m GaAs substrate. Minimum noise-figure of 5.4dB with an associated gain of 11.1 dB is demonstrated at a total chip dissipation of 1.8 mW at 94 GHz. Biased for higher gain, 16/spl plusmn/1 dB is measured over a 77-103 GHz frequency band.     

A wideband LNA employing gate-inductive-peaking and noise-canceling techniques in 0.18μm CMOS

正This paper presents a wideband low noise amplifier(LNA) for multi-standard radio applications.The low noise characteristic is achieved by the noise-canceling technique while the bandwidth is enhanced by gateinductive -peaking technique.High-frequency noise performance is consequently improved by the flattened gain over the entire operating frequency band.Fabricated in 0.18μm CMOS process,the LNA achieves 2.5 GHz of -3 dB bandwidth and 16 dB of gain.The gain variation is within±0.8 dB from 300 MHz to 2.2 GHz.The measured noise figure(NF) and average HP3 are 3.4 dB and -2 dBm,respectively.The proposed LNA occupies 0.39 mm2 core chip area.Operating at 1.8 V,the LNA drains a current of 11.7 mA.     

A 6-9 GHz ultra-wideband CMOS PA for China's ultra-wideband standard

A 6-9 GHz ultra-wideband CMOS power amplifier(PA) for the high frequency band of China's UWB standard is proposed.Compared with the conventional band-pass filter wideband input matching methodology,the number of inductors is saved by the resistive feedback complementary amplifying topology presented.The output impendence matching network utilized is very simple but efficient at the cost of only one inductor.The measured S_(22) far exceeds that of similar work.The PA is designed and fabricated with TSMC 0...     

Development of multiband phase shifters in 180-nm RF CMOS technology with active loss compensation

We present the design and development of a novel integrated multiband phase shifter that has an embedded distributed amplifier for loss compensation in 0.18-/spl mu/m RF CMOS technology. The phase shifter achieves a measured 180/spl deg/ phase tuning range in a 2.4-GHz band and a measured 360/spl deg/ phase tuning range in both 3.5- and 5.8-GHz bands. The gain in the 2.4-GHz band varies from 0.14 to 6.6 dB during phase tuning. The insertion loss varies from -3.7 dB to 5.4-dB gain and -4.5 dB to 2.1-dB gain in the 3.5- and 5.8-GHz bands, respectively. The gain variation can be calibrated by adaptively tuning the bias condition of the embedded amplifier to yield a flat gain during phase tuning. The return loss is less than -10 dB at all conditions. The chip size is 1200 /spl mu/m/spl times/2300 /spl mu/m including pads.     

宽中频CMOS下变频器单片

该文介绍了一种工作于毫米波频段的宽中频(IF)下变频器.该下变频器基于无源双平衡的设计架构,片上集成了射频(RF)和本振(LO)巴伦.为了优化无源下变频器的增益、带宽和隔离度性能,电路设计中引入了栅极感性化技术.测试结果表明,该下变频器的中频带宽覆盖0.5～12?GHz.在频率为30?GHz、幅度为4?dBm的LO信号...     

Modeling and design for electrical performance of wideband flip-chip transition

A locally matching technique is proposed in this paper to improve the wideband performance of the flip-chip transition. The gap width of the coplanar waveguide (CPW) line in the bump pad region of both the chip and board is enlarged for achieving larger inductance to compensate the capacitance at the transition, making the approximate impedance close to 50 /spl Omega/. An equivalent circuit is derived from the frequency response of the transition simulated by Sonnet and is used to control the zero frequency of the structure. With a properly chosen value of the enlarged width, the zero frequency can be controlled to achieve an optimal transition performance over an as wide as possible bandwidth. A systematic design procedure is established and employed to design a transition over a band from dc to 60 GHz. The design and simulation results are also compared with the measured data of a scaled structure as well as a realization of an optimized flip-chip transition design ranging from dc to Ka band. The measured data show a good agreement with the simulation results, if under a careful calibration procedure. Both demonstrate that the present transition design can achieve better than 25 dB in return loss and 0.2 dB in insertion loss over dc to 35 GHz.     

采用内嵌了离散时间滤波器的射频直接采样混频器的CMOS宽带前端芯片

本文展示了一种新型的CMOS宽带射频前端芯片。它由低噪声跨到放大器（LNTA）和内嵌了可编程的离散时间滤波器的射频直接采样混频器（DSM）组成。第一级的LNTA具有0.5到6GHz的带宽,宽带输入匹配以及低噪声的特性。DSM之后的内嵌滤波器工作在离散时间电荷域,可以根据始终频率控制中频带宽,同时滤除混叠和干扰信号。测试结果显示,在0.5到6GHz的带宽内,噪声系数均低于7dB。在2.4GHz处,转换增益为12.6dB,IP1dB为-7.5dBm。该芯片所占面积为0.23mm2,消耗14mA直流电流。     

A Low-Power Wideband CMOS LNA for WiMAX

In this brief, the design of a low-power inductorless wideband low-noise amplifier (LNA) for worldwide interoperability for microwave access covering the frequency range from 0.1 to 3.8 GHz using 0.13-mum CMOS is described. The core consumes 1.9 mW from a 1.2-V supply. The chip performance achieves S₁₁ below -10 dB across the entire band and a minimum noise figure of 2.55 dB. The simulated third-order input intercept point is -2.7 dBm. The voltage gain reaches a peak of 11.2 dB in-band with an upper 3-dB frequency of 3.8 GHz, which can be extended to reach 6.2 GHz using shunt inductive peaking. A figure of merit is devised to compare the proposed designs to recently published wideband CMOS LNAs     

A single-chip image rejecting receiver for the 2.44 GHz band usingcommercial GaAs-MESFET-technology

A single-chip receiver for the 2.44 GHz band has been designed. To minimize the number of chip connections as well as external components, an image rejecting architecture has been chosen. A two-stage voltage controlled ring oscillator is used as a quadrature LO-source. The IF phase relationship is achieved with RC allpass circuits. Special attention is paid to keep the design insensitive to process variations. The 3-mm² chip has been fabricated with commercial 1-μm E/D GaAs MESFET technology and comprises an RF preamplifier, a voltage controlled ring oscillator, a phasing type image reject mixer, an IF preamplifier and a prescaler (division by 16). Except for the power supply and the frequency tuning voltage, no external components are required for basic operation. Prototype devices from two wafer runs were investigated. Power consumption from a single supply voltage of 5 V is 0.6 W. An image rejection of 34 dB is measured over a 130 to 280 MHz IF bandwidth. With a simple input symmetrizing and matching network, a conversion gain of 34 dB and a noise figure of 6.5 dB are achieved. The short term frequency instability of the free running ring oscillator is 400 kHz. With simple passive analog phase lock circuitry, an SSB phase noise of -74 dBc/Hz at 100 kHz offset is attained     

A 2-V, 1-10 GHz BiCMOS transceiver chip for multimode wirelesscommunications networks

This paper concerns the design consideration, fabrication process, and performance results for an ultra-broadband, low-voltage, low-power, BiCMOS-based transceiver chip for cellular-satellite-LAN wireless communication networks. The transceiver chip incorporates an RF amplifier, a Gilbert down-mixer, and an IF amplifier in the receive path, and an IF amplifier, a Gilbert up-mixer, and an RF amplifier in the transmit path. For an RF frequency in the 1-10 GHz band and an IF frequency in the 100-1000 MHz band, the developed transceiver chip consumes less than 60 mW at 2 V, to yield a downconversion gain of 40 dB at 1 GHz and 10 dB at 10 GHz and an upconversion gain of 42 dB at 1 GHz and 11 dB at 10 GHz. To avoid possible start-up problems caused during “stand-by” to “enable” mode transition, a simple switching technique is employed for enabling either the receive or the transmit path, by changing the value of a reference voltage applied to both the down- and the up-mixers. While the developed transceiver chip exhibits the best performance for a dc supply voltage of 2 V, it shows a graceful degradation for a ±0.15 V voltage deviation. The transceiver's chip size is 1.04 mm×1.04 mm     

（英）CMOS毫米波低功耗超宽带共栅低噪声放大器

本文陈述了一个基于单端共栅与共源共栅级联结构的超宽带低噪声放大器(LNA)。该LNA用标准90-nm RF CMOS工艺实现并具有如下特征：在28.5到39 GHz频段内测得的平坦增益大于10 dB;-3 dB带宽从27到42 GHz达到了15 GHz,这几乎覆盖了整个Ka带;最小噪声系数(NF)为4.2 dB,平均NF在27-42 GHz频段内为5.1 dB;S₁₁在整个测试频段内小于-11 dB。40 GHz处输入三阶交调点(IIP3)的测试值为 2 dBm。整个电路的直流功耗为5.3 mW。包括焊盘在内的芯片面积为0.58*0.48 mm2_。     

A monolithic three-stage 2-8-GHz feedback amplifier

A monolithic three-stage resistive-feedback amplifier has been developed for the 2-8-GHz band. This amplifier uses a novel approach which incorporates three stages with varying FET gate widths. The measured gain is 19 ± 1 dB and the VSWR is 2.3:1 in this band. The amplifier chip has a noise figure of ∼6 dB over the bandwidth. The chip size is less than 2.0 × 1.6 mm²and includes the bias circuitry. The amplifier also has AGC capability with more than 20 dB of gain control.     

3.4GHz频率的S波段SAW滤波器

该文研制了一款频率3.4 GHz的S波段声表面波(SAW)滤波器。该滤波器采用一种由新型谐振器构成的阻抗元结构,能提升抗热释电静电损伤能力,用时可在一定程度上提升器件的功率承受能力。同时研制了尺寸为2.0 mm×1.6 mm的芯片级封装(CSP)基板。采用倒装焊工艺实现了芯片与CSP基板的电连接,降低了电磁寄生影响。结果表明,研制的SAW滤波器频率为3.408 GHz,插损为2.23 dB,8 GHz远端阻带大于30 dB,且实测的功率承受能力达到30 dBm。     

A 3.3 mW K-Band 0.18-μ m 1P6M CMOS Active Bandpass Filter Using Complementary Current-Reuse Pair

This letter presents a low-power active bandpass filter (BPF) at K-band fabricated by the standard 0.18 mum 1P6M CMOS technology. The proposed filter is evolved from the conventional half-wavelength resonator filter, using the complementary-conducting-strip transmission line (CCS TL) as the half-wavelength resonator. Furthermore, the complementary MOS cross-couple pair is proposed as a form of current-reuse scheme for achieving low-power consumption and high Q-factor simultaneously. The simulated results indicate that the Q-factor of the proposed half-wavelength resonator can be boosted from 9 to 513 at 25.65 GHz compared with the resonator enhanced by the nMOS cross-couple pair to Q-factor of merely 43 under the same power consumption. The proposed active BPF of order two occupies the chip area of 360 mum times 360 mum without contact pads. The measured results show that the center frequency of the active BPF is 22.70 GHz and a bandwidth of 1.68 GHz (7.39 %). The measured P_{1 dB} and noise figure at 22.70 GHz are -7.65 dBm and 14.05 dB, respectively. There is a 56.84 dB suppression between the fundamental tone and the second harmonic when the input power is -11.26 dBm. While showing 0 dB loss and some residual gain, the active BPF consumes 2.0 mA at 1.65 V supply voltage with maximum of 0.15 dB insertion loss and 9.96 dB return loss at pass band.     

A 3.4-3.6 GHz power amplifier in an InGaP/GaAs HBT

This paper presents a 3.4-3.6 GHz power amplifier（PA） designed and implemented in InGaP/GaAs HBT technology.By optimizing the off-chip output matching network and designing an extra input-matching circuit on the PCB,several problems are resolved,such as resonant frequency point migration,worse matching and lower gain caused by parasitics inside and outside of the chip.Under V_cc = 4.3 V and V_bias = 3.3 V,a P_1dB of 27.1 dBm has been measured at 3.4 GHz with a PAE of 25.8%,the 2nd and 3rd harmonics are -64 dBc and -51 dBc,respectively. In addition,this PA shows a linear gain more than 28 dB with S₁₁<-12.4dB and S₂₂<-7.4 dB in 3.4-3.6 GHz band.     

A 3.4-3.6 GHz power amplifier in an InGaP/GaAs HBT

报道了基于InGaP/GaAs HBT工艺的3.4-3.6GHz功率放大器芯片的设计。针对片外和片内寄生因素引起的谐振点偏移、匹配变差、增益降低等问题,通过优化设计片外匹配电路以及设计输入匹配的片外调整电路,最终取得了较高的增益以及良好的匹配状态。电路测试结果为：在Vcc为4.3V以及Vbias=3.3V下,3.4GHz处的1dB压缩点输出功率达到27.1dBm以上,相应的PAE为25.8%,二次谐波和三次谐波抑制比分别达到了-64dBc和-51dBc。在3.4-3.6GHz频段内,增益大于28dB, S11<-12.4dB,S22<-7.4dB,达到了设计要求。     

2~26GHzGaAs单片功率放大器

报道了一个具有低噪声性能的2~26GHz GaAs超宽带单片功率放大器的研究结果,介绍了模型提取、电路设计和单片制作的全过程.放大器采用分布式设计,在超宽带频率范围内增益为6.5±0.5dB,输入输出驻波比小于2.0.在2~20GHz内测得输出功率大于300mW,噪声系数为3.5~5.5dB.单片放大器包括所有匹配、隔直及偏置电路,芯片面积为3.2mm×1.275mm×0.1mm.     

Crosstalk investigation of laser-diode pairs

The crosstalk between the lasers of different laser-diode pairs has been investigated experimentally in the frequency domain. The mutual crosstalk of two lasers diodes monolithically integrated on a single transmitter chip and separated by 100 μm was measured to be about -50 dB up to a modulation frequency of 100 MHz. At higher frequencies, it rises linearly with the frequency to -40 dB at 1 GHz. Measurements and calculations indicate that the origin of this crosstalk is the leakage current in the chip and inductive coupling of the bond wires. With these crosstalk values, digital data transmission at high bit rates is possible without significantly reducing the receiver sensitivity