Investigations of the influence of dicing techniques on the strength properties of thin silicon

Thin silicon offers a variety of new possibilities in microelectronical, solar and micromechanical industries, e.g. for 3D-integration (stacked dies), thin microelectromechanical packages or thin single crystalline solar cells. The wafers in this investigation were thinned back by grinding and subsequent spin etching steps for stress relief followed by separation into single test dies by sawing or etching. In order to characterize and optimize relevant process steps in terms of quality and fabrication yield, the mechanical properties were investigated considering the defect formation and strength. In this paper the influence of three different dicing technologies on the mechanical strength of thin silicon samples was investigated by 3-point bending tests. Sawing, Dicing-by-Thinning with sawn grooves and Dicing-by-Thinning with dry-etched trenches were used as dicing technologies. Analytical and numerical calculations were performed to calculate fracture stresses from fracture forces in 3-point bending tests taking into account the non-linear relationship of force and displacement during testing. Thus the fracture stress as a parameter of strength could be calculated for all tested samples. The results were statistically evaluated by the Weibull distribution based on the weakest link theory. This approach allows a more comprehensive understanding of the influence of the process on strength properties independently of geometric factors. Samples, being separated by “Dicing-by-Thinning”, have much higher strength than simply sawed samples. If trenches are fabricated by dry-etched process the strength can be increased tremendously.     

Fracture strength characterization and failure analysis of silicon dies

This paper characterizes fracture strength of a silicon die as a first step to predict and prevent die cracking during package assembly, reliability tests, and operation life. Die strength is measured via the three-point bend test conducted using a micro-force tester. Strength reduction due to surface defects, such as tiny notches or micro-cracks that are introduced through wafer backside grinding is evaluated. It is observed that die strength strongly depends on the grinding patterns, i.e. minimum die strength in a wafer is found if the grinding mark is in parallel with the loading axis. Furthermore, fracture strength of dies with different wafer surface conditions like polishing and no treatment (grinding) are also examined. Polished wafers possess the highest silicon strength owing to its minimum surface flaws. On the other hand, untreated wafers contain the most severe surface defects; hence exhibit the lowest die strength. Geometrical factors (square vs. rectangular) and die thickness (4 vs. 6 mils) are probed as well, however these factors do not contribute to die strength degradation. Surface morphology and roughness studies of silicon dies via scanning electron microscope and atomic force microscope also confirmed that die strength degradation is mainly controlled by surface defect (roughness) levels. Observed fracture modes also correlate well with measured die strength.     

Analytical stress characterization after different chip separation methods

Synchrotron white beam X-ray topography (SXRT) and photoelastic stress measurements were used to characterize resulting strain fields after mechanical dicing and laser grooving of bare silicon wafers. The distribution and propagation of the strain fields can be characterized by both methods. In contrast to mechanical dicing, the laser grooving process creates an inhomogeneous strain field. The influenced area is three times larger compared to mechanical dicing. The effect of the dicing procedure on the resulting mechanical fracture strength of the silicon chips was investigated by 3-point bending tests. The fracture strength of samples with an additional laser grooving process was significantly reduced under tensile load. The fracture pattern of the samples indicated that the strain field generated by the separation process causes initial points for μ-cracks propagation under mechanical load. This analysis can help to optimize dicing processes in order to attain a better reliability of chips with regard to process yields.     

Strength evaluation of silicon die for 3D chip stacking packages using ABF as dielectric and barrier layer in through-silicon via

The objective of this study is to evaluate the strength of silicon dies covered with a polymer film - Ajinomoto Build-up Film (ABF) - through the four-point bending (4PB) test and finite element method (FEM) analysis. With the evaluated strength, the possibility of die-cracking in 3D packages, wherein the thinned stacking dies are covered with ABF, under a thermal cycle condition is further investigated. In this study, a sandwich structure composed of an ABF layer as the intermediate layer between two (1 0 0) silicon substrates is applied in the 4PB test. Additionally, two kinds of bonding pressure are applied in the fabrication of 4PB specimens: 1 and 5 MPa. The force-displacement relation of the specimen is first measured by the 4PB test. On the other hand, the corresponding FEM model is simulated to obtain the relation of the first principal stress and the applied displacement. By comparing the experimental data and simulation results, the strength of the silicon substrate covered with ABF can be evaluated. Moreover, the FEM analysis results of a 10-layered die stacking 3D package show that the stress distribution in each stacking die does not exceed the evaluated strength. In summary, this paper demonstrates that the strength of the silicon substrate covered with soft and elastic material, such as ABF, as dielectric and barrier layer in 3D die stacking packages can be enhanced.     

On the mechanical strength of monocrystalline,multicrystalline and quasi‐monocrystalline silicon wafers: a four‐line bending test study

Quasi‐monocrystalline silicon wafers have appeared as a critical innovation in the PV industry, joining the most favorable characteristics of the conventional substrates: the higher solar cell efficiencies of monocrystalline Czochralski‐Si (Cz‐Si) wafers and the lower cost and the full square‐shape of the multicrystalline ones. However, the quasi‐monocrystalline ingot growth can lead to a different defect structure than the typical Cz‐Si process. Thus, the properties of the brand new quasi‐monocrystalline wafers, based on low and high crystal defect densities, have been for the first time studied from a mechanical point of view, comparing their strength with that of both Cz‐Si monocrystalline and typical multicrystalline materials. The study has been carried out employing the four line bending test and simulating them by means of FE models. For the analysis, failure stresses were fitted to a three‐parameter Weibull distribution. High mechanical strength was found in all the cases. However, the quasi‐monocrystalline wafers characterized by large density of bulk defects, due to the noticeable density of extended defects, showed lower fracture tensions. Copyright © 2013 John Wiley & Sons, Ltd.     

A three-parameter Weibull-like fitting function for flip-chip die strength data

Die cracking in the assembly and reliability testing of flip-chip (FC) packages is often a major concern. A widely used die strength test is the so-called the four-point bending (4PB) test. In the 4PB test, the die is under pure bending and the strength of the die is determined by its breaking tensile stress. Although the 4PB test has been widely used, a well-established relation between the 4PB result and the die breaking in FC package has not been reported. This paper discusses the relation from a probabilistic mechanics point of view. The theory considers the following issues in the material strength test and the application loading conditions: (1) the die top in the 4PB test is under uniaxial tensile stress and the die in FC package is under multi-axial stress; (2) the 4PB test only puts part of the die top under tension and the die top in FC plastic package has almost 100% of the die top area under tension; (3) the die stress in the 4PB and in the package has a different distributions which contribute differently to die cracking. Weibull distribution will be used to analysis the 4PB test data. A three-parameter Weibull distribution fitting procedure will be presented. The function form of the cumulative density function of Weibull distribution is specially modified to take the above three issues into consideration and reflect the stress distribution difference between the test and application. The three-parameter Weibull fitting is compared to a two-parameter fitting. It turns out that some systems need three-parameter fitting and some other systems only need the two-parameter fitting. For systems need three-parameter fitting, a two-parameter fitting will be too conservative in design.     

300-mm Low-${hbox {k}}$ Wafer Dicing Saw Development

With the further shrinking of IC dimensions, low- material has been widely used to replace the traditional SiO interlayer dielectric (ILD) in order to reduce the interconnect delay. The introduction of low- material into silicon imposed challenges on dicing saw process. ILD and metal layers peeling and its penetration into the sealing ring of the die during dicing saw are the most common defects. In this paper, the low- material structure and its impact on wafer dicing were elaborated. A practical dicing quality inspection matrix was developed to assess the cutting process variation. A 300-mm CMOS90-nm dual damascene low- wafer was chosen as a test vehicle to develop a robust low- dicing saw process. The critical factors (dicing blade, index speed, spindle speed, cut in depth, test pattern in the saw street, etc.) affecting cutting quality were studied and optimized. The selected C90 Dual damascene low- device passed package reliability tests with the optimized low- dicing saw recipe and process. The further improvement and solutions in eliminating the low- dicing saw peeling were also explored.     

Application of Two Hopfield Neural Networks for Automatic Four-Element LED Inspection

A system for the automatic inspection of LED wafer defects is proposed to detect defective dies in a four-element (aluminum gallium indium phosphide, AlGaInP) wafer. There are over 80000 dies on an LED wafer. Defective dies are typically visually identified with the aid of a scanning electron microscope. This process involves dozens of operators or engineers visually checking the wafers and hand marking the defective dies. However, wafers may not be fully and thoughtfully checked, and different observers usually find different results. These shortcomings lead to significant labor and production costs. Therefore, a solution that consists of two Hopfield neural networks, of which one is used to identify the LED die regions and the other is used to cluster the die into three groups, is proposed to facilitate the detection of defective dies in wafer images. The experimental results show that the proposed method successfully detects defective dies in a four-element wafer.     

底充胶固化工艺对低k倒装焊器件可靠性的影响

利用四点弯曲实验测试了一组芯片(30片)的强度,使用威布尔统计模型描述了芯片失效率的分布,预测了在后续热循环过程中芯片的失效概率。通过有限元软件研究了底充胶固化工艺对芯片上方垂直开裂应力、焊点等效塑性应变及低k层最大等效应力的影响。结果表明:与未经固化的相比,底充胶固化工艺使得芯片的失效率从0.08%增大到0.37%,焊点的等效塑性应变增大约7倍,低k层的最大等效应力增大约18%。     

Investigations of strength of copper-bonded wafers with several quantitative and qualitative tests

The strengths of Cu-bonded wafers with respect to different bonding temperatures and bonding durations by quantitative and qualitative approaches were reviewed and investigated. These investigations include the mechanical dicing test, the tape test, the pull test, and the push test. For all test results, the strength of Cu-bonded wafers increases with increases in bonding duration or bonding temperature. Thermal anneal after bonding improved the bonding strength only at the high bonding temperature and not at the low temperature.     

WL-CSP reliability with various solder alloys and die thicknesses

WL-CSP is a low profile, true chip size package that is entirely built on a wafer using front-end and back-end processing. A new wafer level chip-scale package (WL-CSP) technology has been evaluated using a test vehicle, which has a 0.5 mm pitch of an 8 × 8 array of bumps on a 5 × 5 mm² die. The bump structure and package geometry have been optimized using simulation and validated by experimentation. The board used for reliability testing is a 1.2 mm thick, 2-layer FR-4 board with non-soldermask defined landpads with OSP (organic solderability preservative). The landpads are the same diameter as the 250 μm redistribution dielectric via size. Reliability data will be presented for three solder alloys and two wafer thicknesses. The first evaluation compares the reliability of solder alloys SnPbAg and two Pb-free alternatives: SnAgCu and SnCu. The second evaluation evaluates the potential reliability improvement of WL-CSPs by thinning the wafers. Standard thickness WL-CSP wafers are 27-mils. Wafers were thinned down to 4-mils thickness using two techniques. The first method is standard wafer backgrinding. The second is plasma etching, which results in a damage-free surface and improves wafer and die strength.     

芯片强度改进--减薄前划片+等离子包蚀刻

对于目前的多层芯片封装和IC卡, 不仅在组装工艺的提高良品率中要求芯片强度高, 而且在封装之后还要求有更好的使用期限。根据更薄晶圆的要求, 引入了消除晶圆减薄引起损伤的各种应力解除方法, 但在应力解除之后的划片中又引起了机械损伤, 通过这些方法不可能使芯片强度达到最大。因此, 我们开发了一种结合减薄前划片(DBG)的等离子蚀刻的应力解除方法。减薄前已完成划片工序的晶圆可在其底面和划切面同时用氟基蚀刻, 从而消除机械损伤。我们已能够通过比较经历过常规应力解除芯片来确认被改进芯片强度的平均、最小、最大值。可以预期这项技术将被用于提高今后将进一步扩展的IC卡(即信用卡, 身份证)的寿命要求。     

Evaluation of test methods for silicon die strength

The objective of this study is to evaluate the existing test methods of die strength, including widely-accepted three-point and four-point bending tests, and a newly-proposed point-load test by testing silicon die specimens with different surface conditions. It has been reported that there are three factors to influence die strength: the surface conditions of the die (including grinding-mark direction and surface roughness), the edge crack of the die (so-called chipping created during the cutting process), and the weak planes of the crystal lattice of silicon on (1, 1, 0) and (1, −1, 0). In this study, the focus will be on how these factors affect the strength data from these three test methods. Apart from performing these three tests, the roughness of the die surfaces (including the ground, polished and untreated surfaces) measured by atomic force microscopy, and edge chipping conditions by optical microscopy were correlated with strength data obtained from the tests. It was found that the four-point bending test gives the lowest strength data and its independence on the surface condition, due to much domination by the edge chipping. On the other hand, the three-point bending test provides intermediately high strength data, with slight difference between different surface conditions, and some major control by the edge chipping. It was also observed that both bending tests suffer the effect of the grinding-mark direction. By contrast, the point-load test associated with the applied force-maximum stress equation which is proved to be valid for Hertzian contact and, sometimes, required to take into account geometrically nonlinear effect, gives the highest values of strength among these methods. This test not only provides the data which are merely dependent on the surface roughness and free from the edge chipping and grinding-mark direction effects, but also it gives a bi-stress field similar to the temperature loading and provides direct test for dummy or real IC chips. As a result, the point-load test is one of the most adequate test methods for determining the die strength exclusively due to surface roughness effect.     

Contact resistance and adhesion performance of ACF interconnections to aluminum metallization

Flip chip joining technology using anisotropically conductive films (ACFs) has become an attractive technique for electronic packaging. However, several factors have hindered the wide spread use of this technology. Along with the reliability issue, these factors also include the low availability and high cost of the bumped wafers. This paper introduces the feasibilities of using unbumped die with respect to ACF joints for flip-chip-on-flex (FCOF) assemblies. The unbumped dies contain only bare aluminum pads. Untill now the performance of ACF to Al metallization is a controversial issue from the published reports. In this study, two different test vehicles were used to study contact resistance and adhesion performance. Reliability of contact resistance for ACF joints with the unbumped dies was investigated in terms of varying the thickness of the Al pads. Adhesion performance of ACF to the Al metallization was compared with the adhesion performance of ACF to a glass substrate using the same ACF and the same bonding parameters.FCOF assemblies containing dies with thinner aluminum pads showed lower initial contact resistance and a lower rate of increment during accelerated aging tests. Three factors were considered as the potential causes for the above results: (1) lower concentration of aluminum oxide on the thin Al pad, (2) larger contact area per deformed particle with Au/Ni/Cu electrode for the interconnection of thin Al pad and (3) lower concentration of the defects in the thin Al pad. Contact resistance was found to increase during accelerated testing because of aluminum oxide formation on top of the pads.Contrary to the usual expectation, adhesion strength of ACF with the Al metallization was increased during 60 °C/95% RH testing. After 500 h of such moisture-soak testing, the adhesion strength becomes 3 times the initial value. The change in chemical state on the aluminum surface is considered to be responsible for higher adhesion strength. It is proposed that oxidation of Al surface due to diffused moisture and the new chemical bond formation at the adhesives/aluminum interface are the key reasons for good adhesion reliability.     

Hemisphere-shaped silicon crystal wafers obtained by plastic deformation and preparation of their solar cells

Hemisphere-shaped crystal wafers can be prepared by the plastic deformation of Si crystal wafers. To obtain hemispherical Si wafers, graphite convex and concave dies were used. A Si wafer was set between dies and pressed at high temperatures. The Si wafer was pressed by an overweight of 200 N at various temperatures. The deformation regions in which well-shaped (100) and (111) wafers can be obtained by plastic deformation were determined using parameters of thickness and temperature. In order to demonstrate that the shaped wafers are of sufficiently high quality to be used in the preparation of devices, solar cells were fabricated using the hemispherical Si wafers pressed at 1,120°C and 1,200°C. The conversion efficiency of the hemispherical solar cells is 8.5–11.5%. It was clarified from the conversion efficiency of solar cells that the quality of the shaped crystal wafers can be improved by a proper annealing process. Thus, the hemispherical shaped wafers are of high quality to be used in the preparation of devices.     

Study on the effects of wafer thinning and dicing on chip strength

Die cracking is an annoying problem in the packaging industry. In this paper, we identified the weak regions, in terms of mechanical strength, in chips in a semiconductor wafer using the three-point bending test. The weak regions were observed in two sectors approximately 45/spl deg/ wide, axisymmetric to the wafer center. The strength of the chips within these weak regions was about 30%-35% lower than the average chip strength of the whole wafer. The existence of these weak regions was related to spiral grinding marks, which, in turn, were formed by backside mechanical grinding. The probability distributions of the chip strength and the chip fragmentary pattern confirmed this relationship. When wafers were mechanically ground until they were 50-/spl mu/m thick, chip warpage was found to be oriented to the direction of the grinding marks. Meanwhile, by slowing the mechanical grinding speed by 50%, we were able to increase the average chip strength by 56%. Either plasma etching or polishing after mechanical grinding eliminated the weak regions, and the optimal amount of mechanical grinding and the polishing depths were observed, beyond which the chip strength would not increase. On the other hand, a preprocess for blunting a new saw blade for chip dicing was found to be essential as the chip strength increased five-fold, whereas increasing the dicing speed or using dual saw instead of a single saw had only small effects on the chip strength degradation.     

Fine grain thermal modeling and experimental validation of 3D-ICs

3D die stacking is a promising technique to allow miniaturization and performance enhancement of electronic systems. Key technologies for realizing 3D interconnect schemes are the realization of vertical connections, either through the Si die or through the multilayer interconnections. The complexity of these structures combined with reduced thermal spreading in the thinned dies complicate the thermal analysis of a stacked die structure. In this paper a methodology is presented to perform a detailed thermal analysis of stacked die packages including the complete back end of line structure (BEOL), interconnection between the dies and the complete electrical design layout of all the stacked dies. The calculations are performed by 3D numerical techniques and the approach allows importing the full electrical design of all the dies in the stack. The methodology is demonstrated on a 2 stacked die structure in a BGA package. For this case the influence of through-Si vias (TSVs) on the temperature distribution is studied. The modeling results are experimentally validated with a dedicated test vehicle. A thermal test chip with integrated heaters and diodes as thermals sensors is used to successfully validate the detailed temperature profile of the hot spots in the top die of the die stack.     

Room-temperature microfluidics packaging using sequential plasma activation process

A sequential plasma activation process consisting of oxygen reactive ion etching (RIE) plasma and nitrogen radical plasma was applied for microfluidics packaging at room temperature. Si/glass and glass/glass wafers were activated by the oxygen RIE plasma followed by nitrogen microwave radicals. Then, the activated wafers were brought into contact in atmospheric pressure air with hand-applied pressure where they remained for 24 h. The wafers were bonded throughout the entire area and the bonding strength of the interface was as strong as the parents bulk wafers without any post-annealing process or wet chemical cleaning steps. Bonding strength considerably increased with the nitrogen radical treatment after oxygen RIE activation prior to bonding. Chemical reliability tests showed that the bonded interfaces of Si/Si could significantly withstand exposure to various microfluidics chemicals. Si/glass and glass/glass cavities formed by the sequential plasma activation process indicated hermetic sealing behavior. SiO/sub x/N/sub y/ was observed in the sequentially plasma-treated glass wafer, and it is attributed to binding of nitrogen with Si and oxygen and the implantation of N/sub 2/ radical in the wafer. High bonding strength observed is attributed to a diffusion of absorbing water onto the wafer surfaces and a reaction between silicon oxynitride layers on the mating wafers. T-shape microfluidic channels were fabricated on glass wafers by bulk micromachining and the sequential plasma-activated bonding process at room temperature.     

IC卡中薄芯片碎裂失效机理的研究

薄/超薄芯片的碎裂占据IC卡早期失效的一半以上,其失效模式、失效机理亟待深入研究.本文分析了芯片碎裂的失效模式和机理,并结合实际IC卡制造工艺以及IC卡失效分析实例,就硅片减薄、划片、顶针及卡片成型工艺对薄IC芯片碎裂的影响进行深入探讨.