200-MHz superscalar RISC microprocessor

Design and implementation details of the MIPS R10000, 200-MHz, 64-b superscalar dynamic issue RISC microprocessor is presented. It fetches and decodes four instructions per cycle and dynamically issues them to five fully pipelined, low latency execution units, Its hierarchical nonblocking memory system helps hide memory latency with two levels of set-associative, write-back caches. The processor has over 6.8 M transistors and is built in 3.3-V, 0.30 μm, four-layer metal CMOS technology with under 30 W of power consumption. The processor delivers peak performance of Spec95int of 9 and Spec95fp of 19 operating at 200 MHz. Clock and power distribution as well as circuit design techniques of several blocks are addressed     

A 120-MHz BiCMOS superscalar RISC processor

A superscalar RISC processor contains 2.8 million transistors in a die size of 16.2 mm×16.5 mm, and utilizes 3.3 V/0.5 μm BiCMOS technology. In order to take advantage of superscalar performance without incurring penalties from a slower clock or a longer pipeline, a tag bit is implemented in the instruction cache to indicate dependency between two instructions. A performance gain of up to 37% is obtained with only a 3.5% area overhead from our superscalar design     

3.3-V BiCMOS circuit techniques for a 120-MHz RISC microprocessor

This paper describes 3.3-V BiCMOS circuit techniques for a 120-MHz RISC microprocessor. The processor is implemented in a 0.5-μm BiCMOS technology with 4-metal-layer structure. The chip includes a 240 MFLOPS fully pipelined 64-b floating point datapath, a 240-MIPS integer datapath, and 24 KB cache, and contains 2.8 million transistors. The processor executes up to four operations at 120 MHz and dissipates 17 W. Novel BiCMOS circuits, such as a 0.6-ns single-ended common base sense amplifier, a 0.46-ns 22-b comparator, and a 0.7-ns path logic adder are applied to the processor. The processor with the proposed BiCMOS circuits has a 11%-47% shorter delay time advantage over a CMOS microprocessor     

A 2.2 W, 80 MHz superscalar RISC microprocessor

A 28 mW/MHz at 80 MHz structured-custom RISC microprocessor design is described. This 32-b implementation of the PowerPC architecture is fabricated in a 3.3 V, 0.5 μm, 4-level metal CMOS technology, resulting in 1.6 million transistors in a 7.4 mm by 11.5 mm chip size. Dual 8-kilobyte instruction and data caches coupled to a high performance 32/64-b system bus and separate execution units (float, integer, loadstore, and system units) result in peak instruction rates of three instructions per clock cycle. Low-power design techniques are used throughout the entire design, including dynamically powered down execution units. Typical power dissipation is kept under 2.2 W at 80 MHz. Three distinct levels of software-programmable, static, low-power operation-for system power management are offered, resulting in standby power dissipation from 2 mW to 350 mW. CPU to bus clock ratios of 1×, 2×, 3×, and 4× are implemented to allow control of system power while maintaining processor performance. As a result, workstation level performance is packed into a low-power, low-cost design ideal for notebooks and desktop computers     

A 150 MHz 0.6 μm BiCMOS superscalar microprocessor

An implementation of the Pentium microprocessor architecture in 0.6 μm BiCMOS technology is described. Power dissipation is reduced and performance is enhanced over the previous generation. Processor features, implementation technology, and circuit techniques are discussed. An internal clock rate of 150 MHz is achieved at 3.7 V and -55°C     

A 433-MHz 64-b quad-issue RISC microprocessor

A quad-issue custom VLSI microprocessor is described. This microprocessor implements the Alpha architecture and achieves an estimated performance of 13.3 SPECint9S and 18.4 SPECfp95 at 433 MHz. The 9.6 million transistor die measures 14.4 mm×14.5 mm, and is fabricated in a 0.35-μm, four-metal layer CMOS process. This chip dissipates less than 25 W at 433 MHz using a 2.0 V internal power supply. The design was leveraged from a prior 300-MHz, 3.3-V, 0.50-μm CMOS design. It includes several significant architectural enhancements and required circuit solutions for operation at 2.0 V. The chip will operate at nominal internal power supply voltages up to 2.5 V allowing improved performance at the cost of increased power consumption. At 2.5 V, the chip operates at 500 MHz and delivers 15.4 SPECint95 (est) and 21.1 SPECfp95 (est). This paper describes the chip implementation details and the strategy for efficiently migrating the existing design to the 0.35-μm technology     

A 300-MHz 64-b quad-issue CMOS RISC microprocessor

This 300 MHz quad-issue custom VLSI implementation of the Alpha architecture delivers 1200 MIPS (peak), 600 MFLOPS (peak), 341 SPECint92, and 512 SPECfp92. The 16.5 mm×18.1 mm die contains 9.3 M transistors and dissipates 50 W at 300 MHz. It is fabricated in a 3.3 V, four-layer metal, 0.5 μm, CMOS process. The upper metal layers (metal-3 and metal-4), primarily used for power, ground, and clock distribution. The chip supports 3.3 V/5.0 V interfaces and is packaged in a 499-pin ceramic IPGA. It contains an 8-kbyte instruction cache; an 8-kbyte, dual-ported, data cache; and a 96-kbyte, unified, second-level, 3-way set associative, fully pipelined, writeback cache. This paper describes the circuit and implementation techniques that were used to attain the 300 MHz operating frequency     

Multimedia extensions for a 550-MHz RISC microprocessor

This paper describes circuits used to implement the motion video instructions (MVI) in the 550-MHz Alpha 21 164PC Microprocessor. The chip is fabricated in a 0.35-μm CMOS process and is the first implementation of the MVI instruction set in the Alpha architecture. The MVI instruction set, coupled with the high performance of the 550-MHz processor, delivers 30 frames/s digital video disk (DVD) playback with stereo-quality audio, enables video teleconferencing at 30 frames/s, and significantly improves the performance of MPEG encode algorithms     

A 450-MHz RISC microprocessor with enhanced instruction set andcopper interconnect

This superscalar microprocessor is the first implementation of a 32-bit RISC architecture specification incorporating a single-instruction, multiple-data vector processing engine. Two instructions per cycle plus a branch can be dispatched to two of seven execution units in this microarchitecture designed for high execution performance, high memory bandwidth, and low power for desktop, embedded, and multiprocessing systems. The processor features an enhanced memory subsystem, 128-bit internal data buses for improved bandwidth, and 32-KB eight-way instruction/data caches. The integrated L2 tag and cache controller with a dedicated L2 bus interface supports L2 cache sizes of 512 KB, 1 MB, or 2 MB with two-way set associativity. At 450 MHz, and with a 2-MB L2 cache, this processor is estimated to have a floating-point and integer performance metric of 20 while dissipating only 7 W at 1.8 V. The 10.5 million transistor, 83-mm² die is fabricated in a 1.8-V, 0.20-μm CMOS process with six layers of copper interconnect     

A 160-MHz, 32-b, 0.5-W CMOS RISC microprocessor

This paper describes a 160 MHz 500 mW 32 b StrongARM(R) microprocessor designed for low-power, low-cost applications. The chip implements the ARM(R) V4 instruction set and is bus compatible with earlier implementations. The pin interface runs at 3.3 V but the internal power supplies can vary from 1.5 to 2.2 V, providing various options to balance performance and power dissipation. At 160 MHz internal clock speed with a nominal Vdd of 1.65 V, it delivers 185 Dhrystone 2.1 MIPS while dissipating less than 450 mW. The range of operating points runs from 100 MHz at 1.65 V dissipating less than 300 mW to 200 MHz at 2.0 V for less than 900 mW. An on-chip PLL provides the internal clock based on a 3.68 MHz clock input. The chip contains 2.5 million transistors, 90% of which are in the two 16 kB caches. It is fabricated in a 0.35-μm three-metal CMOS process with 0.35 V thresholds and 0.25 μm effective channel lengths. The chip measures 7.8 mm×6.4 mm and is packaged in a 144-pin plastic thin quad flat pack (TQFP) package     

3.3-V BiCMOS circuit techniques for 250-MHz RISC arithmetic modules

A quasi-complementary BiCMOS gate for low-voltage supply is applied to a 3.3V RISC data path. For a parallel RISC processor, the major issues are the construction of arithmetic modules in a small number of transistors and the shortening of the cycle time as well as the delay time. The feedbacked massive-input logic (FML) concept is proposed to meet these requirements. It reduces the number of transistors and the power within the framework of fully static logic 3-4 times. A low-voltage BiCMOS D-flip-flop is also conceived to allow the single-phase clocking scheme, which is favorable for high-frequency operation of RISCs. To demonstrate these circuit techniques, a 32-b ALU is designed and fabricated using 0.3-μm BiCMOS to demonstrate 1.6 times performance leverage over CMOS at 3.3 V     

A 70-MHz 32-b microprocessor with 1.0-μm BiCMOS macrocelllibrary

A custom 529 K-transistor microprocessor with a five-stage pipeline has been implemented on a 12.98-mm² die. Employing BiCMOS macrocells, a 32-b execution unit, extensible ROM, RAM, a PLL (phase-locked loop) clock generator with bipolar drivers, and sense circuits, and a peak performance of 70 MIPS (million instructions per second) are achieved. Power consumption is 2.1 W at 40 MHz     

A 600-MHz superscalar floating-point processor

The floating-point unit of a 600-MHz, out-of order, superscalar RISC Alpha microprocessor is described. The unit achieves 59 SpecFP95 and can transfer register data at up to 9.6 GB/s. It has two independent pipelines for multiply and add/subtract operations, with iterative divide and square-root circuits, and is fabricated in a 2.2-V, 0.35-μm CMOS process     

A 100-MHz macropipelined VAX microprocessor

A macropipelined CISC microprocessor was implemented in a 0.75-μm CMOS 3.3-V technology. The 1.3-million-transistor custom chip measures 1.62×1.46 cm² and dissipates 16.3 W. The 100-MHz parts were benchmarked at 50 SPEC marks. The on-chip clocking system and several high-performance logic and circuit techniques are described. Macroinstruction handling, micropipeline management, and control store structures highlight the design architecture. The hierarchical array organization and fast tag comparison technique of the primary cache are discussed. Power estimation procedures are outlined, and the results are compared to measurements. Physical design and verification methods, and CAD tools are also described. After extensive functional verification efforts are described, chip and system test results are presented     

A BiCMOS low-distortion 8-MHz low-pass filter

An 8-MHz seventh-degree elliptic-function low-pass filter is described, demonstrating an approach to low-distortion antialias filtering for high-definition video applications. The filter's performance goals are achieved through the use of circuit design principles that capitalize on the strengths of BiCMOS technology. The integrator circuits composing the filter consist of a new wideband low-distortion transconductor circuit and a unique BiCMOS Miller-stage circuit. Integrator time constants are determined by stable RC products, enabling a simplified filter calibration scheme that is insensitive to temperature-induced variations and requires no phaselock circuits. The prototype filter IC, consisting of seven integrators assembled in an active-ladder configuration, was fabricated in a 10-V, 2-μm 2.5-GHz BiCMOS technology that also features thin-film resistors and polysilicon-plate capacitors. Measured results from the calibrated filter show passband flatness of 0.2 dB, with aberrations of less than ±1 dB over a 100°C temperature range. Stopband attenuation meets its designed goal of 60 dB. Driven by 7-V_pp, differential input signals, the filter exhibits less than -72-dBc third-order intermodulation distortion products at 1 MHz. For 5-V_pp inputs at 4 MHz, third-order intermodulation spurs remain below -65 dBc     

A 300-MHz BiCMOS serial data transceiver

A BiCMOS circuit for serial data communication is presented. The chip has phase-locked loops for transmit frequency synthesis and receive clock recovery, serial-to-parallel and parallel-to-serial converters, and encode and decode functions. Since this is a mixed-analog/digital design, and the transmitter and receiver operate asynchronously, many techniques are used to decrease noise coupling. A 1.2 μm BiCMOS process allows operation at speeds of 300 MHz along with this high level of system integration, and the chip consumes less than 1 W from a single 5 V supply     

A 76-MHz BiCMOS programmable logic sequencer

A BiCMOS programmable logic sequencer with a maximum operating frequency of 76 MHz at a power dissipation of 370 mW has been developed. The device is organized as 16 inputs, 48 product terms, and eight registered outputs. The excellent speed power performance and TTL/CMOS compatibility were realized by an optimized circuit design coupled with an advanced BiCMOS process. The process features 13-GHz bipolar transistors, 1- mu m CMOS, TiW fuses, poly resistors, three-layer metal, and single-layer polycide. Bipolar devices are used in areas that utilize their strengths such as high current drivers, small-signal sensing, and precise current sources. CMOS is used in other areas to conserve layout size and power.<>     

A 64-b quad-issue CMOS RISC microprocessor

The HP-PA8000 is a 180-MHz quad-issue custom VLSI implementation of the HP-PA 2.0 64-b architecture delivering 11.84 SPECint95 and 20.18 SPECfp95 with 3.8 million transistors integrated on a 17.68 mm×19.1 mm die in a 3.3-V, 0.5-μm CMOS process. Specialized clock circuits and extensive use of dynamic logic are key factors in this microprocessor's performance. Attention to clock analysis and distribution resulted in a 170 ps clock skew between any two clock nodes. This microprocessor utilizes a 56-entry instruction reorder buffer (IRE), register renaming, and dual functional units to fully exploit instruction level parallelism     

A 480-MHz RISC microprocessor in a 0.12-μm Leff CMOStechnology with copper interconnects

This paper describes the performance improvements of a reduced instruction set computer (RISC) microprocessor that has migrated from a 2.5 V technology to a 1.8 V technology. The 1.8 V technology implements copper interconnects and low V_t field-effect transistors in speed-critical paths and has an L_eff of 0.12 μm. Global clock latency and skew are improved by using copper wires, and early mode timings are improved by reducing clock skew and adding buffers. These enhancements, along with an environment of 2.0 V, 85°C, and with a fast process, produced a 480-MHz RISC microprocessor     

40-MHz CMOS-on-sapphire microprocessor

Silicon-on-sapphire (SOS) technology has been applied to the RCA COSMAC microprocessor to obtain a high-speed single-chip CPU. The chip has 4827 transistors and measures 5.3 mm square. The low device count is obtained through use of bit-serial arithmetic logic, a byte-serial incrementer, and a 5-transistor static storage cell. The low parasitic capacitance of the SOS structure permits a 40-MHz clock rate at 14 V.