一种适用于5G通信的分布式低噪声放大器

宽带低噪声放大器是5G无线通信系统中的关键模块。针对6 GHz以下5G通信应用频段,基于65 nm CMOS工艺,设计了一种三级均匀分布式宽带低噪声放大器。在增益单元电路中,采用噪声抵消技术降低了噪声,同时实现了信号的单转双变换,并通过电流复用技术提升了增益。栅极人工传输线的终端采用了RL型负载,进一步改善了放大器的噪声性能。仿真结果表明,该分布式低噪声放大器的带宽为0.5~5.7 GHz,带内增益达到24.2 dB,噪声系数低于4.5 dB,而最小噪声系数仅为2.7 dB。     

A 24-GHz Patch Array with a Power Amplifier/Low-Noise Amplifier MMIC

This paper presents an active patch array designed at 24 GHz. It can be used as a front-end component for a phased array. A series resonant array structure is chosen which is compact and easy excite. With 5 elements, the array proved a 12-dB antenna gain. A power amplifier and a low noise amplifier are designed on a single GaAs chip (PALNA). Bias switch is used in the PALNA, which greatly reduces the switch loss in a transceiver and increases the efficiency. 20-dB small signal gain is achieved in both power amplifier and low noise amplifier. The active patch array is built by the combination of the patch array and PALNA. The measured active gain of this antenna is 35-dB for the PA mode and 31-dB for the LNA mode. This active patch array can obtain an EIRP of 34 dBm with a total radiated power of 22dBm and a maximum PAE of 32%. To check the noise performance, we applied sources at both normal temperature and 77K (liquid nitrogen) and extracted the noise figure (3.5 dB) of the active antenna by the Y factor method. The results proved that the active antenna is working efficiently as both a transmitting and receiving antenna.     

超低功耗Q波段低噪声放大器芯片的设计和实现

采用GaAs赝配HEMT单片微波集成电路(MMIC)工艺和堆栈偏置技术设计实现了一款Q波段低噪声放大器(LNA)芯片.该放大器采用4级级联的堆栈偏置拓扑结构,前两级电路在确保较低输入回波损耗的同时优化了放大器的噪声系数,后两级电路则采用最大增益的匹配方式,确保放大器具有良好的增益平坦度和较小的输出回波损耗.该LNA芯片最终尺寸为3 250 μm×1 500 μm,实测结果表明在40～46 GHz工作频率内放大器工作稳定,小信号增益大于23 dB,噪声系数小于3.0 dB,在4.5V工作电压下消耗电流约6 mA.此外,在片实测结果和设计结果符合良好.     

宽频带低噪声放大器设计

采用Lange耦合器的宽频带特性设计L／S波段平衡式低噪声放大器电路,并通过仿真设计软件对放大器的工作频带、噪声系数、增益及输入、输出驻波比等几个重要指标进行优化。最后设计的放大器在1．2～2．5GHz频率范围内增益为33～35dB,噪声系数不大于1dB,输入输出驻波比小于1．5,达到了预定的技术指标要求,性能良好。     

（英）D波段InP基高增益、低噪声放大芯片的设计与实现

利用90-nm InAlAs/InGaAs/InP HEMT工艺设计实现了两款D波段（110~170 GHz）单片微波集成电路放大器。两款放大器均采用共源结构,布线选取微带线。基于器件A设计的三级放大器A在片测试结果表明：最大小信号增益为11.2 dB@140 GHz,3 dB带宽为16 GHz,芯片面积2.6×1.2 mm2。基于器件B设计的两级放大器B在片测试结果表明：最大小信号增益为15.8 dB@139 GHz,3dB带宽12 GHz,在130~150 GHz频带范围内增益大于10 dB,芯片面积1.7×0.8 mm2,带内最小噪声为4.4 dB、相关增益15 dB@141 GHz,平均噪声系数约为5.2 dB。放大器B具有高的单级增益、相对高的增益面积比以及较好的噪声系数。该放大器芯片的设计实现对于构建D波段接收前端具有借鉴意义。     

一种用于电视无源双基地雷达系统中的射频接收系统

主要介绍了一种低噪声大动态接收机的设计。该机用于电视无源双基地雷达系统中，接收参考信号直达波。该接收机采用了自行设计的低噪声射频放大器，降低了接收机的整机噪声系数，使用了AGC（自动增益控制）结构，大大提高了接收信号的范围。因此采用低噪声大动态接收机可以提高接收信号的灵敏度和信噪比，使得系统信号处理的准确度大大提高。     

2.4GHz带片上非平衡变压器射频前端的设计与优化

本文介绍了一种工作在2.4GHz频段的低功耗、低噪声、高线性射频接收机前端电路,该接收前端电路使用新型的带三种增益模式的LNA,并提出一种新的片上非平衡变压器优化技术。前端电路采用了直接变频结构,使用片上非平衡变压器实现低噪声放大器与下变频混频器之间的单端-差分转换,优化设计以提高前端电路的噪声性能。本文使用锗硅0.35um BiCMOS工艺,所采用的技术同样适用于CMOS工艺。前端电路总的最大转换增益为36dB;在高增益模式下的双边带噪声系数为3.8dB;低增益模式下,输入三阶交调点位12.5dBm。为了获得最大的输入动态范围,低噪声放大器采用三种可调增益模式,低增益模式使用by-pass结构,大大提高了大信号输入下接收前端的线性度。下变频混频器在输出端使用可调R-C tank,滤除带外高频杂波。混频器输出使用射极跟随器作为输出极驱动片外50ohm负载。该接收前端在2.85-V电源供电下,功耗为33mW,芯片面积为0.66mm2。     

5~6 GHz限幅低噪声放大器的研制

采用GaAs增强型pHEMT工艺,将限幅器和低噪声放大器集成在同一衬底,设计了一款用于5~6 GHz的限幅低噪声放大器。限幅器采用PIN二极管进行设计,低噪声放大器采用并联负反馈、源级电感负反馈以及电流复用结构,减小功耗的同时改善了增益平坦度和稳定性。测试结果表明,在工作频带内,限幅低噪声放大器的增益为27±0.2 dB,噪声系数为1.1~1.3 dB,总功耗为240 mW,耐功率大于46 dBm(2 ms脉宽,30%占空比),芯片尺寸为3.3 mm×1.3 mm。     

6?10 GHz ultra-wideband CMOS LNA

A two-stage matched ultra-wideband CMOS low noise amplifier (LNA) is presented. The LNA is designed to achieve a low noise figure with high voltage gain. The LNA fabricated in a 0.13 mum CMOS process shows a 3.9 dB average noise figure with a 27 dB voltage gain in the 6-10 GHz frequency band with a power consumption of 14 mW.     

高精度大动态范围音频数字增益控制器设计

设计了一种用于音频领域的高精度大动态范围对数型数字增益控制器,实现了在音频范围内的电压到电压对数型衰减控制,衰减范围为0~-94.5 dB,单位衰减量为-1.5 dB。增益控制字为8位信号DIN[7∶0],内部使用18位R-2R结构DAC实现精确衰减控制,使用对数译码逻辑减少输入控制字位数。设计了具有低噪声特性的轨到轨运算放大器,等效输入噪声仅为10.7 nV/Hz@1 kHz。仿真结果表明,设计的对数型数字增益控制器具有工作电压低、动态范围大、衰减精度高、等效输入噪声低等优点。     

Optimum Design for a Low Noise Amplifier in S-Band

An optimum design of a low noise amplifier (LNA) in S-band working at 2-4 GHz is described. Choosing FHC40LG high electronic mobility transistor (HEMT), the noise figure of the designed amplifier simulated by Microwave Office is no more than 1.5 dB, meanwhile the gain is no less than 20 dB in the given bandwidth. The simulated results agree with the performance of the transistor itself well in consideration of its own minimum noise figure (0.3 dB) and associated gain (15.5 dB). Simultaneously, the stability factor of the designed amplifier is no less than 1 in the given bandwidth.     

Optimum Design for a Low Noise Amplifier in S-Band

An optimum design of a low noise amplifier （LNA） in S-band working at 2-4 GHz is described. Choosing FHC40LG high electronic mobility transistor （HEMT）, the noise figure of the designed amplifier simulated by Microwave Office is no more than 1.5 dB, meanwhile the gain is no less than 20 dB in the given bandwidth. The simulated results agree with the performance of the transistor itself well in consideration of its own minimum noise figure （0.3 dB） and associated gain （15.5 dB）. Simultaneously, the stability factor of the designed amplifier is no less than 1 in the given bandwidth.     

A full W-band low noise amplifier module for millimeter-wave applications

A full W-band Low Noise Amplifier (LNA) Module is designed and fabricated in this letter. A broadband transition is introduced in this module. The proposed transition is designed, optimized based on the results from numerical simulations. The results show that 1 dB bandwidth of the transition ranges from 61 to 117 GHz. For the purpose of verification, two transitions in back-to-back connection are measured. The results show that transmission loss is only about 0.9-1.7dB. This transition is used to interface integrated circuits to waveguide components. The characteristic of the LNA module is measured after assembly. It exhibits a broad bandwidth of 75 to 110 GHz , has a small signal gain above 21 dB. The noise figure is lower than 5dB throughout the entire W-band (below 3 dB from 89 to 95GHz) at a room temperature. The proposed LNA module exhibits potential for millimeter wave applications due to its high small signal gain, low noise, and low dc power consumption     

一种带有外部噪声识别功能的AGC电路的设计

基于红外遥控接收芯片中自动增益控制电路的功能需求及其应用环境,设计了一种能够有效抑制外部环境光干扰、线性度高的自动增益控制电路。该电路在传统自动增益控制电路的设计理念基础上引入外部噪声识别功能,设计的核心子电路包括具有线性增益特性的可变增益放大器、比较器以及利用空闲时间识别外部噪声的信号检测与增益控制电路。电路基于0.25μm标准CMOS工艺设计,使用Hspice软件进行仿真验证。仿真结果表明:电源电压为3~5 V,温度为0~85℃时,可变增益放大器的可控增益范围至少可达-69.5~27.6 dB,且至少具有42 dB的线性增益控制范围。     

4～8GHz宽带单片集成低噪声放大器设计

基于0.15μm GaAs PHEMT工艺设计了一款C波段宽带单片集成低噪声放大器。电路由三级放大器级联而成,三级电路结构均使用电阻自偏压技术来实现单电源供电,它既可保证PHEMT管处于低噪声高增益的工作点,又可将所有元器件集成在单片GaAs衬底上,解决了供电复杂的问题。第三级电路采用了并联负反馈结构,降低了带内低频端...     

110-120-GHz monolithic low-noise amplifiers

The authors discuss the development of 110-120-GHz monolithic low-noise amplifiers (LNAs) using 0.1-mm pseudomorphic AlGaAs/InGaAs/GaAs low-noise HEMT technology. Two 2-stage LNAs have been designed, fabricated, and tested. The first amplifier demonstrates a gain of 12 dB at 112 to 115 GHz with a noise figure of 6.3 dB when biased for high gain, and a noise figure of 5.5 dB is achieved with an associated gain of 10 dB at 113 GHz when biased for low-noise figure. The other amplifier has a measured small-signal gain of 19.6 dB at 110 GHz with a noise figure of 3.9 dB. A noise figure of 3.4 dB with 15.6-dB associated gain was obtained at 113 GHz. The authors state that the small-signal gain and noise figure performance for the second LNA are the best results ever achieved for a two-stage HEMT amplifier at this frequency band     

Design and optimization of a 2.4 GHz RF front-end with an on-chip balun

A 2.4 GHz low-power,low-noise and highly linear receiver front-end with a low noise amplifier(LNA) and balun optimization is presented.Direct conversion architecture is employed for this front-end.The on-chip balun is designed for single-to-differential conversion between the LNA and the down-conversion mixer,and is optimized for the best noise performance of the front-end.The circuit is implemented with 0.35μm SiGe BiCMOS technology.The front-end has three gain steps for maximization of the input dynamic range.The overall maximum gain is about 36 dB.The double-sideband noise figure is 3.8 dB in high gain mode and the input referred third-order intercept point is 12.5 dBm in low gain mode.The down-conversion mixer has a tunable parallel R-C load at the output and an emitter follower is used as the output stage for testing purposes.The total front-end dissipation is 33 mW under a 2.85 V supply and occupies a 0.66 mm~2 die size.     

SIS quasiparticle mixers with bow-tie antennas

We have designed and evaluated planar lithographed W-band SIS mixers with bow-tie antennas and several different RF cou;ling structures. Both Pb-In-Au/Pb-Bi and Nb/Pb-In-Au junctions were used, each with ωR_NC«1. Single junctions and series arrays of five junctions directly attached to bow-tie antennas with no additional coupling structure gave poor performance, as expected. Single junctions with inductive microstrips and five-junction arrays with parallel wire inductors gave good coupling over bandwidths of ～5 and 25 percent respectively. Good agreement was found between design calculations based on a simple equivalent circuit and measurements of the frequency dependence of the mixer gain. When good coupling was achieved, typical values of mixer gain G_M (DSB)?0 dB, noise T_M(DSB)?150 K, and receiver noise ～200 K were observed. These measurements are referred to the cryostat window. When corrected for the estimated loss between the cryostat window and the antenna terminals, these values of gain are comparable to those observed for W-band waveguide mixers with IF matching, but the noise is significantly higher. There is evidence that ～100 K radiation surrounding the mixer reduces the gain and increases the noise. No systematic difference was observed between the performance of Pb-In-Au/Pb-Bi junctions and Nb/Pb-In-Au junctions when the area of the latter was made three times smaller and the current density three times larger so as to maintain the same capacitance and resistance.     

Radio Frequency Low Noise Amplifier with Linearizing Bias Circuit

A 1.34 GHz60 MHz low noise amplifier (LNA) designed in a 0.35 m SiGe process is presented. The designed LNA exhibits a power gain of 21.46 dB and a noise figure (NF) of 1.27 dB at 1.34 GHz. The linearity is improved with an active biasing technique. The post-layout simulation shows an input referred 1-dB compression point (IP1dB) of ?11.52 dBm. Compared with the recent reported high gain LNAs, the proposed LNA has a much better linearity without degrading other performance. The LNA draws 10 mA current from a 3.3 V power supply.     

用于雷达接收机检测的平面固态噪声源

设计了集成固态噪声源以测得雷达接收机的增益和噪声系数。设计采用国产噪声二极管开发平面集成固态噪声源用于接收机性能检测,包括噪声二极管集成、耦合器、驱动开关电路等。研究了平面集成固态噪声源超噪比(ENR)的测量方法,以及接收机噪声系数和增益的计算公式。固态噪声源和接收机电路无缝集成,极大减小了体积质量。设计的噪声源实现了28 dB的超噪比,较好地满足了接收机的检测要求,自检误差在可接受范围内。本设计通过了各类环境试验,并在实际产品中得到应用,取得较好的效果。