A fluxless flip-chip bonding for VCSEL arrays using silver-coated indium solder bumps

Alloys of lead-tin system are the most common solder alloys used today. However, there are environmental and health issues concerning the toxicity of lead present in these lead-tin solder alloys. Also, the flux residue removal is mandatory and leads to environmental threats. More importantly, the use of flux may contaminate the optically active surface by organic residue leftover, and a conventional cleaning method may not be effective for optoelectronic assemblies. Therefore, it is necessary to look for fluxless soldering processes for soldering optoelectronic systems. In the present study, we have conducted low-temperature flip-chip bonding of vertical-cavity surface-emitting laser (VCSEL) arrays on a glass substrate that provides propagation paths of laser beams and also supports a polymeric waveguide. Considering both the die shear test and the spreading test, the appropriate bonding temperature and pressure using indium solder bump were found to be about 150/spl deg/C/500 gf. The fracture occured between the indium solder bump and the VCSEL chip pad during the die shear test. It is inferred that both the low bonding temperature and the oxide layer which is formed on the surface of the indium solder prevented the bump from interacting with the chip pad. We expect the thin silver layer coating on the indium bump to protect the inner indium solder from oxidation and to decrease the melting temperature of the indium solder. Thus, we try coating a thin silver layer onto the indium surface. An eutectic reaction occurs at 97 wt.% of In with an eutectic point of 144/spl deg/C and the outer silver layer interacts with indium to form a AgIn/sub 2/ compound layer due to the high interdiffusion coefficient. As a result, the thin silver layer coated on the solder bump is very effective to enhance the adhesion strength between the indium bump and the VCSEL chip pads by decreasing the melting temperature of the indium solder bump locally.     

Growth prediction of tin/copper intermetallics formed between 63/37 Sn/Pb and OSP coated copper solder pads for a flip chip application

This study quantifies the effect of temperature and time on the growth of Cu-Sn intermetallics, specifically for flip chip/ball grid array packaging technology. The activation energy and the growth rates were determined for solid state diffusion, after the initial assembly reflow(s). Three different types of solder joints were investigated. 1) BGA 63/37 solder joints which were formed by a standard convection oven attach of 30 mil (760 /spl mu/m)diameter solder spheres to OSP protected, Cu plated ball pads of an organic flip chip substrate. The ball pads are solder mask defined and of 0.635 mm nominal diameter. 2) Flip chip bump pad solder joint consisting of 63/37 eutectic solder bumped die attached to a nonsolder mask defined, OSP protected, Cu plated pad of the flip chip substrate. The flip chip bumps on the die are created by screen printing solder paste on the die pads and subsequent reflow attach, by a standard convection oven to the die under bump metallurgy (UBM). The nominal die UBM pad diameter is 0.085 mm. 3) Solder joint formed on a coupon which involved the reflow of the balls randomly placed on a Cu plated layer with no solder mask coating. The investigation was performed by first establishing the intermetallic growth rate at six different temperatures, ranging from 85/spl deg/C to 150/spl deg/C. The relationship between intermetallic growth and time was shown to essentially follow the common parabolic diffusion relationship to temperature especially above 100/spl deg/C. The activation energy (E/sub a/) and the growth constant (k/sub 0/) were then calculated from this data. The results showed that the E. for the total intermetallic thickness was essentially similar for the three solder joint configurations of the ball, bump and the coupon described above. E. varied from 0.31 eV to 0.32 eV, while the k/sub 0/ varied from 18.0 /spl mu/m/s/sup 1/2 / to 24.2 /spl mu/m/s/sup 1/2 /.     

Plasma reflow bumping of Sn-3.5 Ag solder for flux-free flip chip package application

A new flux-free reflow process using Ar+10%H/sub 2/ plasma was investigated for application to solder bump flip chip packaging. The 100-/spl mu/m diameter Sn-3.5wt%Ag solder balls were bonded to 250-/spl mu/m pitch Cu/Ni under bump metallurgy (UBM) pattern by laser solder ball bonding method. Then, the Sn-Ag solder balls were reflowed in Ar+H/sub 2/ plasma. Without flux, the wetting between solder and UBM occurred in Ar+H/sub 2/ plasma. During plasma reflow, the solder bump reshaped and the crater on the top of bump disappeared. The bump shear strength increased as the Ni/sub 3/Sn/sub 4/ intermetallic compounds formed in the initial reflow stage but began to decrease as coarse (Cu,Ni)/sub 6/Sn/sub 5/ grew at the solder/UBM interface. As the plasma reflow time increased, the fracture mode changed from ductile fracture within the solder to brittle fracture at the solder/UBM interface. The off-centered bumps self-aligned to patterned UBM pad during plasma reflow. The micro-solder ball defects occurred at high power prolonged plasma reflow.     

Interfacial microstructure and strength of lead-free Sn-Zn-RE BGA solder bumps

Rare earth (RE) elements, primarily La and Ce, were doped in Sn-Zn solder to improve its properties such as wettability. The interfacial microstructure evolution and shear strength of the Sn-9Zn and Sn-9Zn-0.5RE (in wt%) solder bumps on Au/Ni/Cu under bump metallization (UBM) in a ball grid array (BGA) were investigated after thermal aging at 150 /spl deg/C for up to 1000 h. In the as-reflowed Sn-9Zn solder bump, AuSn/sub 4/ intermetallic compounds (IMCs) and Au-Zn circular IMCs formed close to the solder/UBM interface, together with the formation of a Ni-Zn-Sn ternary IMC layer of about 1 /spl mu/m in thickness. In contrast, in the as-reflowed Sn-9Zn-0.5RE solder bump, a spalled layer of Au-Zn was formed above the Ni layer. Sn-Ce-La and Sn-Zn-Ce-La phases were found near the interface at positions near the surface of the solder ball. Upon thermal aging at 150 /spl deg/C, the concentration of Zn in the Ni-Zn-Sn ternary layer of Sn-9Zn increased with aging time. For Sn-9Zn-0.5RE, the Au-Zn layer began to dissolve after 500 h of thermal aging. The shear strength of the Sn-9Zn ball was decreased after the addition of RE elements, although it was still higher than that of the Sn-37Pb and Sn-36Pb-2Ag Pb-bearing solders. The fracture mode of the Sn-9Zn system was changed from ductile to partly brittle after adding the RE elements. This is mainly due to the presence of the brittle Au-Zn layer.     

A reliability comparison of electroplated and stencil printed flip-chip solder bumps based on UBM related intermetallic compound growth properties

The effects of under bump metallurgy (UBM) microstructures on the intermetallic compound (IMC) growth of electroplated and stencil printed eutectic Sn-Pb solder bumps were investigated. The process parameters and their effects on UBM surface morphology and UBM shear strength were studied. For the electroplating process, the plating current density was the dominant factor to control the Cu UBM microstructure. For the stencil printing process, the zincation process has the most significant effect on the Ni UBM surface roughness and Ni grain sizes. In both processes, the good adhesion of UBM to aluminum can be obtained under suitable UBM processing conditions. Samples with different UBM microstructures were prepared using the two processes. The resulting samples were thermal aged at 85/spl deg/C, 120/spl deg/C, and 150/spl deg/C. It was observed that the Cu UBM surface roughness had larger effect on the IMC growth and solder ball shear strength than the Ni UBM surface roughness. The thickness of Cu/sub 3/Sn and Cu/sub 6/Sn/sub 5/ IMC depended strongly on the UBM microstructure. However, for Ni/Au UBM, no significant dependence was observed. More likely, the thickness of Au-Ni-Sn IMC near the IMC/solder interface was controlled by the amount of gold and the gold diffusion rate in the solder. Shear tests were performed after thermal aging tests and thermal/humidity tests. Different failure modes of different sample groups were analyzed. Electroless Ni UBM has been developed because it is a mask-less, low-cost process compared to electroplated Cu UBM. This study demonstrated that the process control was much easier for Ni UBM due to its lower reactivity with Sn material. These properties made Ni UBM a promising candidate for the lead-free solder applications.     

A study in flip-chip UBM/bump reliability with effects of SnPb solder composition

This paper aims to investigate the electromigration phenomenon of under-bump-metallization (UBM) and solder bumps of a flip-chip package under high temperature operation life test (HTOL). UBM is a thin film Al/Ni(V)/Cu metal stack of 1.5 μm; while bump material consists of Sn/37Pb, Sn/90Pb, and Sn/95Pb solder. Current densities of 2500 and 5000 A/cm² and ambient temperatures of 150–160 °C are applied to study their impact on electromigration. It is observed that bump temperature has more significant influence than current density does to bump failures. Owing to its higher melting point characteristics and less content of Sn phase, Sn/95Pb solder bumps are observed to have 13-fold improvement in Mean-Time-To-Failure (MTTF) than that of eutectic Sn/37Pb. Individual bump resistance history is calculated to evaluate UBM/bump degradation. The measured resistance increase is from bumps with electrical current flowing upward into UBM/bump interface (cathode), while bumps having opposite current polarity cause only minor resistance change. The identified failure sites and modes from aforementioned high resistance bumps reveal structural damages at the region of UBM and UBM/bump interface in forms of solder cracking or delamination. Effects of current polarity and crowding are key factors to observed electromigration behavior of flip-chip packages.     

Thermal cycling lifetime of flip chip on board circuits with solder bumps and isotropically conductive adhesive joints

Flip chip on board (FCOB) circuits with solder bumps or isotropically conductive adhesives (ICA) may be subject to joint failure during thermal cycling. Although use of epoxy underfill can increase the lifetime significantly, there is still a risk of failure if the material properties of the underfill material are not adequate to prevent excessive values of stress and strain in the joints. This paper presents experimental measurements of the number of thermal cycles to failure for both solder reflow and ICA joint FCOB circuits. Measurements have been carried out for several different material systems with various types of underfill. The measurements of solder bump lifetime are compared to a lifetime model based on analytical calculations of solder strain. For an underfill type without filler (CTE=58 ppm//spl deg/C), the measurements are in excellent agreement with the model predictions, both giving an average lifetime of around 1500 thermal cycles between -55 and 125/spl deg/C. For two filled types of underfill with CTE nearly matched to that of solder, the measured average lifetimes vary from around 2700 to 5500 cycles. The corresponding model predictions are around 6000 and 7000 cycles, respectively. Measurements of the lifetime of FCOB's with ICA connections have been carried out for two different material systems. The obtained lifetimes vary between approximately 500 and 4000 cycles. No systematic lifetime variation with the thermal expansion of the underfill has been observed, but the lifetime seems to be dependent on the properties of the bump on the chip pad. Delamination, for instance at the ICA/bump interface, is found to be an important cause of failure.     

Effect of bump size on current density and temperature distributions in flip-chip solder joints

Three dimensional thermo-electrical analysis was employed to simulate the current density and temperature distributions for eutectic SnAg solder bumps with shrinkage bump sizes. It was found that the current crowding effects in the solder were reduced significantly for smaller solder joints. Hot-spot temperatures and thermal gradient were increased upon reducing the solder. The maximum temperature for solder joint with 144.7 μm bump height is 103.15 °C which is only 3.15 °C higher than the substrate temperature due to Joule heating effect. However, upon reducing the bump height to 28.9 μm, the maximum temperature in the solder increased to 181.26 °C. Serious Joule heating effect was found when the solder joints shrink. The higher Joule heating effect in smaller solder joints may be attributed to two reasons, first the increase in resistance of the Al trace, which is the main heating source. Second, the average and local current densities increased in smaller bumps, causing higher temperature increase in the smaller solder bumps.     

Controllability of novel Sn/sub 0.95/Au/sub 0.05/ microbumps using interlaminated tin and gold layers for flip-chip interconnection

A flip-chip interconnection technology using novel lead-free solder microbumps with a balling temperature as low as 220 /spl deg/C is presented. Controllability of newly developed Sn/sub 0.95/Au/sub 0.05/ microbumps has been examined experimentally. By varying the bump volume and the diameter of the wettable bump electrodes, Sn/sub 0.95/Au/sub 0.05/ microbumps with heights from 11 /spl mu/m to 37 /spl mu/m were successfully fabricated with a standard deviation of 1.5 /spl mu/m. The deviation of on-chip CPW impedance from 50 /spl Omega/ was lower than 10% for nonmetallization motherboard. The smaller bumps exhibited a better performance since the degradation of reflection properties is ascribed to the bump capacitance, which was estimated 10-20 fF. Because of high process yield and good performance, the flip-chip bonding using Sn/sub 0.95/Au/sub 0.05/ microbumps of the order of 20 /spl mu/m in height may be advantageous for W-band interconnection of InP- or GaAs-based devices.     

Characterization of lead-free solders and under bump metallurgies for flip-chip package

A variety of Pb-free solders and under bump metallurgies (UBMs) was investigated for flip chip packaging applications. The result shows that the Sn-0.7Cu eutectic alloy has the best fatigue life and it possess the most desirable failure mechanism in both thermal and isothermal mechanical tests regardless of UBM type. Although the electroless Ni-P UBM has a much slower reaction rate with solders than the Cu UBM, room temperature mechanical fatigue is worse than on the Cu UBM when coupled with either Sn-3.8Ag-0.7Cu or Sn-3.5Ag solder. The Sn-37Pb solder consumes less Cu UBM than all other Pb-free solders during reflow. However, Sn-37Pb consumes more Cu after solid state annealing. Studies on aging, tensile, and shear mechanical properties show that the Sn-0.7Cu alloy is the most favorable Pb-free solder for flip chip applications. When coupled with underfill encapsulation in a direct chip attach (DCA) test device, the Sn-0.7Cu bump with Cu UBM exhibits a characteristic life or 5322 cycles under -55/spl deg/C/+150/spl deg/C air-to-air thermal cycling condition.     

A new COG technique using low temperature solder bumps for LCD driver IC packaging applications

A new chip on glass (COG) technique using flip chip solder joining technology has been developed for excellent resolution and high quality liquid crystal display (LCD) panels. The flip chip solder joining technology has several advantages over the anisotropic conductive film (ACF) bonding technology: finer pitch capability, better electrical performance, and easier reworkability. Conventional solders such as eutectic Pb-Sn and Pb-5Sn require high temperature processing which can lead to degradation of the liquid crystal or the color filter in LCD modules. Thus it is desirable to develop a low temperature process below 160/spl deg/C using solders with low melting temperatures for this application. In our case, we used eutectic 58 wt%Bi-42 wt%Sn solder for this purpose. Using the eutectic Bi-Sn solder bumps of 50-80/spl mu/m pitch sizes, an ultrafine interconnection between the IC and glass substrate was successfully made at or below 160/spl deg/C. The average contact resistance of the Bi-Sn solder joints was 19m/spl Omega/ per bump, which is much lower than the contact resistance of conventional ACF bonding technologies. The contact resistance of the underfilled Bi-Sn solder joints did not change during a hot humidity test. We demonstrate that the COG technique using low temperature solder joints can be applied to advanced LCDs that lead to require excellent quality, high resolution, and low power consumption.     

Anisotropic behavior of the capillary action in flip chip underfill

An underfill encapsulant can be used to improve the long-term reliability of flip chip interconnecting system by filling the gap between the chip and substrate around the solder bumps. The underfill encapsulant was filled by a capillary flow. This study was devoted to investigate the anisotropic effects of the capillary action induced by the solder bumps. A modified Hele-Shaw flow model, considering the flow resistance in both the thickness direction and the restrictions between solder bumps, was used. A capillary force model, depending on the direction of filling flow, for full array solder bumps was proposed. The capillary force was formulated based on quadrilateral arrangement of solder bumps. It was found that the capillary action is not the same for different directions. In the 45° direction, enhancement of the capillary flow was noticed for a bump pitch within a critical value. The edge preferential flow during the underfill experiment could be attributed to the anisotropic behavior of the capillary action.     

Double bump flip-chip assembly

Capillary underfill remains the dominate process for underfilling Hip-chip die both in packages and for direct chip attach (DCA) on printed circuit board (PCB) assemblies. Capillary underfill requires a post reflow dispense and cure operation, and the underflow time increases with increasing die area and decreasing die-to-substrate spacing. Fluxing or no-How underfills are dispensed prior to die placement and cure during the solder reflow cycle. Since filler particles in the fluxing underfill can be trapped between the solder ball and the substrate pad during placement, the filler content of fluxing underfills is typically limited to <20% or assembly yield drops dramatically. At 20% filler concentration, the coefficient of thermal expansion (CTE) of the underfill is near that of the bulk resin (50-80 ppm//spl deg/C). In this paper, a double bump Hip-chip process is described. A filled capillary underfill is coated onto a wafer and cured. The wafer is then polished to expose the solder bumps. A second solder bump is formed over the original bump by stencil printing solder paste. After dicing, the die is assembled to the PCB using unfilled fluxing underfill. In the resulting structure, the low CTE underfill is near the low CTE Si die, and the higher CTE underfill is in contact with the PCB. In addition, the standoff height is increased compared to a conventional single bump assembly. In air-to-air thermal shock tests, the double bump assembly was /spl sim/ 1.5 X more reliable than the conventional single bump construction with fluxing underfill. Modeling results are also presented.     

in-situ electromigration study on Sn−Ag−Cu solder joint by digital image speckle analysis

The phenomenon of electromigration in Pb-free Sn−Ag−Cu solder joint specimens subject to high current density was characterized. Digital image speckle analysis (DISA) was used to measure the in-situ microdeformation and strain of cross-sectioned solder joints, which are subject to electromigration with a current density of 5 × 10³ A/cm² under an ambient temperature of 150°C. After a 120 h electromigration test, a higher strain near large voids was detected near preexisting voids in the solder joints. The current-crowding effect on strain formation was characterized, as it was found that the strain is high near the interface, while in the middle of the solder bump, the strain is low and could be neglected. Nanoindentation markers were used to form dummy voids to study the effect of preexisting voids. The Sn atomic flux and its effect on formation of electromigration strain are discussed.     

Electromigration Failure Mechanism in Sn-Cu Solder Alloys with OSP Cu Surface Finish

Organic solderable preservative (OSP) has been adopted as the Cu substrate surface finish in flip-chip solder joints for many years. In this study, the electromigration behavior of lead-free Sn-Cu solder alloys with thin-film under bump metallization and OSP surface finish was investigated. The results showed that severe damage occurred on the substrate side (cathode side), whereas the damage on the chip side (cathode side) was not severe. The damage on the substrate side included void formation, copper dissolution, and formation of intermetallic compounds (IMCs). The OSP Cu interface on the substrate side became the weakest point in the solder joint even when thin-film metallization was used on the chip side. Three-dimensional simulations were employed to investigate the current density distribution in the area between the OSP Cu surface finish and the solder. The results indicated that the current density was higher along the periphery of the bonding area between the solder and the Cu pad, consistent with the area of IMC and void formation in our experimental results.     

Studies on solder bump electromigration in Cu/Sn–3Ag–0.5Cu/Cu system

This paper aims to understand the solder bump electromigration phenomenon in the Cu/Sn–3Ag–0.5Cu/Cu system. A temperature of 453 K with a current density of 10 kA/cm² was applied. A void nucleated at the highest current density point at the cathode. As the void grew along the cathode side, a solder depletion occurred on the opposite side of the electron entry point, resulting in an open failure. A unique purposely-designed 3D model simulation methodology provides a good understanding of the void nucleation and growth behavior. The temperature of the solder joint during the electromigration test was measured successfully by the resistance change in the junction line between the two joints.     

Microstructure Evolution of Cu-Cored Sn Solder Joints Under High Temperature and High Current Density

This work investigated the microstructure evolution of Cu-cored Sn solder joints under high temperature and high current density. The Cu₆Sn₅ phase formed at both the Cu core/Sn interface and Cu wire/Sn interface right after reflow and grew with increasing annealing time, while the Cu₃Sn phase formed and grew at the Cu/Cu₆Sn₅ interfaces. Intermetallic compound (IMC) growth followed a linear relationship with the square root of annealing time due to a diffusion-controlled mechanism. Under high current density, the thickness of the interfacial IMCs of the Cu core/Sn interface at the cathode side increased and the Cu core/Sn interface at the anode side exhibited an irregular and serrated morphology with prolonged current stressing time. Finite-element simulation was carried out to obtain the distribution of current density in the solder joint. Since Cu has lower resistivity, the electrical current primarily selected the Cu core as its electrical path, resulting in current crowding at the Cu core and the region between the Cu core and Cu wire. Compared with the conventional solder joint, the electromigration (EM) lifetime of the Cu-cored solder joint was much longer.     

Wave soldering bumping process incorporating electroless nickel UBM

The Si/Ti/Cu/electroless nickel/solder bump was produced incorporating wave soldering without flux. The most suitable wave soldering condition for depositing solder is presented. The material interactions occurring during wave soldering, afterwards reflow, and extended heat treatment were found to produce Ni₃Sn₂ , Ni₃Sn₄, and Ni₄Sn compounds between solder and electroless nickel deposit. The thickness of electroless nickel deposit required for being the barrier layer of the solder bump was investigated by reflow process     

Calibration of electromigration reliability of flip-chip packages by electrothermal coupling analysis

Electromigration reliability of solder interconnects is dominated by current density and temperature inside the interconnects. For flip-chip packages, current densities around the regions where the traces connect a solder bump increase significantly due to the differences in feature sizes and electric resistivities between the solder bump and its adjacent traces. This current-crowding effect along with induced Joule heating accelerates electromigration failures. In this paper, the effects of current crowding and Joule heating in a flip-chip package are examined and quantified by three-dimensional electrothermal coupling analysis. We apply a volumetric averaging technique to cope with the current-crowding singularity. The volumetrically averaged current density and the maximum temperature in a solder bump are integrated into Black’s equation to calibrate the experimental electromigration fatigue lives. An erratum to this article is available at .     

An investigation of effects of Sb on the intermetallic formation in Sn-3.5Ag-0.7Cu solder joints

This study investigates the microstructural evolution and kinetics of intermetallic (IMC) formation in Sn-3.5Ag-0.7Cu lead-free solder joints with different percentages of Sb element, namely, Sn-3.5Ag-0.7Cu-xSb (x=0, 0.2, 0.5, 0.8, 1.0, 1.5, and 2.0). To investigate the elemental interdiffusion and growth kinetics of IMC formation, isothermal aging test is performed at temperatures of 100/spl deg/C, 150/spl deg/C, and 190/spl deg/C, respectively. Scanning electron microscope (SEM) is used to measure the thickness of intermetallic layer and observe the microstructural evolution of solder joint. The IMC phases are identified by EDX and XRD. Results show that some of the antimony powders are dissolved in the /spl beta/-Sn matrix (Sn-rich phase), some of them participate in the formation of Ag/sub 3/(Sn,Sb) and the rest dissolves in the Cu/sub 6/Sn/sub 5/ IMC layer. There is a significant drop in IMC thickness when Sb is added to 0.8 wt%. Over this amount the thickness of the IMC increases slightly again. The activation energy and growth rate of the IMC formation are determined. Results reveal that adding antimony in Sn-3.5Ag-0.7Cu solder system can increase the activation energy, and thus reduce the atomic diffusion rate, so as to inhibit the excessive growth of the IMC. The solder joint containing 0.8 wt% antimony has the highest activation energy. SEM images reveal that the number of small particles precipitating in the solder matrix increases with the increase in Sb composition. Based on the observation of the microstructural evolution of the solder joints, a grain boundary pinning mechanism for inhibition of the IMC growth due to Sb addition is proposed.