Collection of charge from alpha-particle tracks in silicon devices

Experimentally and by computer simulation, we have investigated the collection process of alpha-particle-generated charge in silicon devices. We studied the total charge collected and the transient characteristics of collection for various structures. Analytic results indicate that a strong drift field extends far beyond the original depletion layer, and funnels a large number of carriers into the struck node. This field-funneling component of charge collection is a strong function of substrate resistivity and bias voltage. It is relatively independent of the area of the struck device. The collection is less efficient for a small capacitance node. The funneling also occurred with a time delay when an alpha particle missed the field region by a short distance. Devices on an n-type substrate were also studied. They exhibit a similar funneling effect as the p-type substrate. The agreement between measurement and simulation is excellent. The impact on future VLSI design is discussed.     

Analysis of persistent photoconductivity due to potential barriers

Persistent photoconductivity has been seen in thin silicon resistors fabricated with SIMOX material at temperatures between 60 and 220 K. This effect has been attributed to the depletion of carriers near the interface between the top silicon layer and the buried oxide, which is due to the large number of surface traps at this interface. The depletion of carriers is accompanied by a built-in field on the order of 10,000 V/cm, which causes a potential barrier that is nearly a quarter of the energy gap of silicon. The theory of the recombination kinetics of majority carriers with minority carriers trapped at the interface on the other side of a potential barrier is studied. Both the possibilities of tunneling and thermal activation have been considered. The results show that thermal activation dominates at the temperatures of our measurements in SIMOX material, while at lower temperatures tunneling would dominate.     

1/f noise in gate-controlled planar silicon diodes

Low-frequency excess noise in planar bipolar silicon devices was investigated by means of gate-controlled n+?p diodes. Within the range of parameter values covered in this investigation, it was found that the noise-power maxima invariably occur at gate bias voltages leading to depletion of majority carriers at the surface of the high-resistivity side of the p?n junction.     

Soft errors induced by alpha particles

Soft errors induced by alpha particles can be a reliability concern for microelectronics, especially semiconductor memory devices packaged in ceramic. In dynamic random-access memory devices (DRAM), the data are stored as the presence or absence of minority carrier charges on storage capacitors. For example, in n-channel MOS memory devices, the charge carriers are electrons and the capacitors are potential wells in the p-type silicon. Alpha particles emitted from trace levels of uranium and thorium in the packaging materials can penetrate the surface of the semiconductor die. As the alpha particle passes through the semiconductor device, electrons an dislodged from the crystal lattice sites along the track of the alpha particle. If the total number of generated electrons collected by an empty storage well exceeds the number of electrons that differentiates between a 1 and a 0, the collected electron charge can flip a 1 to a 0 generating a soft error in the memory device. The trend toward increased chip density, smaller device dimensions, and lower voltages further increases the susceptibility of DRAM to soft errors. The susceptibility of DRAM to soft errors is typically measured by accelerated tests or real-time SER tests, each of which have strengths and weaknesses. Knowledge of the factors which lead to soft errors can be used to improve reliability in DRAM by using a physics-of-failure approach to monitor variables in the manufacturing process resulting in building reliability into the manufacturing process     

Modeling of minority-carrier surface recombination velocity atlow-high junction of an n+-p-p+ silicon diode

Modeling of recombination velocity of minority carriers at the p-p ⁺ low-high junction end of the p-base region of n⁺-p-p⁺ silicon diodes is carried out by taking the minority-carrier recombination effects in the space-charge region (SCR) of the low-high (L-H) junction into account. Solving Poisson's equation in the SCR numerically revealed that the SCR is composed of an accumulation layer on the p side and a depletion layer on the p⁺ side. Generally, the depletion layer is very thin as compared with the accumulation layer, and the built-in potential across the depletion layer never exceeds the thermal voltage, i.e. kT/q. Further, the minority-carrier recombination in this layer is also insignificant. For most L-H junction-based silicon devices, in practice, the minority-carrier recombination in the accumulation layer controls the value of the effective minority-carrier recombination velocity (S_eff) at the back surface of the p-base region and the influence of the recombination in the heavily doped p⁺ region is less significant     

Current gain and cutoff frequency falloff at high currents

A theoretical and experimental study of the effects of high-level injection of carriers into a reverse-biased collector-base junction has been performed. Two models which describe the high-current behavior of the junction space-charge region are discussed. The first deals with the formation of a current-induced base region at space-charge-limited current densities. The second model assumes that two-dimensional effects are predominant; at current densities corresponding to the onset of space-charge-limited current, lateral injection of carriers takes place. These phenomena were studied experimentally using silicon double-diffused transistor structures. The existence of space-charge-limited current in the reverse-biased collector depletion layer manifests itself in significant changes in the ac and dc parameters of the transistor. In particular, it is shown that the cutoff frequency (fT) and large-signal current gain (hFE) begin to decrease rapidly with increasing current at the onset of the space-charge limitation. A comparison of experimental results with predictions of the above theories indicates that, while both the formation of a current-induced base region and lateral injection do take place, the latter mechanism controls conventional device performance.     

等效表面电荷对台面半导体器件钝化的影响

进一步研究了半导体斜角造型p-n结的表面空间电荷层模型与表面耗尽区模型.计算了耗尽情况下p-n结的表面空间电荷密度,分析了等效表面电荷密度对正斜角造型p-n结表面耗尽区的影响.利用聚酰亚胺和聚酯改性漆钝化的晶闸管电学特性证实了等效表面电荷密度对台面半导体钝化的影响.同时,通过分别采用聚酰亚胺和掺氧多晶硅钝化的高压整流管研究表明,基于掺氧多晶硅的钝化结构具有屏蔽电荷和均匀电场的作用.     

点状PN结中的光电转换

用Ｎ型硅单晶材料制作了点状ＰＮ结光电二极管，对二极管的光电参数进行了测量。若依平面结的受光面积计算，在同样的光辐射下，点状ＰＮ结光岂二极管的光电流密度是常规面积光电二极管光电流密度的２００倍以上。分析表明，在光探测机制上不仅要考虑平面结范围内的光电转换，更要考虑平面结周边一个少数载流子扩散长度范围内的光电转换。利用点状ＰＮ结光照电流的测量，可以 确定在衬底材料光一少了的扩散长度。     

Properties of Au,Pt, Pd and Rh levels in silicon measured with a constant capacitance technique

Measurements of emission rates and majority carrier capture cross-sections of Au, Pt, Pd and Rh centres in silicon are reported, and the activation energies associated with the different levels of these centres are determined. Where appropriate, our results are compared with values reported in the literature; other results have not been previously reported. The measurement depends on the emission and capture of majority carriers on the centres in the depletion layer of a p-n junction or Schottky barrier. The change in charge state of the centres is monitored by measuring the change in reverse bias applied to the junction necessary to keep the junction capacitance constant. The advantage of this technique, compared with the usual method of keeping the bias voltage constant and measuring the change in capacitance, is demonstrated.     

多晶硅TFT热载流子效应的模拟研究

热载流子效应引起的器件电学特性退化会严重影响电路的工作性能。文章结合多晶硅薄膜晶体管沟道电流的理论模型,讨论了热载流子效应与界面陷阱的关系。沟道载流子在大的漏电场牵引下,运动到漏结附近获得很大的能量从而成为热载流子。如果热载流子能量超过Si-SiO2界面势垒高度,会注入到栅氧层或陷落到界面陷阱,使阈值电压和沟道电流发生退化现象。同时,对多晶硅薄膜晶体管输出特性进行了模拟分析,模拟结果与理论模型基本一致。     

Characteristics of diffused P-N junctions in epitaxial layers

A one-dimensional analysis has been made to determine properties of diffused p-n junctions in epitaxial layers with nonuniform impurity concentration. Impurity diffusion from the surface and from the substrate is assumed to have complementary error function distribution. The transcendental equations obtained by analytical integration of Poisson's equation were evaluated numerically with the IBM 7090/94. Junction depth, impurity gradient and impurity level at the junction are given for a variety of diffusion parameters and impurity concentrations. In addition, graphs are presented, showing the relationship between reverse voltage and depletion layer thickness, capacitance per unit area, and peak electric field for the case of silicon. A comparison between the actual impurity profile and the usual linear approximation using the impurity gradient at the junction gives the range of depletion layer thickness or reverse voltage in which such an approximation is justified. Further, examples are presented of the electric field distribution in the depletion layer for several impurity concentration profiles. Calculated and experimentally determined values of some readily accessible junction characteristics show reasonably good agreement.     

Hot-electron-induced minority-carrier generation in bipolarjunction transistors

The authors report on the observation and analysis of minority-carrier generation in the collector and the substrate of n-p-n bipolar junction transistors as a result of photons which are generated in the collector-base depletion region. Both the substrate current and the additional leakage current peak at V_BE~0.8 V. In the authors' model of the phenomena, the photons induce the generation of carriers both in the depletion region and in the neutral region. The generated minority carriers in the neutral region diffuse and contribute to the substrate current and the junction leakage current. The contribution of the carriers that are generated in the depletion region is not dominant     

双掺硅P-N结特性

双掺硅单晶片经热氧化后在其表面能够形成浅而均匀的P-N结.本文研究这类P-N结的基本特性,在耗尽层近似下给出P-N结空间电荷区中电场分布和电势的解析表达式,并讨论分析P-N结的光电特点.研究结果说明:双掺硅P-N结很有可能应用于光电器件、太阳能电池、集成电路和某些特殊器件.     

Famos—A new semiconductor charge storage device

A new non-volatile charge storage device is described. The floating gate avalanche injection MOS (FAMOS) structure is a p-channel silicon gate field effect transistor in which no electric contact is made to the silicon gate. It combines the floating gate concept with avalanche injection of electrons from the surface depletion region of a p-n junction to yield reproducible charging characteristics with long term storage retention.     

A field-enhanced generation model for field emission from p-typesilicon

Field penetration into p-type silicon emitter creates a depletion region and causes the field emission current to he limited by the supply of electrons in the presence of a high electric field. A model is presented that takes field-enhanced generation within the depletion region into account, which may explain the nonlinear phenomenon in Fowler-Nordheim (F-N) plots of p-type silicon     

A Hybrid Silicon–AlGaInAs Phase Modulator

We demonstrate a carrier depletion phase modulator based on the hybrid silicon evanescent platform. A low temperature and robust bonding process is employed to transfer III–V epitaxial layers to patterned silicon waveguides. An external electric field is applied across the doped multiple quantum wells so that carriers are depleted, resulting in an index change. The device has a voltage-length product, ${V}_{pi }$ L, of 4 V-mm at 1550 nm. An optical bandwidth of 100 nm with an extinction ratio over 10 dB is achieved. The device can handle optical power up to 28 mW.      

基于结模型的极化石英玻璃内建电场分析

用多载流子模型分析玻璃的热极化过程及其内部耗尽层的形成,极化电场的作用使载流子在玻璃内的迁移及由外界的注入最终形成交替的电荷分布,形成类似两个相向p-n结的结构。针对几种典型的p-n结电荷分布形式,计算了相应内建电场及二阶非线性极化率,极化完成后产生的宏观非线性效应主要由钠离子耗尽形成的突变结电场(~3′109V/m)决定,二阶非线性极化率的数值在0.2~1.2pm/V之间,耗尽区分布在阳极表面下25mm的范围。     

一种沟槽-场限环复合终端结构的设计

为了改善硅功率器件击穿电压性能以及改善IGBT电流的流动方向,提出了一种沟槽-场限环复合终端结构。分别在主结处引入浮空多晶硅沟槽,在场限环的左侧引入带介质的沟槽,沟槽右侧与场限环左侧横向扩展界面刚好交接。结果表明,这一结构改善了IGBT主结电流丝分布,将一部分电流路径改为纵向流动,改变了碰撞电离路径,在提高主结电势的同时也提高器件终端结构的可靠性;带介质槽的场限环结构进一步缩短了终端长度,其横纵耗尽比为3.79,较传统设计的场限环结构横纵耗尽比减少了1.48%,硅片利用率提高,进而减小芯片面积,节约制造成本。此方法在场限环终端设计中非常有效。     

High-speed light Modulation in avalanche breakdown mode for Si diodes

The light emission process from a p-n junction in the forward-bias region is slow to respond to modulation signals due to the indirect band structure of silicon. Experimental results for a reverse-bias region showing light modulation in the range of tens of gigahertz are observed for the first time. For such a light emitter, the limiting speed of light modulation is shown to be determined by the transit time of the minority carriers across the junction during the filament formation of breakdown currents, which has been demonstrated by simulation of the propagation of a shockwave-like pattern in the breakdown field.     

Effect of a d.c. electric field parallel to the depletion layer on the microwave oscillations in a p-i-n IMPATT diode

High frequency properties of a p-i-n IMPATT diode have been analysed when an additional d.c. electric field parallel to the area of the junction and perpendicular to the high electric field caused by reverse biasing the device is established in the space charge layer. The transit time required by the carriers to cross the depletion layer is increased due to the increase in the path length caused by the change in the direction of the resultant field while the velocity of the carriers remain saturated. It is found that the frequency for maximum negative resistance decreases with the increase of the additional d.c. electric field.