A wideband low‐spur 0.18‐µm CMOS phase‐locked loop with bandwidth calibration

This paper presents a 0.18‐µm complementary metal‐oxide‐semiconductor wideband phase‐locked loop with low reference spurs. The dual‐level charge‐pump current calibration technique is proposed to maintain a constant loop bandwidth for wide operation frequency range and achieve low reference spurs. The first level charge‐pump current calibration is seamlessly incorporated in the automatic frequency band hopping control and the mechanism also ensures enough negative transconductance for the voltage‐controlled oscillator to function throughout the whole frequency range. The charge‐pump current mismatch is calibrated by the second level charge‐pump current calibration combined with the pulse‐width scaling technique. The operation frequency range of the phase‐locked loop covers from 4.7 GHz to 6.1 GHz. The measured phase noise is?116 dBc/Hz at 1‐MHz offset and the reference spurs are below?66.8 dBc. Copyright © 2015 John Wiley & Sons, Ltd.     

A White LED Driver Using a Buck–Boost Converter

For mobile backlighting applications, a white LED (WLED) driver using a buck–boost converter is proposed in this letter. Unlike conventional converters using boost converters, 2×/1.5× charge pumps, and so on, the proposed converter offers the negative stepped‐down voltage to drive the LED's cathode only when the input voltage is insufficient to drive a 1× transfer mode. Furthermore, unlike the LED backlight using charge pumps, the proposed converter can adjust the output voltage by controlling the duty factor of the clock pulse. Thus, the proposed converter can realize high power efficiency. The validity of the proposed converter is confirmed by simulations and experiments. © 2010 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

A new fast‐lock,low‐jitter,and all‐digital frequency synthesizer for DVB‐T receivers

Lock time and convergence time are the most important challenges in delay‐locked loops (DLLs). In this paper we cover French very high frequency band with a novel all‐digital fast‐lock DLL‐based frequency synthesizer. Because this new architecture uses a digital signal processing unit instead of using phase frequency detector, charge pump, and loop filter in conventional DLL, therefore, it shows better jitter performance, lock time, and convergence speed than previous related works. Optimization methods are used to make input and output signals of the proposed DLL in phase. The proposed architecture is designed to cover all channels of French very high frequency band by choosing number of delay cells in signal path. Simulation has been done for 22–27 delay cells, and f_REF = 16 MHz, which can produce output frequency in range of 176–216 MHz. Locking time is approximately 0.3 µs, which is equal to five clock cycles of reference clock. All of the simulation results show superiority of the proposed structure. Copyright © 2013 John Wiley & Sons, Ltd.     

An Approach to a Higher‐Power‐Density Power Supply for a 380‐V DC Distribution System

A methodology for realizing a higher‐power‐density DC‐DC converter has been proposed for a power unit installed in a 380‐V DC distribution system. The possibility of the converter design will be strengthened by using the series–parallel connection topology for isolated DC‐DC converters. A converter prototype with a power density of 10 W/cm³ has been fabricated, and the feasibility of the converter design has been confirmed experimentally. This result contributes to the realization of a highly efficient and highly space‐saving 380‐V DC distribution system. © 2013 Wiley Periodicals, Inc. Electr Eng Jpn, 186(3): 51–62, 2014; Published online in Wiley Online Library ( wileyonlinelibrary.com ). DOI 10.1002/eej.22494     

Fast‐transient DC‐DC converter using a high‐performance error amplifier with a rapid output‐voltage control technique

This letter presents a method for improving the transient response of DC‐DC converters. The proposed technique replaces the conventional error amplifier with a combination of two different amplifiers to achieve a high loop gain and high slew rate. In addition, a rapid output‐voltage control circuit is employed to further reduce the recovery time. The proposed technique was applied to a four‐phase buck converter, and the chip was implemented using a 0.18‐μm CMOS process. The switching frequency of each phase was set at 2 MHz. Using a supply voltage of 2.7–5.5 V and an output voltage of 0.6–1.5 V, the regulator provided up to 2‐A load current with maximum measured recovery time of only 6.2 and 6.5 μs for increasing and decreasing load current, respectively. Copyright © 2017 John Wiley & Sons, Ltd.     

A hybrid input charge‐pump using micropower thermoelectric generators

For industrial wireless transmitters, a hybrid input charge‐pump utilizing thermoelectric energy from waste heat is proposed in this paper. Unlike conventional converters, the proposed capacitor‐based converter supplies energy to a wireless transmitter by using a thermoelectric power source in combination with a rechargeable battery source. By combining the battery voltage and the thermoelectric generator (TEG) voltage, the proposed converter achieves a wider input range than conventional converters. Consequently, the proposed converter will enable the development of not only an industrial wireless transmitter but also various clean energy applications. Through theoretical analyses, simulations, and experiments, the following results are shown: 1. Even if the voltage of the TEG is small, the proposed converter can provide the sufficient voltage by compensating the insufficient voltage of the TEG with the battery voltage. 2. The formulas obtained by the theoretical analyses are useful for designing the proposed converter because the theoretical results correspond well with the simulation results. © 2012 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

Design of a dual‐input SC DC–DC converter realizing negative outputs

Aimed at a back‐lighting application, a dual‐input switched‐capacitor (SC) DC–DC converter with battery charge process is proposed in this paper. The proposed converter can realize −1/N× (N = 2,3,…) step‐down conversion as well as (N + 1)/N× step‐up conversion. By converting clean energy such as solar energy, the proposed dual‐input converter not only drives light‐emitting diodes (LEDs) but also recharges the battery, although conventional single‐input converter only consumes battery energy. In the proposed converter, the −1/N× stepped‐down voltage is generated to drive the LED's cathode when the input voltage is insufficient to drive a 1× transfer mode. Furthermore, unlike conventional converters, the battery is charged by the (N + 1)/N× stepped‐up voltage when the LED back light is in standby mode. Hence, the proposed converter can realize long battery run time. The validity of circuit design is confirmed by theoretical analyses, simulations, and experiments. The derived theoretical formulas will be helpful to estimate circuit characteristics, because the theoretical results correspond well with the simulation program with integrated circuit emphasis (SPICE) simulation results. © 2011 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

A reduced reference spur multiplying delay‐locked loop

This letter presents a reduced reference spur multiplying delay‐locked loop (MDLL). The static phase offset (SPO) between the reference edge and its counterpart of MDLL output is the dominant mechanism causing reference spur in the spectrum of MDLL output. SPO is mainly caused by the non‐idealities on charge pump (e.g., sink and source current mismatch) and control line (e.g., gate leakage of loop filter and voltage‐controlled delay line control circuit). With a high‐gain stage inserting between phase detector/phase frequency detector and charge pump, the equivalent SPO has been decreased by a factor equal to the gain of the gain stage. To validate the effectiveness of the proposed technique, an MDLL is implemented in TSMC CMOS 0.18 µm process. The simulation result shows that ?60.1 dBc reference spur was achieved at center frequency of 1.8 GHz. Copyright © 2015 John Wiley & Sons, Ltd.     

A self‐calibrated delay‐locked loop with low static phase error

In conventional delay‐locked loop circuits, the charge and discharge of the charge pump result in mismatched current reflecting the size of the static phase error. The static phase error between feedback clock and reference clock is likely to be within tens or hundreds of picoseconds (ps). We thus propose an approach using digital calibration methods to reduce the charge pump current mismatch by means of the setup time of the D‐type flip flop. The setup time of D‐type flip flop is determined and duplicated to detect the phase error between the reference clock and feedback clock. It results in a very small static phase error between the reference clock and feedback clock. This paper used a 0.18 µm CMOS process design, with a reference frequency of 700 ~ 900 MHz. The active area is 0.031 mm², and the phase error after correction is less than 5 ps. Copyright © 2015 John Wiley & Sons, Ltd.     

A new fast‐response buck converter using accelerated pulse‐width‐modulation techniques

A new fast‐response buck converter using accelerated pulse‐width‐modulation techniques is proposed in this article. The benefits of the accelerated pulse‐width‐modulation technique is fast‐transient response, simple‐compensation design, and no requirement for slope compensation; furthermore, some power management problems are minimized, such as EMI (Electro Magnetic Interference), size, design complexity, and cost. The traditional voltage‐mode speed is slower with the transient response, so an accelerated pulse‐width‐modulation technique is used to solve the problem of slowed transient response in this article. The proposed buck converter has excellent conversion efficiency with a wide load conditions. The proposed buck converter has been fabricated with TSMC 0.35 µm CMOS 2P4M processes, and the total chip area is 1.32 × 1.22 mm². Maximum output current is 300 mA when the output voltage equals 1.8 V. When the supply voltage is 3.6 V, the output voltage can be 1–2.6 V. Maximum transient response is less than 5 µs. The simulation and experimental results are presented in this article. Copyright © 2011 John Wiley & Sons, Ltd.     

Dynamics of charge‐pump phase‐locked loops

Certain problems in the existing treatment of the stability of charge‐pump phase‐locked loops are identified and addressed in this work. New results concerning the instability, stability, and asymptotic stability of charge‐pump phase‐locked loops are obtained by means of Lyapunov's direct and indirect methods. Closer consideration of the local dynamics provides further insight into the system's patterns of behavior. In particular, the influence of circuit parameters on the nature of the steady‐state orbits is investigated. Copyright © 2012 John Wiley & Sons, Ltd.     

Graph‐theoretical approach to 2‐switch DC–DC converters

This paper presents a graph‐theoretic approach to analyse and synthesize switch mode DC–DC converters. The result is based on the state‐space averaging equation and the fundamental graph theory. Hence our proposed method is applied to various kinds of DC–DC converters with two switches and topological conditions for two‐switch DC–DC converters are obtained systematically. Copyright © 2005 John Wiley & Sons, Ltd.     

Pulse current regenerative resonant snubber‐assisted two‐switch flyback‐type ZVS PWM DC‐DC converter

In this paper, a two‐switch high‐frequency flyback transformer‐type zero voltage soft‐switching PWM DC‐DC converter using IGBTs is proposed. Effective applications for this power converter can be found in auxiliary power supplies of rolling stock transportation and electric vehicles. This power converter is basically composed of two active power switches and a flyback high‐frequency transformer. In addition to these, two passive lossless snubbers with power regeneration loops for energy recovery, consisting of a three‐winding auxiliary high‐frequency transformer, auxiliary capacitors and diodes are introduced to achieve zero voltage soft switching from light to full load conditions. Furthermore, this power converter has some advantages such as low cost circuit configuration, simple control scheme, and high efficiency. Its operating principle is described and to determine circuit parameters, some practical design considerations are discussed. The effectiveness of the proposed power converter is evaluated and compared with the hard switching PWM DC‐DC converter from an experimental point of view, and the comparative electromagnetic conduction and radiation noise characteristics of both DC‐DC power converter circuits are also depicted. © 2005 Wiley Periodicals, Inc. Electr Eng Jpn, 152(3): 74–81, 2005; Published online in Wiley InterScience ( www.interscience.wiley.com ). DOI 10.1002/eej.20081     

A high‐efficiency isolated DC/DC converter using series connection on the secondary side

This paper proposes a new circuit topology for a high‐efficiency isolated DC/DC converter using series compensation. The proposed converter consists of a high‐efficiency resonance half‐bridge converter and a series converter. The series converter regulates the output voltage and provides only the differential voltage between the input voltage and output voltage. Therefore, the circuit achieves high efficiency when the input voltage is almost equal to the output voltage, because then only the resonance converter will operate. In this paper, the approach employed to achieve high efficiency by using the proposed series compensation method is introduced. In addition, the fundamental operation and the method of designing the proposed circuit are described. The suitability of the proposed circuit was confirmed by performing experiment and loss analysis, and the maximum efficiency achieved was 96.2%. © 2012 Wiley Periodicals, Inc. Electr Eng Jpn, 182(2): 42–52, 2013; Published online in Wiley Online Library ( wileyonlinelibrary.com ). DOI 10.1002/eej.22330     

Dynamic joint model of capacitive charge pumps and on‐chip photovoltaic cells for CMOS micro‐energy harvesting

On‐chip energy harvesting by means of integrated photovoltaic cells in standard CMOS technology can be successfully used to recharge or power‐up integrated circuits with the use of charge pumps for voltage boosting. In this paper, a tool to facilitate the design of such structures is proposed consisting of an accurate model of the joint dynamics of the micro‐photovoltaic cell and a capacitive DC/DC converter in the slow‐switching limit regime. The model takes into account both the top and bottom parasitic capacitances of the flying capacitors. We assume a classical model for the photodiode whose photogenerated current is extracted from device‐level simulations. The joint model is verified by circuit‐level simulations achieving high accuracy and computation time savings of up to 1700×. The joint model shows that the voltage generated by an integrated photovoltaic cell connected to a capacitive DC/DC converter is not constant even under constant illumination. This phenomenon can only be reproduced through the joint model and failing to take it into account results in an error in the estimation of the time needed by the DC/DC converter to reach a given output voltage. We also demonstrate that the maximum output voltage reached by a DC/DC converter in the slow‐switching limit regime when a photovoltaic cell is used as energy transducer depends on the switching frequency. Finally, the applicability of the model is illustrated through the optimization of time response and charge efficiency for the Dickson, Fibonacci, and exponential topologies in the case of implantable devices. Copyright © 2016 John Wiley & Sons, Ltd.     

A bidirectional DC/DC converter charge/discharge controller for solar energy illumination system integrating synchronous rectification SEPIC converter and active clamp flyback converter

This paper presents a novel bidirectional DC‐to‐DC converter charge/discharge controller for solar energy illumination system. The bidirectional converter architecture integrates the synchronous rectification Single Ended Primary Inductor Converter (SEPIC) converter and an active clamp flyback converter. In addition to fully use the properties of the shared components and compensate for the shortcomings of conventional two‐stage illumination systems, the proposed system has the advantages of soft‐switching, simple structure, and high efficiency. During daytime, a SEPIC converter with synchronous rectification function was used to charge the lead acid battery through three‐stage charging and maximum power point tracking. At night, the battery discharges, driving and dimming high‐brightness LEDs using the active clamp flyback converter. Finally, a solar energy illumination system with both a 160 W charge/discharge controller and an 80 W LED driver was implemented to verify the feasibility and practicality of the proposed system. Copyright © 2015 John Wiley & Sons, Ltd.     

Analysis and implementation of a power management unit with a multiratio switched capacitor DC–DC converter for a supercapacitor power supply

An energy‐harvesting system requires an energy‐storing device to store the energy retrieved from the surrounding environment. Rechargeable batteries are commonly used to store this energy; however, because of the limited number of charge/discharge cycles, they need to be periodically replaced. A supercapacitor, which has, ideally, a limitless number of charge/discharge cycles, avoids this problem. In this case, it is required for the power management unit to produce a constant output voltage as the supercapacitor discharges. This paper presents a system with a multiratio switched capacitor DC–DC converter, in a 130‐nm technology, with a maximum output power of 2 mW, a maximum efficiency of 79.63% and a maximum output ripple, in the steady state, of 23 mV for an input voltage range of 2.3–0.87 V. The proposed converter has four operation states, to maximize its efficiency, that correspond to the conversion ratios of 1/2, 2/3, 1/1 and 3/2. Its clock frequency is automatically adjusted to produce a stable output voltage of 1 V. These features are implemented through two distinct controller circuits that use two asynchronous time machines to dynamically adjust the clock frequency and to select the active state of the converter. All the theoretical expressions as well as the behaviour of the whole system were verified by using electrical simulations. Copyright © 2016 John Wiley & Sons, Ltd.     

A switch‐mode boost DC–DC converter for IR‐drop compensation of charging cable

A switch‐mode boost DC–DC converter has been developed to compensate for the IR‐drop because of the finite resistance of a charging cable. The boost ratio of the DC–DC converter is adaptively controlled by an IR‐drop sensing circuit to provide the required voltage level to a battery charger regardless of the cable resistance. Implemented in a 0.18 µm BCDMOS process, the IR‐drop compensating switch‐mode boost DC–DC converter occupies 6.2 mm² active area and shows the 93.2% peak efficiency. The proposed IR‐drop compensating boost converter can be applied to compensate for the IR‐drop of any type of charging cables. Copyright © 2014 John Wiley & Sons, Ltd.     

Efficient power management circuit for biomass-based energy harvesting system

This paper presents an efficient power management circuit (PMC) for microbial fuel cells (MFCs). The proposed PMC has been designed with off-the-shelf components including a charge pump, a supercapacitor, and two boost converters. Both the charge pump and one of the boost converter are directly connected to the MFC, that is, connected in parallel to the MFC. The reason for that using the charge pump can extend the variety of PMC input power, and deploying the boost converter can extract more power from the MFC. Thus, the proposed PMC can test the input power range from 11.25 μW to 1.6 mW. Also, the proposed PMC can extract 6× higher power from the MFC as compared with the charge pump alone. A wide dynamic load range from 10.89 μW to 108.9 mW can be supported by the proposed PMC. Measured results show that the interval to provide power supply to the load by the proposed PMC is 9.2× shorter than that achieved by the charge pump alone. Also, the proposed PMC enhances the end-to-end efficiency by range from 10× to 14.35× with varying loads. The proposed PMC achieves the end-to-end peak efficiency of 73.185%. The proposed PMC can achieve a low charging time, a wide dynamic load range, and a regulated output voltage compared with prior works.     

Non‐invasive chaos control of DC–DC converter and its optimization

The frequency‐domain‐based realization condition related to a novel non‐invasive chaos control is presented in this paper. According to the common piecewise‐linear characteristics of PWM‐controlled DC–DC converter system, a general expression for its Jacobian matrix is derived for optimizing the control parameters of the proposed non‐invasive chaos control. The relevant simulation and experiment results about the application of the chaos control to a voltage‐mode Buck converter are given, which confirm the feasibility of the parameter‐optimization method and the validity of the proposed non‐invasive chaos control. Copyright © 2010 John Wiley & Sons, Ltd.