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Luca Magnelli Francesco A. Amoroso Felice Crupi Gregorio Cappuccino Giuseppe Iannaccone 《International Journal of Circuit Theory and Applications》2014,42(9):967-977
This work focuses on the subthreshold design of ultra low‐voltage low‐power operational amplifiers. A well‐defined procedure for the systematic design of subthreshold operational amplifiers (op‐amps) is introduced. The design of a 0.5‐V two‐stage Miller‐compensated amplifier fabricated with a 0.18‐µm complementary metal–oxide–semiconductor process is presented. The op‐amp operates with all transistors in subthreshold region and achieves a DC gain of 70 dB and a gain–bandwidth product of 18 kHz, dissipating just 75 nW. The active area of the chip is ≈0.057 mm2. Experimental results demonstrate that well‐designed subthreshold op‐amps are a very attractive solution to implement sub‐1‐V energy‐efficient applications for modern portable electronic systems. A comparative analysis with low‐voltage, low‐power op‐amp designs available in the literature highlights that subthreshold op‐amps designed according to the proposed design procedure achieve a better trade‐off among speed, power, and load capacitance. Copyright © 2013 John Wiley & Sons, Ltd. 相似文献
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Afreen Azhari Takamaro Kikkawa 《International Journal of Circuit Theory and Applications》2019,47(8):1293-1301
An ultra-wideband 2- to 12-GHz transmit/receive (T/R) double-pole–eight-throw (DP8T) switching matrix is developed with a 65-nm complementary metal oxide semiconductor (CMOS) process for a radar-based breast cancer detection system. The measured average insertion losses are 5.2, 7, and 10.6 dB at 2, 6, and 12 GHz, respectively, with input and output matching bandwidths of 2 to 12 GHz and a third-order input intercept point (IIP3) of 31 dBm at 8 GHz. The power consumption is less than 1 mW for a 1.2-V power supply. To the best of the authors' knowledge, this is the first reported DP8T CMOS switching matrix to replace the conventional mechanical switch to control a portable radar antenna. 相似文献
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射频功放在放大信号时的非线性使信号放大后产生失真,严重影响通信系统性能。主要针对射频功率放大器的三阶互调失真优化,提出了一种新型的模拟预失真器。融合了完全匹配的IMD3产生器、二次消基频概念,有效地消除了IMD3产生器的基频,降低了基频对三次谐波的干扰。电路设计引入了功率推动概念和双环结构,大大优化了L频段GaN功放的IMD3分量,提升功放线性度。使用ADS2009U1软件仿真实验证明,在950 MHz单音测试下,系统整体效率可达52.1%。在945 MHz和955 MHz双音测试下,IMD3增加了15 dB。该预失真器实现了在低效率损耗下对线性度的优化。 相似文献
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Michele Caselli Matteo Tonelli Andrea Boni 《International Journal of Circuit Theory and Applications》2019,47(7):1086-1104
Radio-frequency (RF) energy harvesting must cope with the limited availability and high variability of the energy source. In this paper, the available RF power in three typical environments (urban, semi-urban, and rural) is investigated. Measurements show that in the surveyed urban and semi-urban environments, an average input power above −22 and −29 dBm, respectively, is available in the [700, 1,000] MHz band. A mathematical model of the interface between the RF rectifier and the DC-DC converter is provided. The analysis demonstrates that the energy can be efficiently transferred to the external accumulator coupling the rectifier with a strobed, input control DC-DC converter. Based on the measurements and the analysis, an RF harvester architecture has been designed in 65 nm Complementary Metal-Oxide Semiconductor (CMOS) technology to operate over the [−40, 85]oC temperature and the [1.1, 2.5] V battery voltage ranges. The input control strategy adopted for the converter allows the adaptation of the harvester to the available RF power and enables a real maximum power point tracking (MPPT). Post-layout simulation of the harvester, recharging a large capacitor, precharged at 2 V, at 950 MHz of input frequency returned a 33.4% peak efficiency with an input power of 15 μW (−18 dBm). The minimum input power leading to a positive energy balance is −30 dBm with an output voltage of 1.1 V. 相似文献
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Stanislaw Szczepanski Bogdan Pankiewicz Slawomir Koziel Marek Wojcikowski 《International Journal of Circuit Theory and Applications》2015,43(11):1671-1686
A CMOS circuit realization of a highly linear multiple‐output differential operational transconductance amplifier (OTA) has been proposed. The presented approach exploits a differential pair as an input stage with both the gate and the bulk terminals as signal ports. For the proposed OTA, improved linearity is obtained by means of the active‐error feedback loop operating at the bulk terminals of the input stage. SPICE simulations of the OTA show that, for 0.35 µm AMS process, total harmonic distortion at 1.36Vpp is less than 1% with dynamic range equal to 60.1 dB at power consumption of 276 μW from 3.3 V supply. As an example, both single output and dual differential OTAs are used to design third‐order elliptic low‐pass filters. The cut‐off frequency of the filters is 1 MHz. The power consumption of the OTA‐C filter utilizing the dual output differential OTA is reduced to 1.24 mW in comparison to 2.2 mW consumed by the single output differential OTA‐C filter counterpart. Copyright © 2014 John Wiley & Sons, Ltd. 相似文献
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W. Aloisi G. Giustolisi G. Palumbo 《International Journal of Circuit Theory and Applications》2003,31(5):513-528
In this paper, a thorough analysis of a gain‐boosted telescopic amplifier (GBTA) is presented and a systematic design procedure for optimizing its time response will be given. Specifically, the GBTA closed‐loop time response will be analysed in detail and the constraints eliminating the well‐known ‘slow settling component’ found. Subsequently, an optimization strategy based on the comparison between the GBTA time response and the time response of a pure two‐pole amplifier (referred to as the target system) will be described. This strategy allows the designer to develop a GBTA starting from the target system specifications in a simple and systematic way. The proposed procedure has been validated by means of simulations and excellent agreement found between the simulated and the expected results. Copyright © 2003 John Wiley & Sons, Ltd. 相似文献
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Enhancing the performances of recycling folded cascode OpAmp in nanoscale CMOS through voltage supply doubling and design for reliability 
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下载免费PDF全文 Pui‐In Mak Miao Liu Yaohua Zhao Rui P. Martins 《International Journal of Circuit Theory and Applications》2014,42(6):605-619
Current‐oriented operational amplifier (OpAmp) design has been common for its orderly current‐to‐speed tradeoff. However, for high‐precision or high‐linearity applications, increasing the current does not help much, as the supply voltage (VDD) and intrinsic gain of the MOSFETs in ultra‐scaled CMOS technologies are very limited. This paper introduces voltage‐oriented circuit techniques to address such limitations. Specifically, a 2xVDD‐enabled recycling folded cascade (RFC) OpAmp is proposed. It features: (1) current recycling to enhance the effective trans conductance by 4x with no extra power; (2) transistor stacking to boost the output resistance by one to two orders of magnitude; and (3) VDD elevating to enlarge the linear output swing by 4x. Comparing with its 1xVDD RFC and FC counterparts, the proposed solution achieves 20‐dB higher DC gain (i.e. 72.8 dB) in open loop and 20‐dB lower IM3 (i.e., –76.5 dB) in closed loop, under the same power budget of 0.6 mW in a 1‐V General Purpose 65‐nm CMOS process. In many applications, these joint improvements in a single stage are already adequate, being more power efficient (i.e. less current paths), stable (i.e. more phase margin), and compact (i.e. no frequency compensation) than multi‐stage OpAmps. Voltage‐conscious biasing and node‐voltage trajectory check ensure the device reliability in both transient and steady states. No specialized high‐voltage device is necessary. Copyright © 2012 John Wiley & Sons, Ltd. 相似文献
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《IEEJ Transactions on Electrical and Electronic Engineering》2017,12(1):140-146
This paper presents a 60‐GHz power amplifier with on‐chip varactor‐based tunable load‐matching networks and an embedded DC temperature‐sensor‐based power detector. The output power can be monitored by the DC temperature sensor, and load‐matching network can be tuned by regulating the control voltage of the varactors, which can be used for correcting unpredictable process, supply voltage, and temperature (PVT) variations and load mismatch. Measured results show that the small‐signal gain of the CMOS power amplifier is up to 6.5 dB at 52 GHz. The power amplifier achieves 5 dBm output P1dB and 7 dBm saturated output power with 4.5% maximun power added efficiency (PAE) at 1 V control voltage. By sweeping the control voltage of the varactors, the power amplifier can obtain the maximun power gain, which can be used to solve the load mismatch. © 2016 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc. 相似文献
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Antonio J. Lopez‐Martin Jaime Ramirez‐Angulo Ramón G. Carvajal Lucía Acosta 《International Journal of Circuit Theory and Applications》2011,39(9):893-903
A novel CMOS current‐feedback operational amplifier (CFOA) aimed to low‐power applications is proposed. The use of a compact class AB implementation allows high current‐drive capability and simultaneously very low quiescent power consumption. Measurement results of a fabricated prototype show for an inverting configuration a closed‐loop bandwidth of 1 MHz independent of gain setting, and a slew rate of 2V/µs for a load capacitance of 30 pF and a quiescent power consumption of 264µW. Copyright © 2010 John Wiley & Sons, Ltd. 相似文献
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张煜 《国外电子测量技术》2007,26(5):29-31,38
在当前许多电子测试仪器中,ALC环路必不可少,很多ALC环路电路设计都很复杂、电路庞大、设计成本高.本文提出一种ALC环路,具有设计简洁、性价比高的特点.该ALC环路从功能上主要分为调制器(PIN二极管)部分、RF射频信号放大部分、功分检波部分,分别详细地介绍了这几部分的原理和电路.ALC环路的工作频率从250 kHz到1 GHz,输入信号功为 0 dBm±1.5 dB,输出信号功为 13 dBm±1.5 dB. 相似文献
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《International Journal of Circuit Theory and Applications》2017,45(6):790-810
In this paper a low power CMOS potentiostat is presented for energy limited applications such as human implantable sensors. The main focus is on using different techniques to reduce the power consumption at different circuit blocks, especially in the output stage that delivers power to the electrochemical cell. The proposed technique includes the use of a class D amplifier to reduce conduction power dissipation compared with conventional linear methods. Power dissipation has been improved by several other considerations such as elimination of opamp blocks which consume static power, avoiding current sampling stages and using dynamic latched comparators for loop error calculations. Closed loop stability problem and a low power solution to overcome this issue are addressed in the paper. The role of effective parameters such as inductor value, output MOSFET dimensions and clock pulse timing has been investigated and optimization considerations are used to achieve the low power potentiostat. Evaluation results show that a 12.96‐μW potentiostat with 1.03‐μW power dissipation and 89% efficiency is achievable with a linearity of R 2 = 0.998. Copyright © 2016 John Wiley & Sons, Ltd. 相似文献
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S. O. Cannizzaro A. D. Grasso G. Palumbo S. Pennisi 《International Journal of Circuit Theory and Applications》2008,36(7):825-837
A frequency compensation technique for three‐stage amplifiers is introduced. The proposed solution exploits only one Miller capacitor and a resistor in the compensation network. The straightness of the technique is used to design, using a standard CMOS 0.35‐µm process, a 1.5‐V OTA driving a 150‐pF load capacitor. The dc consumption is about 14µA at DC and a 1.8‐MHz gain–bandwidth product is obtained, providing significant improvement in both (MHzpF)/mA and ((V/µs)pF)/mA performance parameters. Copyright © 2007 John Wiley & Sons, Ltd. 相似文献
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Jie Jin Chunhua Wang Jingru Sun Sichun Du 《International Journal of Circuit Theory and Applications》2015,43(11):1794-1800
This letter describes a low‐voltage low‐power (LV‐LP) 2.4‐GHz mixer for Industrial, Scientific and Medical (ISM) band wireless applications. The approach is based on a two‐stage amplifier, and the Gilbert switch stage is inserted between the two amplifier stages. The proposed amplifier‐based mixer delivers a remarkable conversion gain of 13 dB with a local oscillator (LO) power of 7 dBm, while consuming only 1.05‐mW DC power from a 0.8‐V supply voltage. The input‐referred third‐order intercept point (IIP3) of the mixer is 3.82 dBm, and the chip area is only 0.429 mm2. The results indicate that this mixer is suitable for the low‐voltage low‐power applications. Copyright © 2014 John Wiley & Sons, Ltd. 相似文献
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无论是特高压交流输电技术的试验研究还是特高压交流设备的绝缘考核都需要特高压交流试验电源,而目前对特高压交流试验电源的探讨很少,因此提出了一种基于DSP控制的新型调频谐振式特高压交流试验电源。它采用运算速度快、处理能力强的TMS320F2407型DSP作为控制器核心芯片,在分析其结构与工作原理的基础上,重点研究了其功率放大电路、保护电路、智能控制系统及光纤反馈测量电路,并以放大电路的输入功率、最大输出功率、放大效率、三极管总的最大损耗作为衡量放大电路的标准。同时还提出适合该电源系统的调频、调压闭环智能控制策略。试验结果表明该特高压交流试验电源输出波形接近标准正弦波、畸变小,电压等级可满足特高压交流试验的需求,整个装置还具有体积小、重量轻、便于运输等优点。 相似文献
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250K～1GHz线性功放及其稳幅电路的设计 总被引：2，自引：0，他引：2
王尽秋 《国外电子测量技术》2005,24(4):15-17
在当前的许多电子产品中,功率放大器必不可少。本文介绍了一款应用于电子测试仪器中的宽带线性功率放大器及其稳幅电路的设计。放大器的工作频率从250ｋＨｚ到1ＧＨｚ,输入信号功率为0ｄＢｍ±1.5ｄＢ,输出功率为18ｄＢｍ±2ｄＢ。该功放系统从功能上主要分为电调衰减部分、ＲＦ信号放大部分、自动增益控制部分(检波和直流放大),本文分别详细介绍了这几个部分的原理和电路。 相似文献
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基于现在射频电路的设计水平,TD-SCDMA终端要求最大程度的保证信号的完整性。提出了一种用于TD-SCDMA终端综测仪的射频接收系统,基于TD-SCDMA标准,射频频率为1800~2400 MHz,在910 kHz的分辨率带宽下,系统要求接收最小-80 dBm的信号,动态范围为60 dBm,中频频率为91~101 MHz。具有结构简单、易于仿真、成本较低等优点。实际测试结果与利用ADS软件仿真结果基本一致,性能指标能够达到设计要求。 相似文献
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电流型功率放大器工作在高电压、大电流情况下,因此保护电路更为重要.分析了功率放大器中功率管容易损坏的情况,研制了避免功放损坏的电路.死区硬件产生电路可以防止因程序故障造成的死区时间减小而导致桥臂短路损坏;当出现上下桥臂同时导通的信号时,防误导通电路可以中止功率驱动芯片IR2110的信号输出;当出现干扰信号导致全桥电路同侧导通时,短路保护电路中止功率驱动芯片的输出,同时还具有过流保护的功能.经过实验验证,这些电路在实际应用中效果良好. 相似文献