A power‐area‐efficient, 3‐band, 2‐RX MIMO,TD‐LTE receiver with direct‐coupled ADC

In this work, a power‐area‐efficient, 3‐band, 2‐RX MIMO, and TD‐LTE (backward compatible with the HSPA+, HSUPA, HSDPA, and TD‐SCDMA) CMOS receiver is presented and implemented in 0.13‐μm CMOS technology. The continuous‐time delta‐sigma A/D converters (CT ?Σ ADCs) are directly coupled to the outputs of the transimpedance amplifiers, eliminating the need of analog anti‐aliasing filters between RX front‐end and ADCs in conventional structures. The strong adjacent channel interference without low‐pass filter attenuation is handled by proper gain control. A low‐power small‐area solution for excess loop delay compensation is implemented in the CT ?Σ ADC. At 20 MHz bandwidth, the CT ?Σ ADC achieves 66 dB dynamic range and 3.5 dB RX chip noise figure is measured. A maximum of 2.4 dB signal‐to‐noise ratio degradation is measured in all the adjacent channel selectivity (ACS) and blocking tests, demonstrating the effectiveness of the strategy against the low‐pass filter removal from the conventional architecture. The receiver dissipates a maximum of 171 mW at 2‐RX MIMO mode. To our best knowledge, it is the first research paper on the design of fully integrated commercial TD‐LTE receiver. Copyright © 2014 John Wiley & Sons, Ltd.     

A low‐power,area‐efficient multichannel receiver for micro MRI

A new integrated, low‐noise, low‐power, and area‐efficient multichannel receiver for magnetic resonance imaging (MRI) is described. The proposed receiver presents an alternative technique to overcome the use of multiple receiver front‐ends in parallel MRI. The receiver consists of three main stages: low‐noise pre‐amplifier, quadrature down‐converter, and a band pass filter (BPF). These components are used to receive the nuclear magnetic resonance signals from a 3 × 3 array of micro coils. These signals are combined using frequency domain multiplexing (FDM) method in the pre‐amplifier and BPF stages, then amplified and filtered to remove any out‐of‐band noise before providing it to an analog‐to‐digital converter at the low intermediate frequency stage. The receiver is designed using a 90 nm CMOS technology to operate at the main B₀ magnetic field of 9.4 T, which corresponds to 400 MHz. The receiver has an input referred noise voltage of 1.1 nV/√Hz, a total voltage gain of 87 dB, a power consumption of 69 mA from a 1 V supply voltage, and an area of 305 µm × 530 µm including the reference current and bias voltage circuits. Copyright © 2013 John Wiley & Sons, Ltd.     

High‐tuning‐range CMOS band‐pass IF filter based on a low‐Q cascaded biquad optimization technique

A design procedure for high‐order continuous‐time intermediate‐frequency band‐pass filters based on the cascade of low‐Q biquadratic cells is presented. The approach is well suited for integrated‐circuit fabrication, as it takes into account the maximum capacitance spread dictated by the available technology and maximum acceptable sensitivity to component variations. A trade‐off between noise and maximum linear range is also met. A novel, wide‐tuning‐range transconductor topology is also described. Based on these results, a 10‐pole band‐pass filter for a code division multiple‐access satellite receiver has been designed and tested. The filter provides tunable center frequency (f₀) from 10 to 70 MHz and exhibits a 28‐MHz bandwidth around f₀ = 70 MHz with more than 39‐dB attenuation at f₀/2 and 2f₀. Third‐order harmonic rejection is higher than 60 dB for a 1‐Vpp 70‐MHz input, and equivalent output noise is lower than 1 mV_rms. The circuit is fabricated in a 0.25‐µm complementary metal oxide semiconductor process, and the core consumes 12 mA from a 2.5‐V supply, offering the best current/pole ratio figure. The die area resulted to be 0.9 × 1.1 mm². Copyright © 2014 John Wiley & Sons, Ltd.     

A reconfigurable high ultimate rejection inductorless band‐pass filter by the use of N‐path passive mixers

In this paper, a band‐pass filter with a tunable bandwidth and the center frequency is introduced, which employs N‐path and N × M‐path passive mixer structures, for multiband multistandard wireless receivers. The center frequency of the proposed filter is tunable from 0.1 to 1 GHz, while its bandwidth is also adjustable from 6% to 34% of the center frequency at 100 MHz. The passband ripple is reduced by applying a Miller compensation technique, resulting in a worst‐case ripple of only 1.6 dB over the entire tuning range. An additional eight‐path filter is also utilized at the input of the circuit, which highly improves the out‐of‐band rejection of the filter as well as its out‐of‐band linearity. The noise figure and the input return loss are, respectively, better than 5 and 10 dB, and depending on the desired center frequency, the total power consumption of the proposed filter varies from 41 to 70 mW.     

Harmonic fold back reduction at the N‐path filters

In this paper, a method is proposed to reduce harmonic fold back (HFB) problem of N‐path filters, without increasing the input reference clock (f_CLK ) frequency. The HFB at the N‐path filter is analyzed, and simple expressions are extracted to model this problem. Using the results of the analysis, an M‐of‐N‐path filter has been proposed that behaves like an M × N‐path filter in terms of HFB problem; however, the f_CLK frequency of this structure is the same as an N‐path filter. To demonstrate the feasibility of the proposed idea, a 3‐of‐4‐path filter is designed, and its characteristics are compared with 4‐path and 12‐path filters by simulation. Impacts of different non‐idealities like clock‐phase error, mismatch, and parasitic capacitance are investigated. The transistor‐level implementation of this filter is performed in 0.18 µm Complementary Metal Oxide Semiconductor (CMOS) technology. The simulation results show that the filter has the pass‐band gain of 17 dB, tuning range of 0.2–1.2 GHz, −3 dB bandwidth of 25 MHz, quality factor of 8–48, 18 dB out‐of‐band rejection, 16 dB rejection of the third harmonic of switching frequency (f_s ), and the noise figure of 4.35 dB (using ideal G_m cells) and 6.95 dB (for practical G_m cells). The strongest harmonic folding to the filter pass‐band occurs around 11f_s with the attenuation of 23.8 dB. Each G_m cell draws about 12.4 mA from 1.8 V supply, and the out‐of‐band IIP3 and P _{1 dB,CP} are 17 and 4 dBm, respectively. Copyright © 2016 John Wiley & Sons, Ltd.     

A 0.8‐V supply bulk‐driven operational transconductance amplifier and Gm‐C filter in 0.18 µm CMOS process

A low voltage bulk‐driven operational transconductance amplifier (OTA) and its application to implement a tunable Gm‐C filter are presented. The linearity of the proposed OTA is achieved by nonlinear terms cancelation technique, using two paralleled differential topologies with opposite signs in the third‐order harmonic distortion term of the differential output current. The proposed OTA uses 0.8 V supply voltage and consumes 31.2 μW. The proposed OTA shows a total harmonic distortion of better than ?40 dB over the tuning range of the transconductance, by applying 800 mV_ppd sine wave input signal with 1 MHz frequency. The OTA has been used to implement a third‐order low‐pass Gm‐C filter, which can be used for wireless sensor network applications. The filter can operate as the channel select filter and variable gain amplifier, simultaneously. The gain of the filter can be tuned from ?1 to 23 dB, which results in power consumptions of 187.2 to 450.6 μW, respectively. The proposed OTA and filter have been simulated in a 0.18 µm CMOS technology. Simulations of process corners and temperature variations are also included in the paper. Copyright © 2014 John Wiley & Sons, Ltd.     

A programmable analog baseband filter with DC offset reduction using servo loop feedback

This paper presents a programmable analog baseband filter with direct current (DC) offset cancelling, using the standard complementary metal‐oxide‐semiconductor process. The servo loop feedback topology is adopted to reject in‐band DC offset at each stage of the receiving system. Furthermore, the proposed back‐to‐back diode‐connected configuration forms an ultrahigh pseudo resistor, which is applied in the feedback path of the integrator to obtain an ultralow cut‐off frequency (<1 Hz) for the high‐pass response. Therefore, low‐frequency application is possible for simultaneously in‐band DC offset and out‐band interference suppression. A servo loop feedback system with a pseudo resistor is used in the analog baseband filter to verify the concept. The chip is fabricated by using the TSMC 0.13‐um complementary metal‐oxide‐semiconductor process and consumes 43.8 mA from a 1.2 V DC supply voltage. The measured gain variation is from 65.6 to ?3.3 dB with a resolution of 1 dB at a bandwidth of 5 MHz. The bandwidth is adjustable from 1.75 to 10 MHz.     

Single transistor high linearity and wide dynamic range active inductor

In this paper, an active inductor (AI) with high linearity and high dynamic range, including a minimum number of components, is presented. The AI is composed by a single transistor, and by a passive compensation network; the latter allows the control of the values of both the inductance and the series resistance. In order to show the feasibility of the proposed AI for filter applications, a prototype board on a TLX8 substrate with a first‐order active band‐pass filter has been fabricated and tested. The filter has a center frequency of 2470 MHz (useful for Bluetooth applications) and a measured noise figure (NF) of 9 dB with a ?5 dBm P₁dB compression point, and a 75 dB dynamic range. Copyright © 2013 John Wiley & Sons, Ltd.     

RF and microwave high‐Q floating active inductor design and implementation

In this paper, a high‐Q floating active inductor (FAI), suitable for RF and microwave applications, is presented. The proposed FAI is based on two cascaded pairs of highly linear capacitance gyrators, which provide a symmetric and reciprocal structure. The proposed FAI shows fully symmetrical two‐port characteristics, high quality factor and high linearity. As a feasibility demonstration, a prototype of the designed FAI has been fabricated, together with an LC series band‐pass filter. At the operating frequency, the real part of the impedance of the equivalent FAI is very low (Req = 0.0039 Ω), providing a very high quality factor. The filter has a central frequency of 430 MHz and a ?3 dB bandwidth of about 9 MHz. Copyright © 2014 John Wiley & Sons, Ltd.     

Reconfigurable narrowband microwave band‐pass filter

A method is proposed for the design of band‐pass filters with tunable centre frequency and bandwidth without the need for adjusting the inter‐resonator couplings. This is achieved by cascading a quasi low‐pass filter and a quasi high‐pass filter, while minimizing interaction between the filters without the need for an isolator between the filters. Simulated results are presented. Copyright © 2013 John Wiley & Sons, Ltd.     

Proposal of over 100‐GHz band waveguide switch

A filter bank consisting of switches and band‐pass filters is one method for configuring a spectrum analyzer preselector. A long‐life switch with high isolation is key to this development. We propose a novel horizontal‐moving waveguide switch designed for easy addition of ports compared to commercial rotating switches. The switch has a small gap between the fixed and moving parts with the gap surrounded by chokes. This configuration offers high isolation and long life. It also reduces the size of the filter bank. This paper describes 2 proposed switch prototypes for frequency ranges from 90 to 140 GHz and from 255 to 315 GHz. The measured switch isolation is better than 50 dB and the insertion loss is less than 3 dB for both prototypes.     

Relaxing the maximum dc input amplitude vs. consumption trade‐off in differential‐input band‐pass biquad filters

This paper shows that an important part of the power consumption of a biquad band‐pass filter is associated with the feedback loop that fixes the high‐pass frequency and blocks the direct current (dc) input signals. The dc input amplitude that can be blocked is related to the maximum output current that one of the transconductors can provide, hence impacting on the required consumption through this effect. Then, a technique that efficiently blocks the dc input signal and fixes the high‐pass frequency is introduced and analyzed in depth. Moreover, an architecture for ultra‐low‐power differential‐input biquads is fully presented. The proposed architecture enables lowering the power consumption or blocking higher levels of dc input without jeopardizing the power consumption. Results show that the proposed architecture, compared with a traditional one, presents a 30% reduction in power consumption and more than doubles the dc input that can be blocked. Copyright © 2016 John Wiley & Sons, Ltd.     

Programmable feedforward linearized CMOS OTA for fully differential continuous‐time filter design

In this paper, a feedforward linearization method for programmable CMOS operational transconductance amplifier (OTA) is described. The proposed circuit technique is developed using simple source‐coupled differential pair transconductors, a feedback‐loop amplifier for self‐adjusting transcoductance (g_m) and a linear reference resistor (R). As a result, an efficient linearization of a transfer characteristic of the OTA is obtained. SPICE simulations show that for 0.35µm AMS CMOS process with a single +3V power supply, total harmonic distortion at 1 V_pp and temperature range from ?30 to +90°C is less than ?49.3 dB in comparison with ?35.8 dB without linearization. Moreover, the input voltage range of linear operation is increased. Power consumption of the linearized OTA circuit is 0.86 mW. Finally, the OTA is used to design a third‐order elliptic low‐pass filter in high‐frequency range. The cut‐off frequency of the operational transconductance amplifier‐capacitor (OTA‐C) filter is tunable in the range of 322.6 kHz–10 MHz using the feedforward linearized OTAs with the digitally programmable current mirrors. Copyright © 2009 John Wiley & Sons, Ltd.     

Analytical synthesis of voltage‐mode even/odd‐nth‐order differential difference current conveyor and fully differential current conveyor II‐grounded resistor and capacitor universal filter structures

A complete definition of an odd/even‐nth‐order notch or band‐reject filter transfer function is presented. Based on the differences between the input voltage and (i) an nth‐order high‐pass; (ii) a traditional nth‐order notch; and (iii) an nth‐order all‐pass filtering transfer function, a systematic method has been proposed to derive a universal filter structure that can realize voltage‐mode odd/even‐nth‐order low‐pass, band‐pass, high‐pass, all‐pass and traditional notch filters. The intrinsic capability of voltage‐mode addition and subtraction of the two active elements, differential difference current conveyors and fully differential current conveyors, is used to advantage in the aforementioned synthesis procedure. Based upon the definition of an nth‐order notch or band‐reject filter transfer function proposed in this paper, the aforementioned universal one has been further extended to the newly defined nth‐order band rejection filter. The voltage and current tracking errors of the two active elements are compensated by varying the resistances of the proposed filter. Filtering feasibility, stability, component sensitivities, linear and dynamic ranges, power consumption, and noise are simulated using H‐Spice with 0.35 µm process. Compared to some of the recently reported universal biquads, the new one is shown to enjoy the lowest component sensitivities and the best output accuracy for all‐pass signals. Moreover, Monte Carlo and two‐tone tests for intermodulation linearity simulations are also investigated. Copyright © 2014 John Wiley & Sons, Ltd.     

基于CFA的六阶切比雪夫有源低通滤波器设计与仿真

结合工程应用中对滤波器的需求,对基于CFA的有源低通滤波器的设计方法进行研究。选用一种典型的电流反馈型运算放大器,在对VCVS滤波电路传递函数分析的基础上,设计了基于CFA的六阶切比雪夫有源低通滤波器,并阐述了根据滤波器性能参数及截止频率确定电路参数的方法。软件仿真结果表明,该有源低通滤波器截止频率约为15 MHz,通带增益为39.796 dB,通带起伏为3.18 dB,过渡带衰减速率为-47.992 dB/倍频,滤波器性能指标与理论一致。该数据表明设计方法有效可行,可为其他有源滤波器的设计提供参考价值。     

A simulation study of high‐order CMOS hyperbolic‐sine filters

This paper advances the field of externally linear–internally nonlinear (ELIN) filters by introducing a synthesis method that enables the design of high‐order class‐AB sinh filters by means of complementary metal–oxide semiconductor (CMOS) weak‐inversion sinh integrators comprising only one type of devices in their translinear loops. The proposed transistor‐level synthesis approach is demonstrated through the examples of (1) a biquadratic and (2) a fifth‐order filter, and their simulated performance is studied. The biquadratic filter achieves a dynamic range of 94 dB and has a tunable quality factor Q up to the value of 8, whereas its natural frequency can be tuned for four orders of magnitude. Its static power consumption amounts to 6.2 μW for Q = 1 and f_o = 2 kHz. The fifth‐order Chebyshev sinh CMOS filter with a cut‐off frequency of 100 Hz, a pass band ripple of 1 dB, and a power consumption of ~300 nW is compared head‐to‐head with its pseudo‐differential class‐AB CMOS log domain counterpart. The sinh filter achieves similar or better signal‐to‐noise ratio (SNR) and signal‐to‐noise‐plus‐distortion ratio (SNDR) performances with half the capacitor area but at the expense of higher power consumption from the same power supply level. All three presented filter topologies are novel. Cadence design framework simulations have been performed using the commercially available 0.35 µm AMS (austriamicrosystems) process parameters. Copyright © 2013 John Wiley & Sons, Ltd.     

Analytical synthesis and comparison of voltage‐mode Nth‐order OTA‐C universal filter structures

Complementary single‐ended‐input operational transconductance amplifier (OTA)‐based filter structures are introduced in this paper. Through two analytical synthesis methods and two transformations, one of which is to convert a differential‐input OTA to two complementary single‐ended‐input OTAs, and the other to convert a single‐ended‐input OTA and grounded capacitor‐based one to a fully differential OTA‐based one, four distinct kinds of voltage‐mode nth‐order OTA‐C universal filter structures are proposed. TSMC H‐Spice simulations with 0.35µm process validate that the new complementary single‐ended‐input OTA‐based one holds the superiority in output precision, dynamic and linear ranges than other kinds of filter structures. Moreover, the new voltage‐mode band‐pass, band‐reject and all‐pass (except the fully differential one) biquad structures, all enjoy very low sensitivities. Both direct sixth‐order universal filter structures and their equivalent three biquad stage ones are also simulated and validated that the former is not absolutely larger in sensitivity than the latter. Finally, a very sharp increment of the transconductance of an OTA is discovered as the operating frequency is very high and leads to a modified frequency‐dependent transconductance. Copyright © 2010 John Wiley & Sons, Ltd.     

Microstrip bandpass filter design using split‐path method and optimized curvature corrections

Bandpass filters with wide pass‐band are an essential requirement in various equipments of satellite and defence communication sectors. Here a method of split‐path interactions is proposed to approximately predict the resonant frequency and topology of bandpass filters which otherwise fall under the category of heuristic designs. Curved transmission lines are often required to make filter structures physically compact; however, curvature effects create errors in the theoretical (design) prediction of resonant or central frequencies for bandpass filter design. Earlier propositions on curvature corrections had been considerably precise, but recent design standards demand even higher accuracies. The prime feature of this work is the use of a meta‐heuristic optimization (i.e. Particle Swarm Optimization) technique in curvature corrections for the first time which brings accuracies of over 99% in the corrected results. The split paths used in this design are suitably curved, with the proposed optimized curvature correction technique, so as to attain a compact size of the filter. The resulting filter has a low insertion loss of around −1.00 dB and a sharp stopband cut‐off. Fabrication was done on a FR4 microstrip substrate with a good agreement between measured and simulated results. Copyright © 2015 John Wiley & Sons, Ltd.     

Explicit design formulas for current‐mode leap‐frog OTA‐C filters and 300 MHz CMOS seventh‐order linear phase filter

The leap‐frog (LF) configuration is an important structure in analogue filter design. Voltage‐mode LF OTA‐C filters have recently been studied in the literature; however, general explicit formulas do not exist for current‐mode LF OTA‐C filters and there is also need for current‐mode LF‐based OTA‐C structures for realization of arbitrary transmission zeros. Three current‐mode OTA‐C structures are presented, including the basic LF structure and LF filters with an input distributor or an output summer. They can realize all‐pole characteristics and functions with arbitrary transmission zeros. Explicit design formulas are derived directly from these structures for the synthesis of, respectively, all‐pole and arbitrary zero filter characteristics of up to the sixth order. The filter structures are regular and the design formulas are straightforward to use. As an illustrative example, a 300 MHz seventh‐order linear phase low‐pass filter with zeros is presented. The filter is implemented using a fully differential linear operational transconductance amplifier (OTA) based on a source degeneration topology. Simulations in a standard TSMC 0.18µm CMOS process with 2.5 V power supply have shown that the cutoff frequency of the filter ranges from 260 to 320 MHz, group delay ripple is about 4.5% over the whole tuning range, noise of the filter is 420nA/√Hz, dynamic range is 66 dB and power consumption is 200 mW. Copyright © 2008 John Wiley & Sons, Ltd.