Innovative design methodologies in quantum‐dot cellular automata

Current transistor‐based IC fabrication technology faces many trivial issues such as those of excess power dissipation, expensive fabrication and short channel effects at very low device size [1]. Quantum‐dot cellular automata (QCA)‐based digital electronics on the other hand provide scope for further development in the future by shrinking the device size. Current QCA logic circuits are based on logic synthesis using Inverters and (three or five input) Majority Gates. In this paper, a new design methodology has been described that can be used to create circuits with even greater device substrate densities than what are currently achieved in existing QCA designs. Based on the proposed methodology, a new QCA inverter is proposed. It is further tested through simulations on QCA Designer. Through the simulations, it is subsequently proved to be much more reliable and robust than the presently used common QCA inverter(s). In the second section of this paper, simple QCA circuits such as ring oscillators using odd number of inverters in daisy chains are described and designed using the proposed inverter design. Copyright © 2013 John Wiley & Sons, Ltd.     

A comparative analysis and design of quantum‐dot cellular automata memory cell architecture

Quantum‐dot cellular automata (QCA) nanotechnology is considered as the best candidate for memory system owing to its dense packages and low power consumption. This paper analyzes the drawbacks of the previous QCA memory architectures and improves memory cell that exploits regular clock zone layout by employing two new clocking signals and a compact Read/Write circuit. The proposed layout is verified with the modified QCADesigner simulator and is analyzed by considering the noise effect. This design, occupying only a fraction of the area compared with the previous memory design, has superior performance. It is shown that the clock circuitry is very regular, helping manufacturability for physical implementation. Comparisons show that Read/Write latency of the proposed design is mitigated, the overall cell number, control cell and layout area are reduced (100%), and its performance against random charge noise is presented to be better. Copyright © 2010 John Wiley & Sons, Ltd.     

Design and simulation of modular 2n to 1 quantum‐dot cellular automata (QCA) multiplexers

In this paper a novel design of a quantum‐dot cellular automata (QCA) 2 to 1 multiplexer is presented. The QCA circuit is simulated and its operation is analyzed. A modular design and simulation methodology is developed, which can be used to design 2ⁿ to 1 QCA multiplexers using the 2 to 1 QCA multiplexer as a building block. The design methodology is formulated in order to increase the circuit stability. Copyright © 2009 John Wiley & Sons, Ltd.     

Novel quantum‐dot cellular automata implementation of flip‐flop and phase‐frequency detector based on nand‐nor‐inverter gates

CMOS technology faces fundamental challenges such as frequency and power consumption due to the impossibility of further reducing dimensions. For these reasons, researchers have been thinking replacement of this technology with other technologies such as quantum‐dot cellular automata (QCA) technology. Many studies have been done to design digital circuits using QCA technology. Phase‐frequency detector (PFD) is one of the main blocks in electrical and communication circuits. In this paper, a novel structure for PFDs in QCA technology is proposed. In the proposed design, the novel D flip‐flop (D‐FF) with reset ability is used. The D‐FF is designed by the proposed D latch which is based on nand‐nor‐inverter (NNI) and an inverter gate. This proposed D latch has 22 cells and 0.5 clock cycle latency and 0.018‐μm² area. The inverter gate of the D‐FF has output signal with high polarization level and lower area than previous inverters, and the NNI gate of the D‐FF is a universal gate. The proposed PFD has 141 cells, 0.17‐μm² occupied area, and two clock cycle latency that is smaller compared with PFD and is based on common inverter and majority gates.     

Design of efficient QCA multiplexers

A new methodology to realize efficient multiplexers using quantum‐dot cellular automata (QCA) is presented in this paper. The novel designs here demonstrated fully exploit the intrinsic logic capabilities of the basic building block in the QCA domain: the Majority Gate. An efficient logic formulation is derived for the 4:1 multiplexing function that can be recursively applied to the realization of multiplexers with any fan‐in, by adding in the worst‐case path only one level of Majority Gate for each input doubling. A 16:1 multiplexer designed by applying the proposed recursive approach requires less than 1600 cells and consumes only 12 clock phases to complete the operation. Copyright © 2015 John Wiley & Sons, Ltd.     

A simple and accurate dynamical modeling of quantum‐dot semiconductor optical amplifiers

In this article, quantum‐dot semiconductor optical amplifiers (QD‐SOAs) have been modelled using state space method. To derive this model, we have manipulated the rate equation model of the QD‐SOA, where the average values of the occupation probabilities along the QD‐SOA cavity are considered as the state variables of the system. Using these variables, the distance dependence of the rate equations is eliminated. The derived state space model gives the optical gain and output signal of the amplifier with a high accuracy. Simulation results show that the derived model is not only much simpler and faster than conventional rate equation models, but also the optical gain and output signal of the investigated QD‐SOA are calculated with a higher precision compared to the rate equation model. Copyright © 2013 John Wiley & Sons, Ltd.     

Modular design of QCA carry flow adders and multiplier with reduced wire crossing and number of logic gates

Quantum‐dot cellular automata (QCA) is an emerging technology with the rapid development of low‐power high‐performance digital circuits. In order to reduce the wire crossings and the number of logic gates in QCA circuits, this paper proposes a full adder named Tile full adder based on a 3 × 3 grid module, a Tile bit‐serial adder based on the new full adder and a Diverse Clock Tile bit serial adder (DC Tile bit‐serial) adder based on the new full adder and a DC multiplier network. Based on previously mentioned circuit units an improved carry flow adder (CFA) named Tile CFA and two types of carry delay multiplier (CDM) named Tile CDM and DC Tile CDM (DC Tile CDM) with different sizes are presented. All of the proposed QCA circuits are designed and simulated with QCADesigner. Simulation results show that these circuit designs not only implement the logic functions correctly but also achieve a significant performance improvement. Copyright © 2015 John Wiley & Sons, Ltd.     

Design of high‐speed low‐power parallel‐prefix adder trees in nanometer technologies

This paper presents a novel approach to design high‐speed low‐power parallel‐prefix adder trees. Sub‐circuits typically used in the design of parallel‐prefix trees are deeply analyzed and separately optimized. The modules used for computing the group propagate and generate signals have been designed to improve their energy‐delay behavior in an original way. When the ST 45 nm 1 V CMOS technology is used, in comparison with conventional implementations, the proposed approach exhibits computational delay with mean value and standard deviation up to 40% and 48% lower and achieves energy consumption with mean value and standard deviation up to 57% and 40% lower. A 32‐bit Brent‐Kung tree made as proposed here reaches a computational delay lower than 165 ps and dissipates 147.4fJ on average. Copyright © 2013 John Wiley & Sons, Ltd.     

Design of a reversible structure for memory in quantum-dot cellular automata

Complementary metal oxide semiconductor (CMOS) technology has limitations in reducing the area and size of circuits. The disadvantages of this technology include high power consumption and temperature problems. Quantum-dot cellular automata (QCA) is a new technology that can overcome these shortcomings. Reversible logic is technology used to reduce the power loss in QCA. QCA can be used to design memories that require high operating speed. In this paper, we propose a structure for the reversible memory in QCA. The proposed structure utilizes three-layer technology, which has a significant impact on circuit size reduction. The proposed structure for the reversible memory has 63% improvement in cell number, a 75% improvement in area occupancy, and a 60% reduction in delay compared to the previous best structure.     

A framework for high‐speed parallel‐prefix adder performance evaluation and comparison

A new framework is proposed for the evaluation and comparison of high‐speed parallel‐prefix adders. The framework specifies input registers and latches and requires sum feedback for single cycle pipelined operation. Test pattern generation is also specified. A newly revised energy‐efficient 64‐bit carry select adder with distributed mixed valence logic to help reduce fan‐out and wire load is presented. Footless pulsed‐precharge domino and compound domino circuits, and smaller transistors help to reduce area and power. Detailed simulations with 65 nm CMOS models are compared with other parallel‐prefix adders that have been instantiated for comparison. Within this framework, energy reductions of 40% are obtained for the new adder versus two leading Kogge‐Stone designs, and 25% versus a new constant delay logic Sklansky style design, at similar cycle times. Copyright © 2014 John Wiley & Sons, Ltd.     

Design and research of a three‐phase voltage sensor based on D‐dot principle

In the design of three‐phase D‐dot voltage sensor based on electric field coupling, both effects of both the adjacent phase electric fields and distribution parameters on measurement should be taken into consideration. This paper builds a simulation model and a physical measuring system of a three‐phase sensor, measures the effect of the distribution parameters by the simulation model, and finally finds the transfer function between the input and output voltage signals of the circuit. The measured voltage waveforms and parameters can be reflected by the physical measuring system. Our results provide a theoretical basis for the design of a three‐phase D‐dot voltage sensor. And the measuring system can achieve multipoint synchronous acquisition and ensure less distortion. © 2016 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

Performance of a novel dot matrix fuel cell using an inorganic micro‐proton conductor

The power generation properties of a novel dot matrix fuel cell using an inorganic micro‐proton conductor were evaluated in dry gas mixtures of hydrogen and oxygen during room‐temperature operation. The single dot matrix fuel cell was composed of aggregates of micro‐electrolyte dots filling pores arranged in a matrix form on a Teflon or polyimide substrate with Pt/C and Pt catalytic electrodes. Micro‐electrolyte dots were prepared by the sol–gel method using titanium phosphorus oxides as the proton conductive hybrid materials. The open‐circuit voltage of the single cell became higher when using a small dot diameter and achieved a maximum of 500 mV with an electrolyte dot density of 17 dots/cm² in the dry gas mixtures during room‐temperature operation. This value corresponds to about one‐half of the theoretical electromotive force. Moreover, the current density of the single cell increased with the dot diameter such that it grew to 8 mA/cm² at a dot diameter of 500 µm. As a result, dot matrix fuel cells connected in series and parallel were found to achieve the cell performance of high‐energy density such as used by high‐energy microchips. © 2012 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

A power efficient buck‐boost converter by reusing the coil inductor for wireless bio‐implants

In this paper, a buck‐boost converter circuit for wireless power transfer via inductive links in bio‐implantable systems is presented. The idea is based on reusing the power receiver coil to design a regulator. This method employs five switches to utilize the coil inductor in a frequency other than the power‐receiving signal frequency. Reusing the coil inductor decreases the on‐chip regulator area and makes it suitable for bio‐implants. Furthermore, in the proposed technique, the regulator efficiency becomes almost independent of the coil receiving voltage amplitude. The proposed concept is employed in a buck‐boost regulator, and simulation results are provided. For a 10 MHz received signal with the amplitude variation within 3 ~ 6 V and with the converter switching rate of 200 kHz, the achieved maximum efficiency is 78%. The proposed regulator can also deliver 10 μA to 4 mA to its load while its output voltage varies from 0.6 to 2.3 V. Simulations of the proposed converter are performed in Cadence‐Spectre using TSMC 0.18 μm CMOS technology. Copyright © 2017 John Wiley & Sons, Ltd.     

A method for the approximate synthesis of cellular non‐linear networks—Part 2: Circuit reduction

In this paper, we face the problem of model reduction in piecewise‐linear (PWL) approximations of non‐linear functions. The reduction procedure presented here is based on the PWL approximation method proposed in a companion paper and resorts to a strategy that exploits the orthonormality of basis functions in terms of a proper inner product. Such a procedure can be favourably applied to the synthesis of the resistive parts of cellular non‐linear networks (CNNs) to reduce the complexity of the resulting circuits. As an example, the method is applied to a case study concerning a CNN for image processing. Copyright © 2003 John Wiley & Sons, Ltd.     

A novel single‐stage AC–DC converter with quasi‐resonant zero‐voltage‐switching for high power factor and high efficient applications

A new single‐stage‐isolated ac–dc converter that can guarantee both high efficiency and high power factor is proposed. It is based on a new dc–dc topology that has prominent conversion ratio similar to that of boost topology so that it is adequate to deal with the universal ac input. In addition, since it utilizes the transformer more than others based on the general flyback topology, the size of whole power system can be reduced due to the reduced transformer. Moreover, the voltage stresses on the secondary rectifiers can be clamped to the output voltage by adopting the capacitive output filter and clamp diode, and the turn‐off loss in the main switch can be reduced by utilizing the resonance. Furthermore, since this converter operates at the boundary conduction mode, the line input current can be shaped as the waveform of a line voltage automatically and the quasi‐resonant zero‐voltage switching can be obtained. Consequently, it features higher efficiency, lower voltage stress, and smaller sized transformer than other topologies. A 100 W prototype has been built and tested as the validation of the proposed topology. Copyright © 2010 John Wiley & Sons, Ltd.     

Design space exploration for sparse matrix‐matrix multiplication on FPGAs

The design and implementation of a sparse matrix‐matrix multiplication architecture on field‐programmable gate arrays is presented. Performance of the design, in terms of computational latency, as well as the associated power‐delay and energy‐delay tradeoff are studied. Taking advantage of the sparsity of the input matrices, the proposed design allows user‐tunable power‐delay and energy‐delay tradeoffs by employing different number of processing elements (PEs) in the architecture design and different block size in the blocking decomposition. Such ability allows designers to employ different on‐chip computational architecture for different system power‐delay and energy‐delay requirements. It is in contrast to conventional dense matrix‐matrix multiplication architectures that always favor the maximum number of PEs and largest block size. In our implementation, the better energy consumption and power‐delay product favors less PEs and smaller block size for the 90%‐sparsity matrix‐matrix multiplications. Although in order to achieve better energy‐delay product, more PEs and larger block size are preferred. Copyright © 2011 John Wiley & Sons, Ltd.