Analog CMOS integrated circuit design: research and undergraduateteaching

The authors describe the use of software that was developed as part of a research program in analog CMOS integrated circuit design for an undergraduate course on analog VLSI design. The software includes some unusual uses of readily available, inexpensive, and easy-to-use programs available for microcomputers such as Macintosh or IBM-PC clones. Although initially intended to help with the design of CMOS operational amplifiers, the IC design method used is very general; other possible applications are described. The flexibility of these programs also allows them to be used with other CAD (computer-aided design) software, including circuit simulators and programs for schematic entry and layout. The software tools allow undergraduate students to complete analog CMOS integrated circuit designs using advanced CAD techniques but without being overwhelmed or losing touch with the underlying circuit design principles. Details of the programs and their use are presented together with the resulting analog IC designs fabricated using MOSIS (MOS Implementation Service)     

Low‐Noise Fully Differential Amplifiers Using JFET‐CMOS Integration Technology for Smart Sensors

In this paper, CMOS‐based low‐noise amplifiers with JFET‐CMOS technology for high‐resolution sensor interface circuits are presented. A differential difference amplifier (DDA) configuration is employed to realize differential signal amplification with very high input impedance, which is required for the front‐end circuit in many sensor applications. Low‐noise JFET devices are used as input pair of the input differential stages or source‐grounded output load devices, which are dominant in the total noise floor of DDA circuits. A fully differential amplifier circuit with pure CMOS DDA and three types of JFET‐CMOS DDAs were fabricated and their noise performances were compared. The results show that the total noise floor of the JFET‐CMOS amplifier was much lower compared to that of the pure CMOS configuration. The noise‐reduction effect of JFET replacement depends on the circuit configuration. The noise reduction effect by JFET device was maximum of about − 18 dB at 2.5 Hz. JFET‐CMOS technology is very effective in improving the signal‐to‐noise ratio (SNR) of a sensor interface circuit with CMOS‐based sensing systems. © 2008 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

A multipurpose circuit to read out and digitize pixel signal for low-power CMOS imagers

A complementary metal oxide semiconductor (CMOS) image sensor with a resolution of 128 × 128 pixels is presented in this paper in which pixel signal readout, noise suppression, and comparing operations are performed by one circuit during two steps: reading and conversion. The main idea of this work is to combine three main operations of an image sensor in one circuit. This method helps to decrease power consumption, silicon area, total noise, and imaging time. The total power consumption of the imager is 11 mW with a 2.5-V power supply and 40-fps frame rate. The pixel layout size is 10 × 10 μm² with a fill-factor of 81%. The analog to digital converter (ADC) resolution is 10 bits, and the error resulted from the proposed circuit is about ±0.5 least significant bit (LSB). The proposed CMOS image sensor was designed based on Taiwan Semiconductor Manufacturing Company (TSMC) 0.18-μm CMOS technology and was simulated by CADENCE SPECTRE circuit simulator. This circuit can be proposed for a CMOS imager with highly accurate and efficient power consumption.     

Asynchronous cellular logic network as a co‐processor for a general‐purpose massively parallel array

This paper demonstrates an implementation of an asynchronous cellular processor array that facilitates binary trigger‐wave propagations, extensively used in various image‐processing algorithms. The circuit operates in a continuous‐time mode, achieving high operational performance and low‐power consumption. An integrated circuit with proof‐of‐concept array of 24×60 cells has been fabricated in a 0.35µm three‐metal CMOS process and tested. Occupying only 16×8µm² the binary wave‐propagation cell is designed to be used as a co‐processor in general‐purpose processor‐per‐pixel arrays intended for focal‐plane image processing. The results of global operations such as object reconstruction and hole filling are presented. Copyright © 2010 John Wiley & Sons, Ltd.     

基于USB2.0的数字摄像系统设计

给出了基于图像传感器OV7660和USB2.0接口的数字图像采集系统设计方案,介绍了硬件电路的设计思路及组成.在此基础上,详细分析了USB2.0单片机控制图像传感器的采集时序,描述了初始化设置图像传感器内部寄存器,读写时序配合的固件程序和将采样数据形成图像实时显示到上位机的图像处理软件.实验表明,该系统软硬件能够很好的配合工作,完成空间图像的实时采样,并且能够实时显示图像,画质优良.     

The subcircuit extraction problem

The steady down scaling of CMOS device dimensions has been the main stimulus to the growth of microelectronics and computer aided very large scale integration (VLSI) design. But the more an integrated circuit (IC) is scaled, the higher its packing density becomes. The increasing size of chips, measured in either area or number of transistors, and the waste of the large capital investment involved in fabricating and testing circuits that do not work, make layout analysis and verification an important part of physical design automation. The most efficient way to overcome these difficulties is to identify a related collection of interconnected primitive devices in a circuit as a gate-level component. This is usually called the subcircuit extraction problem. The paper presents some background on subcircuit extraction. Subcircuit extraction is becoming a more critical issue with the increasing design sizes of very large scale integrated circuits (VLSICs). In the future, one of the most important tasks is to convert current stand-alone subcircuit extraction algorithms into economic benefits. We should make every effort to find those companies who would like to incorporate these algorithms into their VLSI layout verification software to speed up the process.     

A Hybrid Microfluidic/CMOS Capacitive Sensor Dedicated to Lab-on-Chip Applications

A hybrid microfluidic/IC capacitive sensor is presented in this paper for highly integrated lab-on-chips (LoCs). We put forward the design and implementation of a charge based capacitive sensor array in 0.18-mum CMOS process. This sensor chip is incorporated with a microfluidic channel using direct-write microfluidic fabrication process (DWFP). The design, construction and experimental results as well are demonstrated using four different chemical solutions with known dielectric constants. The proposed highly sensitive CMOS capacitive sensor (ap530 mV/fF) along with low complexity DWFP emerges as clear favorite for LoC applications.     

Recent progress on CMOS successive approximation ADCs

Recent progress in CMOS integrated successive approximation (SAR) analog‐to‐digital converters (ADCs) is remarkable in terms of architecture and performance. Because of the inherent non‐necessity of active circuit elements such as operational amplifiers, the SAR architecture is suitable for fine CMOS processes. By using a time‐interleaved architecture, it achieves a very high speed conversion rate of 90 G‐sample/s with an 8‐bit resolution. Also, for applications with very low power consumption, such as wireless sensor nodes, it achieves 84 nW at 10‐bit, 200 k‐sample/s. A high signal to noise and distortion ratio (SNDR) can also be achieved by using several techniques such as an SAR architecture that combines oversampling and noise shaping. This survey paper explains the progress made recently in SAR‐ADC circuit techniques and the achieved performances. © 2016 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

A Wireless Capsule Endoscope System With Low-Power Controlling and Processing ASIC

This paper presents the design of a wireless capsule endoscope system. The proposed system is mainly composed of a CMOS image sensor, a RF transceiver and a low-power controlling and processing application specific integrated circuit (ASIC). Several design challenges involving system power reduction, system miniaturization and wireless wake-up method are resolved by employing optimized system architecture, integration of an area and power efficient image compression module, a power management unit (PMU) and a novel wireless wake-up subsystem with zero standby current in the ASIC design. The ASIC has been fabricated in 0.18-mum CMOS technology with a die area of 3.4 mm _* 3.3 mm. The digital baseband can work under a power supply down to 0.95 V with a power dissipation of 1.3 mW. The prototype capsule based on the ASIC and a data recorder has been developed. Test result shows that proposed system architecture with local image compression lead to an average of 45% energy reduction for transmitting an image frame.     

基于IIC总线的图像传感器接口设计

本文主要介绍了IIC总线的概念、特点以及基于IIC总线的图像传感器接口的软硬件设计与实现。文章采用软件模拟的方法实现了不带IIC总线接口的TMS320C54x与CMOS图像传感器之间的IIC通讯。IIC总线系统软硬件通过调试,应用在视频监控系统中,效果良好。本文所提出的设计方法配置灵活,性能可靠,具有较大实用价值。     

高帧频DVI接口彩色CMOS数字相机系统设计

针对高帧频彩色CMOS图像传感器在机器视觉高速成像领域中的应用,本文介绍利用高性能可编程逻辑器件FPGA实现CMOS图像传感器MI-MV13的高速驱动时序的设计,并且在FPGA内部设计了高速FIFO缓存器和双口RAM来完成Bayer彩色阵列图像数据的实时同步转换输出RGB彩色分量。最终由2片专用DVI接口集成芯片SiI178实现了DVI-IDualLink模式的高帧频高分辨率彩色图像输出,DVI接口方便显示终端和高速存储设备链接。该相机系统具有集成度高、低功耗、接口通用紧凑、传输带宽高的优点。     

A 9‐bit successive approximation ADC in SOI CMOS operating up to 300 °C

Industrial electronics are in great demand for oil and gas exploration, well drilling, and automotive applications where the operating temperature goes beyond 200 °C. Circuit designs using conventional complementary metal–oxide semiconductor (CMOS) technology are mostly rated at maximum of 125 °C, which is not suitable for harsh environment. In this paper, a high‐temperature (HT) 9‐bit successive approximation register analog‐to‐digital converter (SAR ADC) designed in silicon‐on‐insolation CMOS technology with a sampling rate of 50 kS/s is presented. The design considerations of the HT SAR ADC are discussed from process selection, temperature‐aware circuit design, and measurement perspectives. The ADC achieves an effective number of bit (ENOB) of 8.35 bits and a figure of merit of 93 pJ/step at room temperature. Under HT test, ENOBs of 7.3 bits at 225 °C and 6.9 bits at 300 °C are obtained. The power consumption is 1.52 mW from a 5‐V supply at room temperature and only 2.17 mW at 300 °C. Copyright © 2015 John Wiley & Sons, Ltd.     

Sensitivity-Enhanced CMOS Phase Luminometry System Using Xerogel-Based Sensors

We present the design and implementation of a phase luminometry sensor system with improved and tunable detection sensitivity achieved using a complementary metal-oxide semiconductor (CMOS) integrated circuit. We use sol-gel derived xerogel thin films as an immobilization media to house oxygen (O₂) responsive luminescent molecules. The sensor operates on the principal of phase luminometry wherein a sinusoidal modulation signal is used to excite the luminophores encapsulated in the porous xerogel films and the corresponding phase shift of the emission signals is monitored. The phase shift is directly related to excited state lifetimes of the luminophores which in turn are related to the concentration of the target analyte species present in the vicinity of the luminophores. The CMOS IC, which consists of a 16 times 16 high-gain phototransistor array, current-to-voltage converter, amplifier and tunable phase shift detector, consumes an average power of 14 mW with 5-V power supply operating at a 38-kHz modulation frequency. The output of the IC is a dc voltage that corresponds to the detected luminescence phase shift with respect to the excitation signal. As a prototype, we demonstrate an oxygen sensor system by encapsulating the luminophore tris(4,7-diphenyl-1,10-phenanthroline)ruthenium(II) within the xerogel matrices. The sensor system showed a fast response on the order of few seconds and we obtained a detection sensitivity of 118 mV per 1% change in O₂ concentration. The system demonstrates a novel concept to tune and improve the detection sensitivity for specific concentrations of the target analyte in many biomedical monitoring applications.     

Design and analysis of power‐CMOS‐gate‐based switched‐capacitor DC–DC converter with step‐down and step‐up modes

A unified multi‐stage power‐CMOS‐transmission‐gate‐based quasi‐switched‐capacitor (QSC) DC–DC converter is proposed to integrate both step‐down and step‐up modes all in one circuit configuration for low‐power applications. In this paper, by using power‐CMOS‐transmission‐gate as a bi‐directional switch, the various topologies for step‐down and step‐up modes can be integrated in the same circuit configuration, and the configuration does not require any inductive elements, so the IC fabrication is promising for realization. In addition, both large‐signal state‐space equation and small‐signal transfer function are derived by state‐space averaging technique, and expressed all in one unified formulation for both modes. Based on the unified model, it is all presented for control design and theoretical analysis, including steady‐state output and power, power efficiency, maximum voltage conversion ratio, maximum power efficiency, maximum output power, output voltage ripple percentage, capacitance selection, closed‐loop control and stability, etc. Finally, a multi‐stage QSC DC–DC converter with step‐down and step‐up modes is made in circuit layout by PSPICE tool, and some topics are discussed, including (1) voltage conversion, output ripple percentage, and power efficiency, (2) output robustness against source noises and (3) regulation capability of converter with loading variation. The simulated results are illustrated to show the efficacy of the unified configuration proposed. Copyright © 2003 John Wiley & Sons, Ltd.     

From energy‐delay metrics to constraints on the design of digital circuits

In this paper, the adoption of general metrics of the energy‐delay tradeoff is investigated to achieve energy‐efficient design of digital CMOS very large‐scale integrated circuits. Indeed, as shown in a preliminary analysis on the performance of various commercial microprocessors, a wide range of EⁱD^j metrics is typically adopted. Physical interpretation and interesting properties for the designs minimizing EⁱD^j metrics are provided together with the adoption of the Logical Effort theory to define practical design constraints. Two design examples in a 65‐nm CMOS technology are also reported to exemplify the theoretical results. Copyright © 2011 John Wiley & Sons, Ltd.     

Design and implementation of a digital control IC for driving multiple cold cathode fluorescent lamps

This study designs and develops a digital control integrated circuit (IC) for driving circuits operating multiple cold cathode fluorescent lamps (CCFLs). The control IC adopts an external crystal oscillator for the IC's external frequency to provide the driving circuits a fixed frequency. Inside the IC, two control loops are designed, under synchronized operation frequencies, for a boost regulator and an inverter. The main function of the boost regulator control loop is to supply a steady DC voltage for the inverter. In designing the inverter's control circuit, an adjustable‐frequency adjustable‐voltage soft‐start technique is used to start the lamps. We also use burst mode digital dimming technique to achieve synchronized dimming for the parallel‐connected lamp‐ignition circuits. The feedback voltage from the CCFLs can determine if any lamp is abnormal via a proposed lamp abnormality detection circuit. To deal with the equivalent‐circuit's component parameter differences among various manufacturers' and brands' piezoelectric transformers (PTs), the inverter's operation frequency is designed fine‐tunable in this study. Finally, the proposed design concept was implemented with an actual control IC and a driving circuit for CCFLs. The measured data and waveforms from our test circuitry are presented, which verifies the validity of the miniaturized controller proposed in this study. Copyright © 2008 John Wiley & Sons, Ltd.     

A 5‐MHz AT‐cut quartz crystal oscillating circuit functioning in 350 nA

An oscillating circuit functioning at ultra low power (350 nA) for a 5‐MHz AT‐cut quartz crystal oscillator was investigated. This circuit has a resistance between the power terminal of the CMOS‐IC and the power supply, and another between the earth terminal of the CMOS‐IC and the ground (GND). These resistances discourage an inrush of current, and set a gain (g_m) necessary for oscillating the circuit at minimum. The developed circuit is quite simple, but enables driving at once‐unthinkable, low power (below 1 µA). © 2007 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

A wide variable‐range CMOS–VCXO for IC

Recently, miniaturization, low power consumption, and high‐frequency stability have been required in crystal oscillators as a frequency source, because of the rapid development of mobile communications, typified by cellular phones. Usually, a VCXO (Voltage Controlled Crystal Oscillator) has been included in PLL. And it has been required that the VCXO should be implemented on a CMOS–IC chip. The oscillating frequency of a traditional VCXO has been controlled by capacitance variation of a varactor diode. But it is difficult to implement the varactor diode on an IC chip. In our previous study, we showed that a transistor VCXO utilizing the MOSFET's Miller capacitance of a variable capacitance circuit had a wide frequency variable range. On the other hand, in a CMOS–VCXO, the Miller capacitance has decreased. Therefore, a wide frequency variable range could not be obtained by utilizing the Miller capacitance in the CMOS–VCXO. In this paper, first, a variable capacitance circuit is realized in order to construct a wide‐variable‐range CMOS–VCXO for IC. The variable capacitance circuit is composed of a MOSFET as a voltage controlled resistance. Next, the CMOS–VCXO is constructed by the variable capacitance circuit and a CMOS crystal oscillator. As a result, we show that the CMOS–VCXO has a wide frequency variable range of about 400 ppm.© 1999 Scripta Technica, Electr Eng Jpn, 130(3): 49–56, 2000     

A waveform generator circuit for extra low‐frequency CMOS micro‐power applications

This paper presents a novel low‐power CMOS extra low‐frequency (ELF) waveform generator based on an operational trans‐conductance amplifier (OTA). The generator has been designed and fabricated using 2.5‐V devices available in 130‐nm IBM CMOS technology with a ±1.2‐V voltage supply. Using the same topology, two sets of device dimensions and circuit components are designed and fabricated for comparing relative performance, silicon area and power dissipation. The first design consumes 691 μW, while the second design consumes 943 μW using the same voltage supply. This low‐power performance enables the circuit to be used in many micro‐power applications. ELF oscillation is achieved for the two designs being around 3.95 Hz and 3.90 Hz, respectively, with negligible waveform distortion. The measured frequencies agree well with the simulation results. The first design is found to provide overall optimal performance compared to the second design at the expense of higher silicon area. Copyright © 2015 John Wiley & Sons, Ltd.     

A 1–6 GHz analog radio frequency power driver in 90 nm complementary metal‐oxide semiconductor technology for wireless applications

One of the most challenging subsystems for integrated radio frequency (RF) complementary metal‐oxide semiconductor (CMOS) solutions is the power amplifier. A 1–6 GHz RF power driver (RFPD) in 90 nm CMOS technology is presented, which receives signals from on‐chip RF signal chain components at ?12 dBm power levels and produces a 0 dBm signal to on‐chip or off‐chip 50 Ω loads. A unique unit cell design is developed for the RFPD to offset issues associated with very wide multi‐fingered transistors. The RF driver was fabricated as a stand‐alone sub‐circuit on a 90 nm CMOS die with other sub‐circuits. Experimental tests confirmed that the on‐chip RFPD operates up to 6 GHz and is able to drive 50 Ω loads to the desired 0 dBm power level. Spur free dynamic range exceeded 70 dB. The measured power gain was 11.6 dB at 3 GHz. The measured 1 dB compression point and input third‐order intercept point (IIP3) were ?4.7 dBm and ?0.5 dBm, respectively. Also, included are modeling, simulation, and measured results addressing issues associated with interfacing the die to a package with pinouts and the package to a printed circuit test fixture. The simulations were made through direct current (DC), alternating current (AC), and transient analysis with Cadence Analog Design Environment. The stability was also verified on the basis of phase margin simulations from extracted circuit net‐lists. Copyright © 2013 John Wiley & Sons, Ltd.