Design of high‐speed low‐power parallel‐prefix adder trees in nanometer technologies

This paper presents a novel approach to design high‐speed low‐power parallel‐prefix adder trees. Sub‐circuits typically used in the design of parallel‐prefix trees are deeply analyzed and separately optimized. The modules used for computing the group propagate and generate signals have been designed to improve their energy‐delay behavior in an original way. When the ST 45 nm 1 V CMOS technology is used, in comparison with conventional implementations, the proposed approach exhibits computational delay with mean value and standard deviation up to 40% and 48% lower and achieves energy consumption with mean value and standard deviation up to 57% and 40% lower. A 32‐bit Brent‐Kung tree made as proposed here reaches a computational delay lower than 165 ps and dissipates 147.4fJ on average. Copyright © 2013 John Wiley & Sons, Ltd.     

Energy‐efficient single‐clock‐cycle binary comparator

A new fast low‐power single‐clock‐cycle binary comparator is presented. High speed is assured by using parallel‐prefix architecture, whereas low power is guaranteed by reducing the switching activities of the internal nodes. When implemented with the ST 90 nm 1 V CMOS technology, the proposed circuit exhibits a 4.5 GHz maximum running frequency and 0.77µW/ MHz energy dissipation. Copyright © 2010 John Wiley & Sons, Ltd.     

Noise‐immune dual‐rail dynamic circuit for wide fan‐in gates in asynchronous designs

Dual‐rail dynamic logic circuits can provide inverting and noninverting outputs, especially for asynchronous designs, to implement complicated gates at the cost of approximately doubling the area and power consumption. In this paper, a new dual‐rail dynamic circuit is proposed which has lower die area consumption and higher noise immunity without dramatic speed degradation for even wide fan‐in gates for asynchronous circuits. The main idea in the proposed circuit is that voltage due to the current of the pulldown network (PDN) is compared with the reference voltage to provide two complementary outputs. The reference voltage almost corresponds to the leakage current of the PDN with all transistors being off. The proposed circuit is compared with conventional dual‐rail circuits such as differential domino logic and differential cross‐coupled domino logic. Simulation results for 32‐bit‐wide OR gates designed using high‐performance 16‐nm predictive technology model demonstrate significant performance advantages such as 66% power reduction and at least 2.86× noise‐immunity improvement at the same delay compared to the differential domino circuits. © 2012 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

Design of low power approximate floating‐point adders

Due to the increasing demands for more power in data intensive computing, low power design methodologies play a very important role in these systems. For noncritical data, the approximate computing that significantly reduces the power can be used. In this paper, an approximate floating‐point adder is proposed by designing an inexact mantissa adder and exponent subtractor. The results indicate that the power consumption and delay of the proposed approximate floating‐point adder have been decreased by 37% and 62% compared with the IEEE‐754 single‐precision floating‐point (FP) adder. Furthermore, compared with a state‐of‐the‐art inexact floating‐point adder, the proposed method provides an improvement of 7% and 21% in terms of the power consumption and delay. In addition, the proposed floating‐point adder has been investigated in terms of error, and the mean error of the proposed floating‐point adder at worst is about 55% less than that of another approximate floating‐point adder considered in this work. High dynamic range (HDR) images are processed using the proposed approximate floating‐point adders to show the performance of the proposed adder. The results show that, on average, peak signal‐to‐noise ratio increased by 9.6 and 18.64 dB, which may be achieved by utilizing the proposed floating‐point adder.     

Modular design of QCA carry flow adders and multiplier with reduced wire crossing and number of logic gates

Quantum‐dot cellular automata (QCA) is an emerging technology with the rapid development of low‐power high‐performance digital circuits. In order to reduce the wire crossings and the number of logic gates in QCA circuits, this paper proposes a full adder named Tile full adder based on a 3 × 3 grid module, a Tile bit‐serial adder based on the new full adder and a Diverse Clock Tile bit serial adder (DC Tile bit‐serial) adder based on the new full adder and a DC multiplier network. Based on previously mentioned circuit units an improved carry flow adder (CFA) named Tile CFA and two types of carry delay multiplier (CDM) named Tile CDM and DC Tile CDM (DC Tile CDM) with different sizes are presented. All of the proposed QCA circuits are designed and simulated with QCADesigner. Simulation results show that these circuit designs not only implement the logic functions correctly but also achieve a significant performance improvement. Copyright © 2015 John Wiley & Sons, Ltd.     

Gate‐level body biasing technique for high‐speed sub‐threshold CMOS logic gates

An efficient technique for designing high‐performance logic circuits operating in sub‐threshold region is proposed. A simple gate‐level body biasing circuit is exploited to change dynamically the threshold voltage of transistors on the basis of the gate status. Such an auxiliary circuit prepares the logic gate for fast switching while maintaining energy efficiency. If 200 aJ is the target total energy per operation consumption, a two input NAND (NOR) gate designed as described here shows a delay reduction between 20% (16%) and 40% (48%), with respect to previously proposed sub‐threshold approaches. Copyright 2012 John Wiley & Sons, Ltd.     

Noise‐tolerant dynamic CMOS circuits design by using true single‐phase clock latching technique

In this paper, a true‐single‐phase clock latching based noise‐tolerant (TSPCL‐NT) design for dynamic CMOS circuits is proposed. A TSPCL‐NT dynamic circuit can isolate and filter noise before the noise enters into the dynamic circuit. Therefore, it cannot only greatly enhance the noise tolerance of dynamic circuits but also release the signal contention between the feedback keeper and the pull‐down network effectively. As a result, noise tolerance of dynamic circuits can be improved with lower sacrifice in power consumption and operating speed. In the 16‐bit TSPCL‐NT Manchester adder, the average noise threshold energy can be enhanced by 3.41 times. In the meanwhile, the power‐delay product can be improved by 5.92% as compared with the state‐of‐the art 16‐bit XOR‐NT Manchester adder design under TSMC 90 nm CMOS process. Copyright © 2014 John Wiley & Sons, Ltd.     

一种高速浮点加法器的优化设计

高性能浮点加法器是现代微处理器中的重要部件,是实时图像处理和数字信号处理的核心,同时也是微处理器数据处理的关键路径,其完成一次加法操作的周期基本决定了微处理器的主频。本文介绍了一种高速浮点加法器的优化设计,它通过采用基于Two-Path算法的错位并行改进算法;在前导零预测电路设计中采用并行预测;尾数的54位CLA加法器中采用NAND门来代替以前CLA中常用的NOT门和AND门等一系列的改进措施,从而提高了浮点加法器的速度,使得加法运算由传统的5周期变成3周期,经仿真验证后,加法器的频率能达到350MHz。经仿真验证后,采用逻辑门比传统的浮点加法算法节省了23%。     

FDSTDL: Low-power technique for FinFET domino circuits

Major issues in designing low-power high-speed VLSI circuits are propagation delay, power consumption, and noise tolerance. This paper describes fin field-effect transistor (FinFET) technology for the design of low-power VLSI circuits. FinFET uses two gates (front and back) in place of a single gate as in complementary metal-oxide–semiconductor (CMOS) technology for better control of the channel. A new technique foot driven stack transistor domino logic (FDSTDL) is proposed for designing domino logic circuits in order to reduce leakage power and propagation delay. In this paper, 2-, 4-, 8-, and 16-input domino OR gates are designed and simulated using existing and proposed techniques in CMOS and FinFET technology. Simulation is done on the 32 nm predictive technology model (PTM) node using HSPICE on a direct current (DC) supply voltage of 0.9 V. The proposed circuit is simulated in two modes of FinFET, short gate (SG) mode, and low power (LP) mode. The proposed technique shows maximum power reduction of 43.45% in SG mode in comparison with conditional stacked keeper domino logic (CSK-DL) technique and maximum delay reduction of 38.66% in LP mode in comparison with coarse-mesh finite difference (CMFD) technique at a frequency of 200 MHz.     

Design of novel efficient adder and subtractor for quantum‐dot cellular automata

Quantum‐dot cellular automata (QCA) is one of the new emerging technologies being investigated as an alternative to complementary metal oxide semiconductor technology. This paper proposes optimized one‐bit full adder (FA) for implementation in QCA. The fault effects at the proposed FA outputs due to the missing cell defects are analyzed, and the test vectors for detection of all faults are identified. Also, the efficient designs of one‐bit full subtractor (FS), one‐bit FA/FS and four‐bit carry flow adder (CFA) are presented using the proposed FA. These structures are designed and simulated using QCADesigner software. The proposed designs are compared with other previous works. In comparison with the best previous design, the proposed FA has 25% and 26% improvement in cells count and area, respectively, and it is faster. For the proposed FS, FA/FS and CFA, the obtained results confirm that these designs are more efficient in terms of area, cell count and delay. Therefore, the implementation of these designs may lead to the efficient use of the calculative unit in various applications, which may be used as a basic building block of a general purpose nanoprocessor. Copyright © 2014 John Wiley & Sons, Ltd.     

Startup analysis of an H2‐O2‐fired gas turbine cycle

A new thermodynamic cycle using artificial energy is now under investigation. The Japanese World Energy Network research program (WE‐NET) is one of the artificial energy technology programs which will use hydrogen energy. One of the targets of the program is the development of a high‐thermal‐efficiency, emission‐free power plant. The H₂‐O₂‐fired gas turbine is the key technology of the program and the advanced Rankine cycle is suggested as one of the most effective cycles. The advanced Rankine cycle is based on the direct steam expansion cycle. Mass and heat balance calculations were performed to determine the optimal operating point and the component design was carried out to develop the cycle. Further investigations necessary to realize the cycle include such topics as operational ability and cost performance. This paper considers operational ability, especially startup performance. In this analysis, the algorithm and process flow configuration for startup are developed. The investigation finds that the advanced Rankine cycle has good potential for practical use. © 1999 Scripta Technica, Electr Eng Jpn, 128(1): 9–16, 1999     

Simplified carry save adder‐based array multiplier scheme and circuits design

Conventional array multiplier based on carry save adders is optimized in this letter. Some specific full adders in the adders array for partial products accumulation are simplified without any cost. By modifying the logic expressions of two special full adders, circuit complexity is reduced, resulting in decreased power dissipation and propagation delay. Static circuit structures for the adders are provided to demonstrate the effectiveness. Furthermore, logical AND gates to produce partial products are redesigned to save area and power. The layout regularity of array multiplier is well preserved. Circuit simulation shows that speed and power can be improved 9.7% and 3.1% for a 4*4 structure, and the number of transistors decreases 5.3%. Copyright © 2014 John Wiley & Sons, Ltd.     

Output‐feedback model‐reference adaptive calibration for map‐based anti‐jerk control of electromechanical automotive clutches

It is well known that the map‐based control can reduce the computational burden of the automotive on‐board controller. This paper proposes an output‐feedback model‐reference adaptive control algorithm to calibrate the map‐based anti‐jerk controller for electromechanical clutch engagement. The algorithm can be used to adaptively construct a data‐driven fuzzy rule base without resorting to manual tuning, so that it can overcome the problem of conventional knowledge‐based fuzzy logic design, which involves strenuous parameter‐tuning work in the construction of calibration maps. To accurately define the consequent of each fuzzy rule for anti‐jerk control, an output feedback law for computing the reference trajectory of clutch engagement is developed to eliminate the discontinuous slip‐stick transition, whereas an adaptive controller is designed to track the reference trajectory and compensate the nonlinearity. The convergence of the proposed output‐feedback model‐reference adaptive control algorithm is analyzed. Simulation results indicate that the proposed method can successfully reduce the excessive vehicle jerk and frictional energy dissipation during clutch engagement as compared with the conventional knowledge‐based fuzzy logic controller without fine tuning.     

High‐voltage compliant microelectrode array drivers for intracortical microstimulation

We present in this paper two low‐power high‐impedance microelectrode array drivers (MEDs) dedicated for visual intracortical microstimulation. These output stages of a new microstimulator are highly configurable and able to deliver higher compliance voltage (20 V for anodic and cathodic phases) across microelectrode‐tissue interface impedance compared with previously reported designs. Each MED is featured with a high‐voltage switch‐matrix, 3.3 V/20 V current mirrors, an on‐chip 32‐bit serial‐in parallel‐out shift register, and the new forbidden state logic circuits. Both systems are able to deliver eight bipolar or 16 monopolar stimulation simultaneously. The first MED is able to deliver one stimulation current level and the second one provides four different current amplitudes simultaneously to 16 electrodes. Two microchips have been designed and fabricated using Teledyne DALSA 0.8 µm 5V/ 20v double‐diffused metal‐oxide‐semiconductor field‐effect transistor (Teledyne DALSA Semiconductor, Bromont, Québec, Canada) technology to meet the required high‐voltage compliance. The nominal values of largest supply voltages are ±10 V. The maximum stimulation current per input channel is 400 μA and per output channel through an emulated microelectrode impedance of 100 kΩ is 100 μA. The measured output compliance voltage is 10 V/phase (anodic or cathodic) for the specified supply voltages. Increment of supply voltages to ±13 V allows 220 μA stimulation current per output channel enhancing the output compliance voltage up to 20 V/phase. The measured quiescent power consumptions of the proposed microelectrode array drivers are 316 and 735 μW, respectively. Post‐layout simulation and measurement results of two MEDs and comparison with other designs have been reported in this paper. Copyright © 2015 John Wiley & Sons, Ltd.     

Analysis and design of a two‐transformer active‐clamping forward converter with parallel‐connected current doubler rectifiers

A new two‐transformer active‐clamping forward converter with parallel‐connected current doubler rectifiers (CDRs) is proposed in this paper. The presented DC–DC converter is mainly composed of two active‐clamping forward converters with secondary CDRs. Only two switches are required and each one is the auxiliary switch for the other. The circuit complexity and cost are thus reduced. The leakage inductance of the transformer or an additional resonant inductance is employed to achieve zero‐voltage‐switching (ZVS) during the dead times. Two CDRs at the secondary side are connected in parallel to reduce the current stresses of the secondary windings and the ripple current at the output side. Accordingly, the smaller output chokes and capacitors decrease the converter volume and increase the power density. Detailed analysis and design of the presented two‐transformer active‐clamping forward converter are described. Experimental results are recorded for a prototype converter with a DC input voltage of 130??180V, an output voltage of 5 V and an output current of 40 A, operating at a switching frequency of 100 kHz. Copyright © 2010 John Wiley & Sons, Ltd.     

Hardware‐efficient approximate logarithmic division with improved accuracy

Among all the arithmetic operations, division operation takes most of the clock cycles resulting in more path delay and higher power consumption. Many algorithms, including logarithmic division (LD), have been implemented to reduce the critical path delay and power consumption of division operation. However, there is a high possibility to further reduce these vital issues by using the novel approximate LD (ALD) algorithm. In the proposed ALD, a truncation adder is used for mantissa addition. Using this adder, the power delay product (PDP) and normalized mean error distance (NMED) are minimized. From the error analysis and hardware evaluation, it is observed that the proposed ALD using truncation adder (ALD‐TA) with an appropriate number of inexact bits achieve lower power consumption and higher accuracy than existing LDs with exact units. The normalized mean error distance of 8‐, 16‐, and 32‐bit ALD‐TA is compared with LDs of same bits and observed a decrease of up to 21%, 20%, and 21%, and the PDP has a reduction of up to 33%, 51%, and 72%, respectively. Application of ALD‐TA to image processing shows that high performance can be achieved by using ALDs than exact LDs.     

Electroosmotic micropump for lab‐on‐a‐chip biomedical applications

Lab‐on‐a‐chip (LOC) integrated microfluidics has been a powerful tool for new developments in analytical chemistry. These microfluidic systems enable the miniaturization, integration and automation of complex biochemical assays through the reduction of reagent use and enabling portability. Electroosmotic micropumps could be employed as powerful tools to generate required flow in point of care (POC) devices. In the present study, parallel electroosmotic micropumps are investigated to improve the efficiency of simple micropumps. According to the results, parallel micropumps generate higher flow rate in comparison with conventional electroosmotic pump. In the last decade, a large variety of non‐Newtonian fluids have been utilized in biomedical application but requirements for a POC device such as high efficient driving flow, miniaturization and simple handling of POC devices remain unmet. As a consequence, in this study, power law model as non‐Newtonian fluids that flow through the parallel micropumps are investigated in order to enhance fluid pumping and decreasing voltage requirement.. It is found that as the power law index increases the mass flow rate decreases. Also, the flow rate is almost constant for the higher power law index. Obtained results, demonstrated that parallel micropump could enhance pumping of non‐Newtonian fluid (blood) up to 30%. Copyright © 2016 John Wiley & Sons, Ltd.     

A highly sensitive and ultra low‐power forward body biasing circuit to overcome severe process,voltage and temperature variations and extreme voltage scaling

Dynamic voltage scaling is one of the most popular methods used to reduce energy consumption in today's digital electronic systems. However, addressing process, voltage and temperature variations at subthreshold voltages has become an inevitable procedure. Using a variation‐sensitive and ultra low‐power design, this paper proposed a novel technique capable of sensing and responding to process, voltage and temperature variations as well as dynamic voltage scaling by providing an appropriate forward body bias so that energy‐delay product of the whole system was improved. Theoretical analysis for process variation probability, confirmed by post‐layout HSPICE (Synopsys, Inc., Mountain View, CA) simulations for an 8‐bit pipelined Kogge–Stone adder, showed that the circuit performance was enhanced in severe variations and extreme voltage scaling situation. For this adder, for example, assuming a voltage scaling from 0.8 to 0.3 V and temperature changes of ?15 to 75 °C, the proposed technique brought about a seven times less delay variation, whereas energy‐delay product improved by 23% compared with a zero body biased adder. Copyright © 2013 John Wiley & Sons, Ltd.     

A numerical model for the oscillation frequency,the amplitude and the phase‐noise of MOS‐current‐mode‐logic ring oscillators

This paper presents a new model for the frequency of oscillation, the oscillation amplitude and the phase‐noise of ring oscillators consisting of MOS‐current‐mode‐logic delay cells. The numerical model has been validated through circuit simulations of oscillators designed with a typical 130 nm CMOS technology. A design flow based on the proposed model and on circuit simulations is presented and applied to cells with active loads. The choice of the cell parameters that minimize phase‐noise and power consumption is addressed. Copyright © 2009 John Wiley & Sons, Ltd.