Design of high‐speed low‐power parallel‐prefix adder trees in nanometer technologies

This paper presents a novel approach to design high‐speed low‐power parallel‐prefix adder trees. Sub‐circuits typically used in the design of parallel‐prefix trees are deeply analyzed and separately optimized. The modules used for computing the group propagate and generate signals have been designed to improve their energy‐delay behavior in an original way. When the ST 45 nm 1 V CMOS technology is used, in comparison with conventional implementations, the proposed approach exhibits computational delay with mean value and standard deviation up to 40% and 48% lower and achieves energy consumption with mean value and standard deviation up to 57% and 40% lower. A 32‐bit Brent‐Kung tree made as proposed here reaches a computational delay lower than 165 ps and dissipates 147.4fJ on average. Copyright © 2013 John Wiley & Sons, Ltd.     

Simplified carry save adder‐based array multiplier scheme and circuits design

Conventional array multiplier based on carry save adders is optimized in this letter. Some specific full adders in the adders array for partial products accumulation are simplified without any cost. By modifying the logic expressions of two special full adders, circuit complexity is reduced, resulting in decreased power dissipation and propagation delay. Static circuit structures for the adders are provided to demonstrate the effectiveness. Furthermore, logical AND gates to produce partial products are redesigned to save area and power. The layout regularity of array multiplier is well preserved. Circuit simulation shows that speed and power can be improved 9.7% and 3.1% for a 4*4 structure, and the number of transistors decreases 5.3%. Copyright © 2014 John Wiley & Sons, Ltd.     

Gate‐level body biasing technique for high‐speed sub‐threshold CMOS logic gates

An efficient technique for designing high‐performance logic circuits operating in sub‐threshold region is proposed. A simple gate‐level body biasing circuit is exploited to change dynamically the threshold voltage of transistors on the basis of the gate status. Such an auxiliary circuit prepares the logic gate for fast switching while maintaining energy efficiency. If 200 aJ is the target total energy per operation consumption, a two input NAND (NOR) gate designed as described here shows a delay reduction between 20% (16%) and 40% (48%), with respect to previously proposed sub‐threshold approaches. Copyright 2012 John Wiley & Sons, Ltd.     

Active‐terminated transmitter and receiver circuits for high‐speed low‐swing duobinary signaling

In this work, we propose transmitter and receiver circuits for high‐speed, low‐swing duobinary signaling over active‐terminated chip‐to‐chip interconnect. In active‐termination scheme port impedance of transmitter and receiver is matched with characteristic impedance of the interconnect. Elimination of the passive terminators helps in reducing the transmitted signal level without degrading the 0signal detectability of the receiver. High‐speed current‐mode receiver and transmitter circuits are designed, so that the input port impedance of the receiver and the output port impedance of the transmitter are matched with characteristic impedance of the link. These Tx–Rx pair is used to validate the proposed active‐termination scheme. We also propose a duobinary precoder architecture suitable for high‐speed operation and a low‐power broadband equalizer topology for compensating the lossy long interconnect. The duobinary transmitter and receiver circuits are implemented in 1.8 V, 0.18 µm Digital CMOS technology. The designed high‐speed duobinary Tx/Rx circuits work up to 8 Gb/s speed while transmitting the data over 29.5 in. FR4 PCB trace for a targeted bit error rate (BER) of 10^?15. The power consumed in the transmitter and receiver circuits is 42.9 mW at 8 Gb/s. Copyright © 2010 John Wiley & Sons, Ltd.     

An MTJ‐based non‐volatile flip‐flop for high‐performance SoC

The conventional magnetic tunneling junction (MTJ)‐based non‐volatile D flip‐flop (NVDFF) has a slow D‐Q delay and a tradeoff between its D‐Q delay and its sensing current. In addition, a sufficient write current cannot be obtained with the core device, since two MTJs exist in the write path and a write current degradation problem occurs due to the precharge transistors. The proposed MTJ‐based non‐volatile semidynamic flip‐flop (NVSDFF) has a semidynamic structure that ensures a fast D‐Q delay and separates the sensing circuit from the D‐Q signal path to reduce the sensing current without affecting the D‐Q delay. The proposed NVSDFF also provides a sufficient write current by merely using the core device, since only one MTJ exists in the write path. In addition, the head switch, which is added to remove the write current degradation problem, further reduces the sensing current. Thus, the proposed NVSDFF has a higher read disturbance margin than the previous NVDFF with an IO device. The HSPICE simulation results with the industry‐compatible 45 nm model parameter show that the D‐Q delay in the proposed NVSDFF is 50.5% of that of the previous NVDFF with an IO device, and the sensing current, 32.3%. In the proposed NVSDFF, the read disturbance margin is 15.9% larger than in the previous NVDFF with an IO device, and the area is 17.8% smaller. Copyright © 2012 John Wiley & Sons, Ltd.     

Optimum design approach for low‐speed,high‐torque permanent magnet motors

This paper presents an optimum design approach for low‐speed, high‐torque permanent magnet motors. The approach is divided into two steps: the first consists of the rough estimation of torque by linear analysis, and the second the optimization of the motor configuration by nonlinear FEM analysis. Under restricted dimensional specifications and electrical requirements, a 16‐pole, 18‐coil permanent magnet motor with a rating of 600 Nm and 300 rpm was designed and constructed. © 2001 Scripta Technica, Electr Eng Jpn, 135(4): 52–63, 2001     

A low‐power technique for high‐resolution dynamic comparators

A low‐power technique for high‐resolution comparators is introduced. In this technique, p‐type metal‐oxide‐semiconductor field‐effect transistors are employed as the input of the latch of the comparator just like the input of the preamplifier. The latch and preamplifier stages are activated in a special pattern using an inverter‐based controller. Unlike the conventional comparator, the preamplification delay can be set to an optimum low value even if after the preamplification, the output voltages is less than n‐channel metal‐oxide semiconductor voltage threshold. As a result, the proposed comparator reduces the power consumption significantly and enhances the speed. The speed and power benefits of the proposed comparator were verified using analytical derivations, PVT corners, and post layout simulations. The results confirm that the introduced technique reduces the power consumption by 60%, also, provides 57% better comparison speed for an input common mode voltage (V_cm) range of 0‐Vdd/2.     

Design and analysis of low‐speed,high‐torque permanent magnet motors

This paper presents design and analysis of low‐speed, high‐torque permanent magnet motors. The motor has 16‐pole, 18‐coil construction, and a unique winding arrangement to produce high torque. The simplified torque analysis is proposed considering the line of magnetic induction distribution in the motor. The validity of the proposed analysis has been proved by both linear and nonlinear FEM analyses. The 500‐Nm, 200‐rpm test motor has been designed and constructed and the motor shows the expected characteristics. © 2000 Scripta Technica, Electr Eng Jpn, 132(3): 48–56, 2000     

Control schemes and transient characteristics of a high‐speed phase shifter for power flow control in power transmission systems

In recent years, attention has been paid to the concept of FACTS (Flexible AC Transmission Systems), along with significant progress in power electronic technology. A high‐speed phase shifter, which is one of the most promising devices in the FACTS concept, has the potential of power flow control and/or voltage stability in power transmission systems. In this paper, theory and experiment reveal that conventional high‐speed phase shifters may cause power swings in a transient state as a result of coupling between instantaneous active and reactive power control loops. Thus, two new control schemes for a high‐speed phase shifter are proposed to achieve both power flow control and power swing damping. The second proposed control scheme is based on the control scheme of an already proposed series active filter. Simulated and experimental results agree well with analytical results, not only in steady states but also in transient states. © 1999 Scripta Technica, Electr Eng Jpn, 128(2): 74–82, 1999     

Two novel low power and very high speed pulse triggered flip‐flops

Two novel low power and high‐speed pulse triggered flip‐flops were presented in this paper. Short circuit current was controlled, and race condition between pull‐up and pull‐down branches was removed, which caused reduction of power consumption. On the other hand, the number of stack transistors in the discharging path was reduced which decreased delay of the flip‐flops. The first proposed flip‐flop reduced the number of transistors and the second proposed flip‐flop used conditional data mapping and removed floating node of the first flip‐flop. Post‐layout simulation result showed that the first proposed flip‐flop reduced 21% of power delay product and the second proposed flip‐flop reduced 16% of power delay product in comparison with other flip‐flops in 50% of data switching activities. Copyright © 2014 John Wiley & Sons, Ltd.     

An accurate power delivery system (PDS) design methodology for high‐speed digital systems

The trend in high‐speed digital circuits is to increase speed and density and to operate at lower voltage. This fast increase in the switching speed combined with the decrease of the operating voltage causes the allowable absolute voltage variations to decrease, which makes the PDS design a more challenging task than ever. Moreover, the complex 3D nature of the modern PDS causes it to be more sensitive to capacitors' placement as well as capacitance value. In this paper, we introduce an efficient complete solution for the design of high‐speed digital PDS. This solution (a) takes the effects of the decoupling capacitor placement into consideration through a 3D electromagnetic simulation of the PDS, (b) defines a more‐realistic PDS design target, and (c) presents a clear capacitor value selection methodology. Finally, we applied our methodology to an industrial test case, compared its results with that of industrial design, and showed its advantages. Copyright © 2010 John Wiley & Sons, Ltd.     

A high‐speed RSD‐based flexible ECC processor for arbitrary curves over general prime field

This workpresents a novel high‐speed redundant‐signed‐digit (RSD)‐based elliptic curve cryptographic (ECC) processor for arbitrary curves over a general prime field. The proposed ECC processor works for any value of the prime number and curve parameters. It is based on a new high speed Montgomery multiplier architecture which uses different parallel computation techniques at both circuit level and architectural level. At the circuit level, RSD and carry save techniques are adopted while pre‐computation logic is incorporated at the architectural level. As a result of these optimization strategies, the proposed Montgomery multiplier offers a significant reduction in computation time over the state‐of‐the‐art. At the system level, to further enhance the overall performance of the proposed ECC processor, Montgomery ladder algorithm with (X,Y)‐only common Z coordinate (co‐Z) arithmetic is adopted. The proposed ECC processor is synthesized and implemented on different Xilinx Virtex (V) FPGA families for field sizes of 256 to 521 bits. On V‐6 platform, it computes a single 256 to 521 bits scalar point multiplication operation in 0.65 to 2.6 ms which is up to 9 times speed‐up over the state‐of‐the‐art.     

Low‐power,low‐area preamplifier for ultra high‐speed multi‐channel optical communication system

A novel circuit technique was applied to the design of a preamplifier for ultra high‐speed short‐distance parallel optical communication system in standard 180‐nm CMOS technology. This circuit is featured by low power, low area as well as high gain bandwidth product, and suited for applications in low‐cost process. The restraint on voltage headroom as bottleneck in traditionally adopted regulated cascode configuration has been fundamentally analyzed and lifted by feed‐forward common gate stage to achieve high gain bandwidth product under limited f_T and strict power restriction. Complex poles were carefully assigned to further attain bandwidth extension without sacrifice on power, noise, and chip area. No additional peaking techniques and subsequent gain‐boosting stages are adopted, which makes the design simple and favorable in low‐cost high‐density multi‐channel optical communication system. The preamplifier provides a trans‐impedance gain of up to 52 dBΩ and a 3‐dB bandwidth of 8.4 GHz. Operating under a 1.8‐V supply, the power dissipation is 8 mW, and the chip area is only 0.075×0.08 mm. The measured average input‐referred noise–current spectral density is . Copyright © 2011 John Wiley & Sons, Ltd.     

Development of a new adaptive LQG system generator for high‐speed damping control techniques of power system oscillation

With the advent of interconnection of large‐scale electric power systems, many new dynamics power system problems have emerged, which include low‐frequency intersystem oscillations and many others. To date, most major generators in trunk electric power systems in Japan are equipped with supplementary excitation control, commonly referred to as the conventional single and two input PSS. However, low‐frequency oscillations still occur. It is difficult for these conventional PSS to improve the additional damping of power system oscillation, because of the hardware and design of fixed PSS control constants from a one‐machine infinite‐bus model. It has therefore become necessary to develop a new adaptive LQG system generator. This paper explains the development of the new adaptive LQG system and the simulation of low‐frequency and local mode oscillation for this new adaptive LQG system. © 2002 Wiley Periodicals, Inc. Electr Eng Jpn, 142(3): 30–40, 2003; Published online in Wiley InterScience ( www.interscience.wiley.com ). DOI 10.1002/eej.10109     

A speed control method for a PM motor using a speed observer and a low‐resolution encoder

This paper proposes a new speed control method for a PM motor using a low‐resolution encoder and a speed observer. The servo system should be economical and simple. For this purpose, this paper realizes the high‐performance speed control system using a low‐resolution encoder, whose performance is nearly equal to the performance of speed servo system using a conventional optical encoder. The speed observer uses the information of motor current and motor voltage. The rotor position is calculated by the estimated value of speed observer. This observer has the influence of electrical parameter variation. This paper proposes the correction algorithm of both the voltage error of PWM inverter and the electrical parameter variation. The experimental results and numerical simulation results point out that the proposed speed control system has the desired speed response with respect to parameter variations and load torque perturbation. © 2003 Wiley Periodicals, Inc. Electr Eng Jpn, 143(1): 66–75, 2003; Published online in Wiley InterScience ( www.interscience.wiley.com ). DOI 10.1002/eej.10121     

Examination of new vector control system of permanent magnet synchronous motor for high‐speed drives

A new vector control system for permanent magnet synchronous motor drives has been developed. To stabilize the current control loop in the high‐rotating‐speed region, a novel configuration of current controller is introduced. The unique characteristic of the proposed current controller is that the current regulator is connected to the conventional motor model in a series. By analyzing the transfer characteristics of the control, it became clear that the influence of the coupling component between the d–q axes can be deleted theoretically if the control parameters are set properly. The stability and torque response of the proposed vector control system were improved, and the effectiveness of the proposed controller was demonstrated by a time domain simulation and some experiments. In addition, the robustness of the controlling system was investigated experimentally. © 2011 Wiley Periodicals, Inc. Electr Eng Jpn, 176(4): 61–72, 2011; Published online in Wiley Online Library ( wileyonlinelibrary.com ). DOI 10.1002/eej.21123     

A 0.1 to 2.7‐GHz SOI SP8T antenna switch adopting body self‐adapting bias technique for low‐loss high‐power applications

A low‐loss high‐power single‐pole 8‐throw antenna switch adopting body self‐adapting bias technique in a 0.18‐μm thick‐film partially depleted silicon‐on‐insulator complementary metal‐oxide‐semiconductor process is implemented for multimode multiband cellular applications. A topology with symmetric port design is developed. We employ the body‐contacted field‐effect transistor to handle high power level and obtain low harmonic distortion. However, the conventional bias method for body‐contacted field‐effect transistor leads to poor insertion loss (IL), serious imbalanced voltage division, and large die size. Therefore, a new body self‐adapting bias scheme is adopted to improve the IL and power handling capability with die area reward by removing the employment of extra biasing resistor and voltage supply at the body. The presented silicon‐on‐insulator antenna switch utilizing the new body bias strategy reveals similar harmonic performance as a conventional switch version, thanks to the analogous DC bias to the gate and body, while it exhibits effectively lower IL, imbalanced voltage division, and die area. The measured IL and 0.1‐dB compression point (P_?0.1dB), at 1.9/2.7 GHz, are roughly 0.52/0.82 dB and 39.2/36.9 dBm, respectively. The overall IL and P_?0.1dB are apparently improved by approximately 0.05 to 0.13 dB and 0.5 to 0.8 dBm compared with the conventional version.     

A power‐performance tunable logic with adjustable threshold pseudo‐dynamic building blocks and CMOS compatibility

The continued downscaling of CMOS technology has resulted in very high performance devices, but power dissipation is a limiting factor on this way. Power and performance of a device are dependent on process, temperature, and workload variation that makes it impossible to find a single power optimal design. As a result, adaptive power and performance adjustment techniques emerged as attractive methods to improve the effective power efficiency of a device in modern design approaches. Focusing on this issue, in this paper, a novel logic family is proposed that enables tuning the transistor's effective threshold voltage after fabrication for higher speed or lower power. This method along with dynamic voltage scaling allows simultaneous optimization of static and dynamic power based on the workload requirement. The externally static topology of the proposed logic makes it possible to replace static circuits without requiring significant changes in the system. Experimental results obtained using 90‐nm CMOS standard technology show that the proposed logic improves the average power‐delay product by about 40% for the attempted benchmarks.     

A fast acoustic field mapping approach based on fabry–perot sensor with high‐speed camera

A Fabry–Perot (FP) interferometer‐based ultrasound sensor provides an inherently broadband response and excellent detection sensitivity compared to piezoelectric zirconate titanate (PZT) or polyvinylidene difluoride (PVDF) transducers. It is therefore expected to be used for medical ultrasound imaging and photoacoustic imaging. However, at present, mapping acoustic fields takes much time for scanning, which hinders real‐time measurement. We propose a new approach that utilizes a high‐speed camera (HSC) to map acoustic fields without mechanical scanning and to sample signals of acoustic waves with the shutter of the HSC. Experimental results indicate that acoustic field at the focus of a pulsed 1‐MHz PZT ultrasound transducer can be detected and mapped by using the FP sensor with the HSC. By improving the uniformity of the FP sensor and the exposure time, the frame rate of HSC can be further developed, and this approach should be able to provide a fast acoustic field mapping for high‐resolution biomedical photoacoustic and other ultrasonic imaging. © 2014 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

Electromagnetic analysis coupled with motion for high‐speed circuit breakers of eddy current repulsion using the tableau approach

Electromagnetic field analysis coupled with motion using the tableau approach has been applied to high‐speed circuit breakers of eddy current repulsion mechanisms. This breaker has an opening time of 1 ms and break time less than 1 cycle (20 ms). The driving part of the breaker is composed of electromagnetic repulsion mechanisms and disk springs with nonlinear characteristics. The mechanisms are composed of two fixed coils and one repulsion plate. A numeric experiment has been applied to investigate the dynamic behavior of the electromagnetic repulsion mechanism using the equivalent circuit method. Calculation results were in good agreement with both measurement results and calculation results by FEM on an experimental model. In addition, repulsive forces depending on material conductivities have been researched. © 2005 Wiley Periodicals, Inc. Electr Eng Jpn, 152(4): 8–16, 2005; Published online in Wiley InterScience ( www.interscience.wiley.com ). DOI 10.1002/eej.20149