Divide‐by‐2 LC injection‐locked frequency divider with wide locking range at low and high injection powers

A wide locking range nMOS divide‐by‐2 RLC injection‐locked frequency divider (ILFD) was designed and implemented in the TSMC 0.18‐µm BiCMOS process. The ILFD is based on a cross‐coupled oscillator with one direct injection MOSFET and a RLC resonator. The RLC resonator is used to extend the locking range so that dual‐band locking ranges can be merged in one locking range at both low and high injection powers. At the drain‐source bias of 0.9 V for switching transistors, and at the incident power of 0 dBm the locking range of the divide‐by‐2 ILFD is 7.24 GHz, from the incident frequency 2.65 to 9.89 GHz, the locking range percentage is 115.47%. The power consumption of ILFD core is 8.685 mW. The die area is 0.726 × 0.930 mm². Copyright © 2016 John Wiley & Sons, Ltd.     

Wide‐band dual‐resonance capacitive cross‐coupled divide‐by‐5 injection‐locked frequency divider

A wide locking range divide‐by‐5 injection‐locked frequency divider (ILFD) is proposed and was implemented in the TSMC 0.18‐μm 1P6M CMOS process. Conventional divide‐by‐5 ILFD has limited locking range. The proposed divide‐by‐5 ILFD is based on a capacitive cross‐coupled voltage‐controlled oscillator (VCO) with a dual‐resonance resonator, which is implemented in the divide‐by‐5 ILFD to obtain a wide overlapped locking range. At the drain‐source bias V_DD of 0.9 V and at the incident power of 0 dBm, the measured locking range of the divide‐by‐5 ILFD is 3.2 GHz, from the incident frequency 9.4 to 12.6 GHz, the percentage is 29.09%. The core power consumption is 2.98 mW. The die area is 0.987 × 1.096 mm².     

Wide‐locking range divide‐by‐4 injection‐locked frequency divider using injection MOSFET DC‐biased above threshold region

A novel wide locking range divide‐by‐4 injection‐locked frequency divider (ILFD) is proposed in the paper and was implemented in the TSMC 0.18 µm 1P6M CMOS process. The divide‐by‐4 ILFD uses two injection transistors in series and DC‐biased above threshold voltage and a frequency doubler to enhance the function of linear mixers. At the drain‐source bias of 0.9 V and at the incident power of 0 dBm, the locking range of the divide‐by‐4 is 2.6 GHz; from the incident frequency 12.2 to 14.8 GHz, the percentage is 19.26%. The core power consumption is 10.35 mW. The die area of ILFD is 1.026 × 0.943 mm². Copyright © 2015 John Wiley & Sons, Ltd.     

A quad‐band W‐CDMA transceiver IC–direct conversion architecture with fractional frequency divider

A quad‐band (0.8, 1.7, 2, and 1.4 GHz) wideband code division multiple access (W‐CDMA) transceiver, which uses a divide‐by‐2.5 frequency divider in local parts of a direct‐conversion architecture, has been developed. Using the fractional‐2.5 frequency divider reduces the fractional bandwidth of the voltage‐controlled oscillator and avoids injection locking of the local RF synthesizer perfectly. This transceiver achieved 3% error‐vector magnitude and—46 dB ACLR, which satisfy the margin given in standard specifications. © 2012 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

A study of superharmonic injection locking in multiband frequency dividers

A superharmonic voltage‐controlled injection‐locked frequency divider, implemented using a modified Colpitts oscillator operating at 2.5, 5 and 10 GHz and a cross‐coupled LC oscillator operating at 1.25, 2.5 and 5 GHz, is demonstrated. The proposed triple‐band operation is achieved by employing a novel technique that uses pin‐diodes and negative power supply. The discrete dividers, built with low noise hetero‐junction FETs and high‐frequency SiGe BJTs, are described theoretically while their functionality is proven experimentally. Additionally, a short phase noise analysis, which is missing in the literature, is given. Phase noise, frequency range of operation, and locking range measurement results are presented. Finally, post‐layout simulation results of a 5 GHz fully differential injection‐locked frequency divider, implemented in a 0.25µm SiGe process are provided. Copyright © 2010 John Wiley & Sons, Ltd.     

Subharmonic injection‐locking and self‐oscillating mixing

Subharmonic injection‐locking and self‐oscillating mixing functions of a modified Colpitts oscillator operating at 1 GHz are reported. The injection‐locking circuit, using a GaAs FET, is described theoretically and experimentally. Phase noise, power consumption and conversion gain measurements indicate that the proposed design is attractive for low‐cost, low‐power consumption front‐ends. Copyright © 2008 John Wiley & Sons, Ltd.     

A 1.9‐GHz silicon‐on‐insulator CMOS stacked‐FET power amplifier with uniformly distributed voltage stresses

A 1.9‐GHz single‐stage differential stacked‐FET power amplifier with uniformly distributed voltage stresses was implemented using 0.32‐μm 2.8‐V thick‐oxide MOSFETs in a 0.18‐μm silicon‐on‐insulator CMOS process. The input cross‐coupled stacked‐FET topology was proposed to evenly distribute the voltage stresses among the stacked transistors, alleviating the breakdown and reliability issues of the stacked‐FET power amplifier in sub‐micrometer CMOS technology. With a 4‐V supply voltage, the proposed power amplifier with an integrated output coupled‐resonator balun showed a small‐signal gain of 17 dB, a saturated output power of 26.1 dBm, and a maximum power‐added efficiency of 41.5% at the operating frequency. Copyright © 2017 John Wiley & Sons, Ltd.     

Design and analysis of a millimeter‐wave injection locked frequency divider with transconductance boosting technique

This paper presents a degenerated injector (mixer) with transconductance boosted by biasing the mixer transistor in the knee region of its I‐V curve, without increasing the transistor size and its parasitics. This mixer can enhance the locking range of millimeter‐wave injection‐locked frequency dividers. To compensate the degradation of mixer transconductance (conversion‐gain) due to the degeneration effect, a neutralization technique is employed. Analyses are given for locking‐range and induced phase‐noise of the proposed divider for arbitrary injection strength. It is shown that the locking‐range, as a function of injection strength, is improved by increasing the fundamental component of transconductance. Using 180‐nm CMOS technology, a 1.78‐mW divider‐by‐two is designed with free‐running frequency of 27.92 GHz, locking‐range of 51 to 59.6 GHz, and figure‐of‐merit of 4.83 (GHz/mW). EM simulation results of the proposed and conventional structure are compared, which illustrates 56% improvement in locking‐range.     

A linear,ultra wideband,low‐power, 2.1–5 GHz,VCO

A linear, Ultra Wideband, low‐power VCO, suitable for UWB‐FM applications is proposed, forming the main part of a UWB‐FM transmitter. The VCO is designed in TSMC 90thinspacenm digital CMOS process and includes a Source‐Coupled Multivibrator, used as current‐controlled oscillator (CCO) which generates output frequencies between 2.1 and 5 GHz and a voltage‐to‐current (V‐to‐I) converter which translates the VCO input voltage modulation signal to current. Two single‐ended inverter buffers are employed to drive either a differential or a single‐ended UWB antenna. The presented VCO is designed for 1 V power supply and exhibits a linear tuning range of 2.1–5 GHz, a differential output power of ?7.83 dBm±0.78 dB and low power consumption of 8.26 mW, including the output buffers, at the maximum oscillation frequency. It is optimized for a very high ratio of tuning range (81.69%) over power consumption equal to 9.95 dB. The desired frequency band of 3.1–5 GHz for UWB‐FM applications is covered for the entire industrial temperature range (?40 to 125^°C). Copyright © 2010 John Wiley & Sons, Ltd.     

Nonlinear dynamics of divide‐by‐two injection‐locked frequency dividers in locked operation mode

A method for analyzing the nonlinear dynamics of the injection‐locked frequency dividers in synchronized operation mode is presented, including the stability analysis of locked states. We use a specific divide‐by‐two circuit, namely a differential LC CMOS divider with a complementary topology, as a guideline for presentation, showing that the sizing of the devices significantly affects the synchronization mechanism of the divider, which exhibits a very rich dynamical behavior. We provide closed‐form expressions to determine the amplitude and the phase in the locked state, as well as the locking range, leading to accurate results, which are validated by numerical simulations. The presented analysis of the frequency divider dynamics enables us to establish that stable locked oscillations occur on the whole locking range predicted by the well‐known Adler's equation and that these are possible also beyond that range. Copyright © 2013 John Wiley & Sons, Ltd.     

A wideband low‐spur 0.18‐µm CMOS phase‐locked loop with bandwidth calibration

This paper presents a 0.18‐µm complementary metal‐oxide‐semiconductor wideband phase‐locked loop with low reference spurs. The dual‐level charge‐pump current calibration technique is proposed to maintain a constant loop bandwidth for wide operation frequency range and achieve low reference spurs. The first level charge‐pump current calibration is seamlessly incorporated in the automatic frequency band hopping control and the mechanism also ensures enough negative transconductance for the voltage‐controlled oscillator to function throughout the whole frequency range. The charge‐pump current mismatch is calibrated by the second level charge‐pump current calibration combined with the pulse‐width scaling technique. The operation frequency range of the phase‐locked loop covers from 4.7 GHz to 6.1 GHz. The measured phase noise is?116 dBc/Hz at 1‐MHz offset and the reference spurs are below?66.8 dBc. Copyright © 2015 John Wiley & Sons, Ltd.     

A low‐voltage band‐gap reference circuit with second‐order analyses

A new band‐gap reference (BGR) circuit employing sub‐threshold current is proposed for low‐voltage operations. By employing the fraction of V_BE and the sub‐threshold current source, the proposed BGR circuit with chip area of 0.029mm² was fabricated in the standard 0.18µm CMOS triple‐well technology. It generates reference voltage of 170 mV with power consumption of 2.4µW at supply voltage of 1 V. The agreement between simulation and measurement shows that the variations of reference voltage are 1.3 mV for temperatures from ?20 to 100^°C, and 1.1 mV per volt for supply voltage from 0.95 to 2.5 V, respectively. Copyright © 2010 John Wiley & Sons, Ltd.     

A 5‐GHz energy‐efficient tunable pulse generator for ultra‐wideband applications using a variable attenuator for pulse shaping

A new energy‐efficient tunable pulse generator is presented in this paper using 0.13‐µm CMOS technology for short‐range high‐data‐rate 3.1–10.6 GHz ultra‐wideband applications. A ring oscillator consisting of current‐starved CMOS inverters is quickly switched on and off for the duration of the pulse, and the amplitude envelope is shaped with a variable passive CMOS attenuator. The variable passive attenuator is controlled using an impulse that is created by a low‐power glitch generator (CMOS NOR gate). The glitch generator combines the falling edge of the clock and its delayed inverse, allowing the duration of the impulse to be changed over a wide range (500–900 ps) by varying the delay between the edges. The pulses generated with this technique can provide a sharp frequency roll off with high out‐of‐band rejection to help meet the Federal Communications Commission mask. The entire circuit operates in switched mode with a low average power consumption of less than 3.8 mW at 910 MHz pulse repetition frequency or below 4.2 pJ of energy per pulse. It occupies a total area of 725 × 600 µm² including bonding pads and decoupling capacitors, and the active circuit area is only 360 × 200 µm². Copyright © 2011 John Wiley & Sons, Ltd.     

A subthreshold current‐sensing ΣΔ modulator for low‐voltage and low‐power sensor interfaces

A continuous‐time (CT) ΣΔ modulator for sensing and direct analog‐to‐digital conversion of nA‐range (subthreshold) currents is presented in this work. The presented modulator uses a subthreshold technique based on subthreshold source‐coupled logic cells to efficiently convert subthreshold current to digital code without performing current‐to‐voltage conversion. As a benefit of this technique, the current‐sensing CT ΣΔ modulator operates at low voltage and consumes very low power, which makes it convenient for low‐power and low‐voltage current‐mode sensor interfaces. The prototype design is implemented in a 0.18 µm standard complementary metal‐oxide semiconductor technology. The modulator operates with a supply voltage of 0.8 V and consumes 5.43 μW of power at the maximum bandwidth of 20 kHz. The obtainable current‐sensing resolution ranges from effective number of bits (ENOB) = 7.1 bits at a 5 kHz bandwidth to ENOB = 6.5 bits at a 20 kHz bandwidth (ENOB). The obtained power efficiency (peak FoM = 1.5 pJ/conv) outperforms existing current‐mode analog‐to‐digital converter designs and is comparable with the voltage‐mode CT ΣΔ modulators. The modulator generates very low levels of switching noise thanks to CT operation and subthreshold current‐mode circuits that draw a constant subthreshold current from the voltage supply. The presented modulator is used as a readout interface for sensors with current‐mode output in ultra low‐power conditions and is also suitable to perform on‐chip current measurements in power management circuits. Copyright © 2014 John Wiley & Sons, Ltd.     

Series resonant ZCS‐PFM DC‐DC power converter with high‐frequency high‐voltage transformer link for high‐power magnetron drive

This paper presents a single lossless inductive snubber‐assisted ZCS‐PFM series resonant DC‐DC power converter with a high‐frequency high‐voltage transformer link for industrial‐use high‐power magnetron drive. The current flowing through the active power switches rises gradually at a turned‐on transient state with the aid of a single lossless snubber inductor, and ZCS turn‐on commutation based on overlapping current can be achieved via the wide range pulse frequency modulation control scheme. The high‐frequency high‐voltage transformer primary side resonant current always becomes continuous operation mode, by electromagnetic loose coupling design of the high‐frequency high‐voltage transformer and the magnetizing inductance of the high‐frequency high‐voltage transformer. As a result, this high‐voltage power converter circuit for the magnetron can achieve a complete zero current soft switching under the condition of broad width gate voltage signals. Furthermore, this high‐voltage DC‐DC power converter circuit can regulate the output power from zero to full over audible frequency range via the two resonant frequency circuit design. Its operating performances are evaluated and discussed on the basis of the power loss analysis simulation and the experimental results from a practical point of view. © 2005 Wiley Periodicals, Inc. Electr Eng Jpn, 153(3): 79–87, 2005; Published online in Wiley InterScience ( www.interscience.wiley.com ). DOI 10.1002/eej.20126     

Low‐power quadrature generators for body area network applications

This paper presents different alternatives for the implementation of low‐power monolithic oscillators for wireless body area networks and describes the design of two quadrature generators operating in the 2.4‐GHz frequency range. Both implementations have been designed in a 90‐nm Complementary Metal‐Oxide Semiconductor (CMOS) technology and operate at 1 V of supply voltage. The first architecture uses a voltage‐controlled oscillator (VCO) running at twice the desired output frequency followed by a divider‐by‐2 circuit. It experimentally consumes 335 μW and achieves a phase noise of ?110.2 dBc/Hz at 1 MHz. The second architecture is a quadrature VCO that uses reinforced concrete phase shifters in the coupling path for phase noise improvement. Its power consumption is only 210 μW, and it obtains a phase noise of ?111.9 dBc/Hz at 1 MHz. Copyright © 2011 John Wiley & Sons, Ltd.     

An inductorless CMOS quadrature oscillator continuously tuneable from 3.1 to 10.6 GHz

Modern RF front‐ends require wide tuning‐range oscillators with quadrature outputs. In this paper we present a two‐integrator quadrature oscillator, which covers the whole bandwidth of UWB applications. A circuit prototype in a 130 nm CMOS technology is continuously tuneable from 3.1 to 10.6 GHz. The circuit die area is less than 0.013mm², leading to a figure‐of‐merit FOMA of ?176.7dBc/Hz at the upper frequency. The supply voltage is 1.2 V, and the power consumption is 7 mW at the lower frequency and 13 mW at the upper frequency. Copyright © 2010 John Wiley & Sons, Ltd.     

A 0.008‐mm2, 35‐μW, 8.87‐ps‐resolution CMOS time‐to‐digital converter using dual‐slope architecture

This paper presents a high resolution time‐to‐digital converter (TDC) for low‐area applications. To achieve both high resolution and low circuit area, we propose a dual‐slope voltage‐domain TDC, which is composed of a time‐to‐voltage converter (TVC) and an analog‐to‐digital converter (ADC). In the TVC, a current source and a capacitor are used to make the circuit as simple as possible. For the same reason, a single‐slope ADC, which is commonly used for compact area ADC applications, is adapted and optimized. Because the main non‐linearity occurs in the current source of the TVC and the ramp generator of the ADC, a double gain‐boosting current source is applied to overcome the low output impedance of the current source in the sub‐100‐nm CMOS process. The prototype TDC is implemented using a 65‐nm CMOS process, and occupies only 0.008 mm². The measurement result shows a dynamic range with an 8‐bit 8.86‐ps resolution and an integrated non‐linearity of ±1.25 LSB. Copyright © 2016 John Wiley & Sons, Ltd.     

Three‐stage multiphase‐switched‐capacitor boost DC‐AC inverter

A closed‐loop scheme of a three‐stage multiphase‐switched‐capacitor boost DC‐AC inverter (MPSCI) is proposed by combining the multiphase operation and sinusoidal‐pulse‐width‐modulation (SPWM) control for low‐power step‐up DC‐AC conversion and regulation. In this MPSCI, the power unit contains two parts: MPSC booster (front) and H‐bridge (rear). The MPSC booster is suggested for an inductor‐less step‐up DC‐DC conversion, where three voltage doublers in series are controlled with multiphase operation for boosting voltage gain up to 2³ = 8 at most. The H‐bridge is employed for DC‐AC inversion, where four solid‐state switches in H‐connection are controlled with SPWM to obtain a sinusoidal AC output. In addition, SPWM is adopted for enhancing output regulation not only to compensate the dynamic error, but also to reinforce robustness to source/loading variation. The relevant theoretical analysis and design include: MPSCI model, steady‐state/dynamic analysis, voltage conversion ratio, power efficiency, stability, capacitance selection, total harmonic distortion (THD), output filter, and closed‐loop control design. Finally, the closed‐loop MPSCI is simulated, and the hardware circuit is implemented and tested. All the results are illustrated to show the efficacy of the proposed scheme. Copyright © 2011 John Wiley & Sons, Ltd.     

A linearized and low noise CMOS mixer with B‐type amplifier‐based sub‐harmonic balun

A low noise and high linearity down‐conversion CMOS mixer for 2.4‐GHz wireless receiver is presented in this paper. Using a sub‐harmonic balun with a simple but effective B‐type amplifier, the local oscillator frequency required for this mixer has been reduced by half, and the input local oscillator signal could be single‐ended rather than differential, which simultaneously simplifies the design of local oscillator. A distortion and noise cancelation transconductor in association with current bleeding technique is employed to improve the noise and linearity of the entire mixer under a reduced bias current without compromising the voltage gain. Fabricated in a 0.18‐µm RF CMOS technology of Global Foundries, the mixer demonstrates a voltage gain of 15.8 dB and input‐referred third‐order intercept point of 6.6 dBm with a noise figure of 2.6 dB. It consumes 7.65 mA from a 1.0‐V supply and occupies a compact area of 0.75 × 0.71 mm² including all test pads. Copyright © 2016 John Wiley & Sons, Ltd.