Measurement and simulation of partial switching in ferroelectric PZT thin-films

Abstract

In digital memory applications, metal ferroelectric metal (MFM) capacitors are typically fully switched from one polarization state to the other, with the difference in displacement current allowing determination of the cell state. However, by applying a pulse of insufficient amplitude and/or duration to fully switch the ferroelectric, such a device may be partially polarized. Here, the measurement of partial switching in sol-gel derived PZT MFM capacitors due to applied voltage pulses is reported. SPICE, a commonly used circuit simulation program, has been modified to incorporate a ferroelectric capacitor device model. The MFM device model added to SPICE is reviewed, and the simulation of partial switching is demonstrated. Simulation results modeling the PE hysteresis loops and switching transients due to applied voltage steps closely match those measured in the laboratory. We conclude with the modeling of incomplete switching due to applied pulses of insufficient amplitude to cause polarization saturation, which is attributed to the polycrystalline nature of the thin-films.     

Physics-based modeling approaches of resistive switching devices for memory and in-memory computing applications

The semiconductor industry is currently challenged by the emergence of Internet of Things, Big data, and deep-learning techniques to enable object recognition and inference in portable computers. These revolutions demand new technologies for memory and computation going beyond the standard CMOS-based platform. In this scenario, resistive switching memory (RRAM) is extremely promising in the frame of storage technology, memory devices, and in-memory computing circuits, such as memristive logic or neuromorphic machines. To serve as enabling technology for these new fields, however, there is still a lack of industrial tools to predict the device behavior under certain operation schemes and to allow for optimization of the device properties based on materials and stack engineering. This work provides an overview of modeling approaches for RRAM simulation, at the level of technology computer aided design and high-level compact models for circuit simulations. Finite element method modeling, kinetic Monte Carlo models, and physics-based analytical models will be reviewed. The adaptation of modeling schemes to various RRAM concepts, such as filamentary switching and interface switching, will be discussed. Finally, application cases of compact modeling to simulate simple RRAM circuits for computing will be shown.     

Analytic transient solution of SCFL logic gates

In this paper we propose the analytical solution of switching transients for SCFL logic gates. The analysis of an SCFL logic gate is carried out without linearization and can be brought back to multiple analyses of a basic cell, given by a differential pair with switching input voltages and a variable tail current, to take the effect of series‐gating into account. The differential equation for this cell is a Riccati equation, if a quadratic current–voltage relationship is used for the transistors, and it can be solved by the infinite power series method, in case of polynomial input signals. An algorithm is proposed to analyse the full transient of a complex SCFL gate. This provides a closed form expression for transient signals in terms of circuit and device parameters, that can be used for symbolic analysis or fast time‐domain numerical simulation. Some case studies are presented for SCFL gates using OMMIC ED02AH technology, and a good agreement between the proposed model and SPICE simulations using complex device models is obtained. Copyright © 2005 John Wiley & Sons, Ltd.     

Why‐ and how‐ to integrate Verilog‐A compact models in SPICE simulators

This article presents a fast and accurate way to integrate and validate Verilog‐A compact models in SPICE‐like simulators. Modifications in the models' Verilog‐A source code may be required prior to their conversion into low‐level C language by a code generator. The most common of these modifications is discussed. The generated C code is then directly compiled in the target simulator resulting in an equivalent SPICE model. The comparison between Verilog‐A and SPICE models in the same simulation environment, for simple and complex circuits, validates the procedure. Performance tests for demanding designs are carried out for both models. Results highlight the higher simulation speed and lower memory consumption of SPICE models. Copyright © 2012 John Wiley & Sons, Ltd.     

Single crystalline SrTiO<Subscript>3</Subscript> as memristive model system: From materials science to neurological and psychological functions

Taking the advantage of the well-established defect chemistry of SrTiO₃, acceptor and donor doped SrTiO₃ single crystals are used as model systems to understand the roles of oxygen vacancies and the Schottky barrier in the resistive switching. More importantly, SrTiO₃ based memristive devices are used to emulate the neurological and psychological functions of the brain. The synaptic plasticity is achieved with Ni/Nb-SrTiO₃/Ti memristive devices, and the learning and forgetting processes of the brain, together with the resultant explicit and implicit memories, are also realized with the device. Associative learning, a classical learning case of the brain, is demonstrated as well. The emulation of various neurological and psychological functions in a single memristive device simplifies the construction of the artificial neural network and facilitates the advent of the artificial intelligence. In this work, materials science becomes directly related to neurology and psychology.     

Design rules for threshold switches based on a field triggered thermal runaway mechanism

We investigate a new type of threshold switching devices, which is based on a purely electronic phenomena. These threshold switches are polarity independent and switch abruptly from a high resistive state to a low resistive state at a threshold voltage. The device stays in this low resistive state as long as a high voltage drops over the device. When the voltage is reduced, the low resistive state is lost and the device switches back to the initial high resistive state. This makes these threshold switches highly interesting as selector elements for resistive switching memory concepts, based on device arrays, which are the prerequisite for new applications like logic-in-memory concepts. The threshold switching considered here is based on a combination of a Poole–Frenkel conduction mechanism and Joule heating. Hence, it is not strongly restricted to specific materials rather it is connected to the physical quantities of the Poole–Frenkel conduction mechanism and the thermal conductance. This enables to design the threshold switch to its application requirements by adjusting the relevant physical material properties or designing the device geometry. Here we present a theoretical study, which tackles the influence of several material properties and the device design. From this simulation model the impact on technical important figures of merits is determined, such as the threshold switching voltage and the selectivity.     

Finite element power diode model optimized through experiment‐based parameter extraction

This paper presents a finite element physics‐based power diode model with parameters established through an extraction procedure validated experimentally. The model core is a numerical module that solves the ambipolar diffusion equation through a variational formulation followed by an approximate solution with the finite element method. Other zones of the device are modeled with classical methods in an analytical module. This hybrid approach enables accurate modeling and simulation of power bipolar semiconductor devices, using standard SPICE circuit simulators, with low execution times. As physics‐based models need a significant number of parameters, an automatic parameter extraction method has been developed. The procedure, based on an optimization algorithm (simulated annealing), enables an efficient extraction of parameters using some simple device waveform measurements. Implementation details of power diode model, in IsSpice simulator, are presented. Experimental validation is performed. Results prove the usefulness of the proposed methodology for efficient design of power circuits through simulation. Copyright © 2008 John Wiley & Sons, Ltd.     

Interactive compact device modelling using Qucs equation‐defined devices

Recent trends in compact device modelling and circuit simulation suggest a growing movement towards standardization of Verilog‐A as a vehicle for semiconductor device specification and model interchange among commercial and open source simulators. This paper introduces a nonlinear equation‐defined device (EDD) characterized by current, voltage and charge equations with a similar syntax to Verilog‐A. The EDD has been implemented in Qucs and used extensively as a central feature in an interactive modelling system that allows straightforward prototyping of compact device models prior to translation into Verilog‐A. To illustrate the properties and the use of the Qucs EDD a number of examples centred on well‐known SPICE models are described. Copyright © 2008 John Wiley & Sons, Ltd.     

New macromodels of a switch for SPICE applications

This paper is concerned with the macromodeling of a “switch” which is important from the point of view of the SPICE simulation of DC-DC power converters, switching mode power supplies and power electronic circuits. In this paper, some new macromodels of switches are introduced which are simpler and allow faster simulation times than a previously known model. The underlying principle and the mechanism of the proposed models has been explained in a manner suitable for educational purposes     

晶闸管投切电容的最佳编码方式与最优投切阈值的数学分析和应用

投切电容的编码方式和投切阈值关系到采用晶闸管投切电容(Thyristor-switched capacitor,TSC)的静止无功补偿装置的补偿效果与经济性.文章从运筹学的角度对电容的最佳编码方式进行了数学分析,验证了二进制编码方式是最佳的,从数列和实际经验出发,得到了电容最优投切阈值的实用计算公式,并根据投切电容的最佳编码方式和最优投切阈值设计了一台TSC型静止无功补偿装置,通过与一般TSC型无功补偿装置的补偿效果进行比较表明该装置的补偿效果更明显,从而验证了本文数学理论分析的正确性.     

Advanced simulation tool for FeRAM design

Abstract

A ferroelectric capacitor model was derived, and a ferroelectric device library was implemented into SPICE (both PSPICE and HSPICE) simulation tool. With this SPICE model, 1T-1C/2T-2C, or any other ferroelectric circuit, such as FeFET, chain cell, link cell can be simulated accurately and in real-time. Simulations of hysteresis loops, TVS, switching characteristics are shown in this paper.     

A tabular source approach to modelling and simulating device and circuit noise in the time domain

Simulation of device and circuit noise at low frequencies is often carried out as part of a small‐signal ac analysis. Moreover, circuit simulators with rf analysis capabilities usually specify circuit performance in terms of S parameters and model high‐frequency noise in terms of noise waves and correlation matrices. It is also unusual to find circuit simulators that extend noise simulation to the time domain. This is particularly true for software packages developed from SPICE 2g6 or 3f5. This paper introduces a simple tabular noise source technique, which adds time‐domain noise to semiconductor device models and integrated circuit macromodels. The proposed technique is suitable for use with any general purpose circuit simulator. To demonstrate the power of the suggested approach the text describes time‐domain noise extensions to the SPICE diode, BJT, JFET, MOSFET and MESFET models. These noise extensions have been implemented and tested with the ‘Quite universal circuit simulator’ (Qucs). Copyright © 2011 John Wiley & Sons, Ltd.     

Area-efficient design of three- and four-stage voltage multipliers for power integrated circuits

In this paper we develop dynamic models for ideal three- and four-stage voltage multipliers. Starting from the models proposed, we can perform a pencil-and-paper area-efficient optimized design. The circuits discussed are commonly used in power ICs or memory ICs to allow the switching on of an MOS device. The models proposed are validated both by measurement on a breadboard and by SPICE simulation.     

An advanced VHDL‐AMS PiN diode model: towards simulation‐based design of power converters

This paper focuses on the modeling of a power PiN diode. The focal point basis is the dependence on temperature. The PiN diode remains a difficult device to model mainly during switching transients. An advanced PiN diode temperature‐dependent model is developed and implemented in VHDL‐AMS. Heterogeneous simulation scheme including the circuit wiring parasitic components, the probe effects and the dependent diode models is successfully simulated using SIMPLORER simulator. Experimental data of several commercial PiN diodes are compared to simulation results at different temperature levels. A good rate of consistency is found. Copyright © 2014 John Wiley & Sons, Ltd.     

The compact d.c. electrothermal model of power MOSFETs for SPICE

This paper concerns the problem of modelling of power MOS transistors in SPICE. In the paper the new form of the electrothermal d.c. model (ETM) of the considered class of power devices is proposed. The ETM is based on the modified Shichman–Hodges model, in which the generation current, the breakdown voltage, the sub‐threshold region, the thermally dependent series resistances and self‐heating are included. The device inner temperature calculated from the thermal model is the sum of the ambient temperature and the product of the electrical power dissipated inside the device and its thermal resistance. The presented model has been verified experimentally. The results of calculations and measurements of MTD15N06V (ON Semiconductor) and IRF840 (International Rectifier) transistors are given as well. Copyright © 2009 John Wiley & Sons, Ltd.     

Reliability Estimation for Large-Area Solder Joints Using Explicit Modeling of Damage

The issues of available cyclic fatigue models in life prediction of large-area solder joints using finite-element analysis (FEA) are discussed. In this paper, a new FEA approach called successive initiation (SI) is modified and introduced in conjunction with energy partitioning (E-P) damage model to resolve some of the issues with available damage models such as geometry and scale dependency and provide a solution to large-area solder joints. This new technique models damage explicitly, meaning that it separates initiation from propagation by monitoring the plastic and creep damage at the tip of the crack successively. The SI technique could be easily used with continuous loadings of different types and frequencies. The modeling approach is then implemented on a power device with large-area solder. Sensitivity study is conducted with the help of the experiment to determine the right initiation threshold for smooth crack initiation and propagation. The results of modeling are then compared with available experimental data for the same power device. The comparison shows that using the damage model constants generated for small solder joints such as ball-grid array or chip-scale package could significantly overpredict the life of larger area solders. New E-P damage model constants for large-area solder joints are obtained and presented by calibrating the modeling to the experiment.     

Complete delay modeling of sub‐threshold CMOS logic gates for low‐power application

In this paper, the propagation delay of a complementary metal‐oxide semiconductor (CMOS) inverter circuit in sub‐threshold regime has been analyzed thoroughly with respect to variable loads, rise and fall time of input, device dimensions and temperature, without neglecting the significant drain induced barrier lowering (DIBL) and body bias effects. In particular, sub‐threshold slope factor and current strength have been modeled with respect to temperature, which would be efficacious for the analysis of sub‐threshold circuit as temperature plays an important role in propagation delay. Transistor stacking has also been modeled considering variation in threshold voltage, sub‐threshold slope factor and DIBL coefficient owing mainly to fluctuation in doping levels. The CMOS inverter delay model together with transistor stacking model has been incorporated in the analysis of propagation delays of NAND and NOR gates. Extensive simulations have been performed under 45 and 22 nm CMOS technology using simulation program with integrated circuit emphasis (SPICE) to ensure the correctness of the analysis. Simulation shows that this model is applicable for the analysis of digital sub‐threshold circuit in sub‐90 nm technology. Copyright © 2015 John Wiley & Sons, Ltd.     

Anticipation of digital patterns

A memristive device is a novel passive device, which is essentially a resistor with memory. This device can be used for novel technical applications like neuromorphic computation. In this paper, we focus on anticipation—a capability of a system to decide how to react in an environment by predicting future states. Especially, we have designed an elementary memristive circuit for the anticipation of digital patterns, where this circuit is based on the capability of an amoeba to anticipate periodically occurring unipolar pulses. The resulting circuit has been verified by digital simulations and has been realized in hardware as well. For the practical realization, we have used an Ag‐doped TiO_2?x‐based memristive device, which has been fabricated in planar capacitor structures on a silicon wafer. The functionality of the circuit is shown by simulations and measurements. Finally, the anticipation of information is demonstrated by using images, where the robustness of this anticipatory circuit against noise and faulty intermediate information is visualized.