基于蚂蚁算法和遗传算法的同步时序电路初始化

本文针对时序电路的初始化提出一种新的实现方法．在电路没有设置一个总复位信号的情况下，必须。使得电路状态由未知变为已知，电路才能正常工作．本文用逻辑初始化方式，通过将蚂蚁算法和遗传算法交叉生成初始化序列，最大限度地初始化触发器，实现电路的初始化．实验结果表明，这种方法和其他同类算法相比较能在初始化触发器数量和序列长度上取得很好的结果．     

一种先进的时序电路测试生成算法

本文对近年来国内外学者在时序电路测试生成方面的研究成果进行了综述,对其做了比较、分析,并在前人研究的基础上提出一种时序电路的测试生成方法.     

Why is Combinational ATPG Efficiently Solvable for Practical VLSI Circuits?

Empirical observation shows that practically encountered instances of combinational ATPG are efficiently solvable. However, it has been known for more than two decades that ATPG is an NP-complete problem (Ibarra and Sahni, IEEE Transactions on Computers, Vol. C-24, No. 3, pp. 242–249, March 1975). This work is one of the first attempts to reconcile these seemingly disparate results. We introduce the concept of cut-width of a circuit and characterize the complexity of ATPG in terms of this property. We introduce the class of log-bounded width circuits and prove that combinational ATPG is efficiently solvable on members of this class. The class of of log-bounded width circuits is shown to strictly subsume the class of k-bounded circuits introduced by Fujiwara (International Symposium on Fault-Tolerant Computing, June 1988, pp. 64–69). We provide empirical evidence which indicates that an interestingly large class of practical circuits is expected to have log-bounded width, which ensures efficient solution of ATPG on them.     

Low-power multi-core ATPG to target concurrency

A function-based automatic test pattern generation (ATPG) tool for embedded core testing is presented that reduces test cost and considers test power dissipation of system-on-chip (SoC). Cores are tested concurrently with the use of test functions, as opposed to simple patterns, and by I/O pin allocation on the test access mechanism (TAM) during a compact ATPG process. Turnaround time benefits from pre-existing test vectors, or test functions supplied by the provider of each core. The presented method also targets low-power dissipation by considering the switching activity on the SoC inputs. Experimental results show a significant reduction in the test application time due to the achieved level of concurrency.     

Distributed Test Pattern Generation for Stuck-At Faults in Sequential Circuits

Automatic test pattern generation (ATPG) remains one of themost complex CAD tasks. Therefore, numerous methods were proposed tospeed up ATPG by using parallelism. In this paper, we focus onparallelizing ATPG for stuck-at faults in sequential circuits bycombining fault and search space parallelism. Fault parallelism isapplied to so-called easy-to-detect faults. The main task of thisapproach is to find a best-suited partitioning of the fault list,based on dependencies between faults. For hard-to-detect faultsleft by fault parallelism, search space partitioning is applied,integrating depth-first and breadth-first search. Since a smalltest set size is mandatory for a cheap test and fault parallelismincreases the number of test patterns, test set compaction is donein a post-processing phase. Results show that our approach is notonly capable of achieving potentially superlinear speedups, but alsoimproves test set quality. The parallel environment we use consistsof a network of 100 workstations connected via ethernet.     

基于ATPG的无线接入芯片的可测试性设计

可测试性设计是现代芯片设计中的关键环节,针对无线接入芯片的可测试性设计对测试技术有更高的要求。首先概述可测试性设计和测试向量自动生成理论,然后采用最新的测试向量自动生成技术,根据自行设计的无线接入芯片的内部结构及特点,建立一套无线接入芯片可测试性设计的方案。同时功能测试向量的配合使用,使得设计更为可靠。最终以最简单灵活的方法实现了该芯片的可测试性设计。     

时序电路的形式化证明

对硬件的形式化验证是硬件验证的一个发展方向,形式化验证一个时序电路就是证明电路的实现是否满足他的规格描述.本文提出了用等式逻辑ε的一个公式Ws来表示电路的实现,用Tempura的程序B表示对该电路的特性描述.公式B（∈）P引入来证明电路的正确性,这里P是电路的初始状态,是从Ws中抽取的,另外还要从Ws提取输出等式.这样,一旦证明了B（∈）P,就能证明实现满足规格描述.最后,给出了一个例子来说明此证明方法.     

ATPG and diagnostics for boards implementing boundary scan

The emergence of the IEEE 1149.1 boundary scan standard facilitates structured approaches for board partitioning, allowing test generation and execution on localized logic clusters. This article discusses a study conducted on 1149.1 board designs to examine issues associated with board-level Automatic Test-Pattern Generation (ATPG) and diagnostics.     

Test Set and Fault Partitioning Techniques for Static Test Sequence Compaction for Sequential Circuits

We propose a new static test set compaction method based on a careful examination of attributes of fault coverage curves. Our method is based on two key ideas: (1) fault-list and test-set partitioning, and (2) vector re-ordering. Typically, the first few vectors of a test set detect a large number of faults. The remaining vectors usually constitute a large fraction of the test set, but these vectors are included to detect relatively few hard faults. We show that significant compaction can still be achieved by partitioning faults into hard and easy faults, and compaction is performed only for the hard faults. This significantly reduces the computational cost for static test set compaction without affecting quality of compaction. The second key idea re-orders vectors in a test set by moving sequences that detect hard faults to the beginning of the test set. Fault simulation of the newly concatenated re-ordered test set results in the omission of several vectors so that the compact test set is smaller than the original test set. Experiments on several ISCAS 89 sequential benchmark circuits and large production circuits show that our compaction procedure yields significant test set reductions in low execution times.     

Combining GAs and Symbolic Methods for High Quality Tests of Sequential Circuits

A symbolic fault simulator is integrated in a Genetic Algorithm (GA) environment to perform Automatic Test Pattern Generation (ATPG) for synchronous sequential circuits. In a two phase algorithm test length and fault coverage as well are optimized. Furthermore, not only the Single Observation Time Test Strategy is supported, but also test patterns with respect to the Multiple Observation Time Test Strategy are generated. However, there are circuits that are hard to test using random pattern sequences, even if these sequences are genetically optimized. Thus, deterministic aspects are included in the GA environment to improve fault coverage. Experiments demonstrate that both a priori time consuming strategies, the symbolic simulation approach and the GA, can be combined at reasonable costs: Tests with higher fault coverages and considerably shorter test sequences than previously presented approaches are obtained.     

对全速测试中时序例外路径的处理方法的改进

全速测试（at-speed ATPG）是现代电子设计中必需的一个重要环节。然而由于在做ATPG时,时序信息不完整,所以某些全速测试的向量会激活一些实际系统中不需要那么快时钟速度的路径,这样就会使得这些向量在芯片量产测试中无法通过,导致芯片良率的降低,而这些降低却是由测试的失误造成的。本文主要解释了时序例外路径（timi...     

An Efficient Logic Equivalence Checker for Industrial Circuits

We present our formal combinational logic equivalence checking methods for industry-sized circuits. Our methods employ functional (OBDDs) algorithms for decisions on logic equivalence and structural (ATPG) algorithms to quickly identify inequivalence. The complimentary strengths of the two types of algorithms result in a significant reduction in CPU time. Our methods also involve analytical and empirical heuristics whose impact on performance for industrial designs is considerable. The combination of OBDDs, ATPG, and our heuristics resulted in a decrease in CPU time of up to 80% over OBDDs alone for the circuits we tested. In addition, we describe an algorithm for automatically determining the correspondence between storage elements in the designs being compared.     

基于边缘初始化的竞争网络的矢量量化

用神经网络实现图像矢量量化是一种非常有效的方法。我们对竞争网络的初始化进行改进,提出一种新的基于边缘初始化的竞争网络的矢量量化(EICL),实验表明主客观效果良好。     

基于用户卡的可信执行环境初始化方案

智能终端具备的可信执行环境在加载环节存在加载证书权威性问题.在分析可信执行环境(TEE)初始化架构和初始化方案的基础上,利用信任链技术,设计提出了将运营商用户卡作为可信根,进行智能终端可信执行环境初始化的方案,为电信运营商利用用户卡资源参与可信执行环境的产业链建设提供思路.     

PSpice在高频电子线路中的应用

PSpice软件是目前应用最广的电子线路仿真软件，他可以根据电路的结构和元器件参数对电路进行仿真分析，从而可以方便、精确地判断电路设计的正确性。本文介绍了PSpice软件的功能和特点，利用PSpice对包络检波器进行了仿真，并对包络检波器的两种特有失真（惰性失真和负峰切割失真）进行了观察和分析。通过这一实例较详细地说明如何用PSpice软件对高频电子电路进行仿真与性能分析。从而为高频电子线路的设计和教学提供了一个新的途径。     

基于数据分布特性的聚类中心初始化方法

文中提出了一种新的基于数据局部和全局分布特性的K--Means初始化方法．算法通过对数据空间进行网格化后统计每个网格中数据点数目,选取具有数目局部最大值的网格,再利用距离优化方法全局的估算出K个初始聚类中心．在人工和真实数据集上,进行了与传统的聚类中心初始化算法的比较．实验结果表明,该算法利用局部最大值网格和距离优化的方法估算的聚类中心能够在保持及改善聚类效果的同时,明显减少迭代次数,提高收敛速度．     

Functional Fault Equivalence and Diagnostic Test Generation in Combinational Logic Circuits Using Conventional ATPG

Fault equivalence is an essential concept in digital design with significance in fault diagnosis, diagnostic test generation, testability analysis and logic synthesis. In this paper, an efficient algorithm to check whether two faults are equivalent is presented. If they are not equivalent, the algorithm returns a test vector that distinguishes them. The proposed approach is complete since for every pair of faults it either proves equivalence or it returns a distinguishing vector. The advantage of the approach lies in its practicality since it uses conventional ATPG and it automatically benefits from advances in the field. Experiments on ISCAS’85 and full-scan ISCAS’89 circuits demonstrate the competitiveness of the method and measure the performance of simulation for fault equivalence.     

初始权值优化技术在机器人学习中的应用

针对移动机器人建立了基于BP神经网络的智能避障控制模型,提出了初始权值优化技术,使得样本组与初始权值相匹配,显著地提高了网络的收敛速度.为了提高系统的实时性,文中采用C和汇编语言混合编制控制程序.计算机仿真和实测结果表明该系统具有学习能力强、人机交互效果好等优点.     

基于通用航迹起始模型的一步延迟新算法

针对杂波环境下的快速目标航迹起始问题,提出一种新的航迹起始算法,该算法结合了一种新的航迹起始模型和一步延迟航迹起始算法的优点。其主要思想是在普通航迹起始模型的基础上,增加了一级中间航迹,并采用一步延迟航迹起始算法,利用相邻两个采样周期的量测,计算累积新息,剔除虚假航迹、分裂航迹。仿真结果表明:该算法比一般的逻辑算法设计灵活性更强,虚假航迹起始概率也明显下降。     

GaAs IC CAD及其在通信电路中的应用技术

介绍了自主开发的多个完整实用的 Ga As IC CAD软件 ,包括微波无源元件建模、微波有源器件测试建模、微波毫米波 IC CAD、光电集成电路 CAD、 Ga As VHSIC CAD、微波高速 MCM CAD等 ,并简要介绍了针对 Ga As工艺线的建库工作。以上软件和库已用于多个通信电路的设计。