Noise considerations for mixed‐signal RF IC transceivers

This paper discusses design tradeoffs for mixedsignal radio frequency integrated circuit (RF IC) transceivers for wireless applications in terms of noise, signal power, receiver linearity, and gain. During air wave transmission, the signal is corrupted by channel noise, adjacent interfering users, image signals, and multipath fading. Furthermore, the receiver corrupts the incoming signal due to RF circuit nonlinearity (intermodulation), electronic device noise, and digital switching noise. This tutorial paper gives an overview of the design tradeoffs needed to minimize RF noise in an integrated wireless transceiver. Fundamental device noise and the coupling of switching noise from digital circuits to sensitive analog sections and their impact on RF circuits such as frequency synthesizers are examined. Methods to minimize mixedsignal noise coupling and to model substrate noise effects are presented.     

SIVA: A System for Coverage-Directed State Space Search

We introduce SImulation Verification with Augmentation (SIVA), a tool for coverage-directed state space search on digital hardware designs. SIVA tightly integrates simulation with symbolic techniques for efficient state space search. Specifically, the core algorithm uses a combination of ATPG and BDDs to generate directed input vectors, i.e., inputs which cover behavior not excited by simulation. We also present approaches to automatically generate lighthouses that guide the search towards hard-to-reach coverage goals. Experiments demonstrate that our approach is capable of achieving significantly greater coverage than either simulation or symbolic techniques in isolation.     

The dangers of simplistic delay models

The identification of sensitizable paths and the determination of path delays play key roles in many delay fault testing schemes. In this paper we examine a range of gate delay models with respect to their impact on identifying both sensitizable paths and maximum circuit delays in combinational logic circuits. We provide recommendations on the minimum acceptable model for identifying critical paths, and a minimum acceptable model for determining maximum circuit delays. In particular, we recommend against the use of delay models which fail to distinguish between rise and fall delays. Such models, including the commonly-used unit-delay model, are shown to significantly misrepresent circuit delay behaviour, particularly with respect to critical paths and long false paths.This research is supported by the Natural Sciences and Engineering Research Council of Canada.     

Perspectives on Analytical Modeling of Small Geometry MOSFETs in SPICE for Low Voltage/Low Power CMOS Circuit Design

The present state of the art in analytical MOSFET modeling for SPICE circuit simulation is reviewed, with emphasis on the circuit design usage of these models. It is noted that the model formulation represents an upper limit of what is possible from any type of model, but that good parameter extraction is required to most closely approach that limit. The individual model types presently in common use are examined, with discussion of the behavior of each model, its strengths and weaknesses, its applicability to certain types of circuits, and criteria that a circuit design consumer can employ to judge a model before using it for circuit design. Some related issues, such as node charge and gate capacitance modeling, charge conservation, and statistical simulation of process variations, are also evaluated. Finally, new trends, directions, and requirements of MOSFET modeling for circuit simulation are considered.     

Predictive Caching Strategy for On-Demand Routing Protocols in Wireless Ad Hoc Networks

Route caching strategy is important in on-demand routing protocols in wireless ad hoc networks. While high routing overhead usually has a significant performance impact in low bandwidth wireless networks, a good route caching strategy can reduce routing overheads by making use of the available route information more efficiently. In this paper, we first study the effects of two cache schemes, link cache and path cache, on the performance of on-demand routing protocols through simulations based on the Dynamic Source Routing (DSR) protocol. Since the path cache DSR has been extensively studied, we focus in this paper on the link cache DSR in combination with timer-based stale link expiry mechanisms. The effects of different link lifetime values on the performance of routing protocol in terms of routing overhead, packet delivery ratio and packet latency are investigated. A caching strategy incorporating adaptive link timeout is then proposed, which aims at tracking the optimal link lifetime under various node mobility levels by adaptively adjusting the link lifetime based on the real link lifetime statistics. The performance of the proposed strategy is then compared with the conventional path cache DSR. The results show that without a timeout mechanism, a link cache scheme may suffer severe performance degradation due to the use of broken routes, while the proposed adaptive link cache strategy achieves significantly improved performance by reducing the routing overhead when the network traffic load is high.     

β-bit serial/parallel multipliers

A generalized -bit least-significant-digit (LSD) first, serial/parallel multiplier architecture is presented with 1n wheren is the operand size. The multiplier processes both the serial input operand and the double precision product -bits per clock cycle in an LSD first, synchronous fashion. The complete two's complement double precision product requires 2n/ clock cycles. This generalized architecture creates a continuum of multipliers between traditional bit-serial/parallel multipliers (=1) and fully-parallel multipliers (=n). -bit serial/parallel multipliers allow anoptimized integrated circuit arithmetic to be designed based on a particular application's area, power, throughput, latency, and numerical precision constraints.This project was pratically funded by the UCSD-NSF I/UCR Center on Ultra-High Speed Intergrated Circuits and Systems.     

Floor acquisition multiple access (FAMA) in single‐channel wireless networks

The FAMANCS protocol is introduced for wireless LANs and adhoc networks that are based on a single channel and asynchronous transmissions (i.e., no time slotting). FAMANCS (for floor acquisition multiple access with nonpersistent carrier sensing) guarantees that a single sender is able to send data packets free of collisions to a given receiver at any given time. FAMANCS is based on a threeway handshake between sender and receiver in which the sender uses nonpersistent carrier sensing to transmit a requesttosend (RTS) and the receiver sends a cleartosend (CTS) that lasts much longer than the RTS to serve as a busy tone that forces all hidden nodes to back off long enough to allow a collisionfree data packet to arrive at the receiver. It is shown that carrier sensing is needed to support collisionfree transmissions in the presence of hidden terminals when nodes transmit RTSs asynchronously. The throughput of FAMANCS is analyzed for singlechannel networks with and without hidden terminals; the analysis shows that FAMANCS performs better than ALOHA, CSMA, and all prior proposals based on collision avoidance dialogues (e.g., MACA, MACAW, and IEEE 802.11 DFWMAC) in the presence of hidden terminals. Simulation experiments are used to confirm the analytical results.     

Biasing a differential pair in low-voltage analog circuits: a systematic approach

This paper deals with a systematic approach to the common mode and the differential mode biasing of a differential transistor pair. Four different variants will be shown, two of these variants show practical importance; a practical circuit of one of these variants turns out to be the traditional long-tailed pair. This variant is mainly suited, if the input signal operates at voltage level, whereas another variant has great advantages if operation at current level occurs. Besides, the latter variant turns out to be very favorable in circuits operating with a single low supply voltage. Two practical circuits based on this variant are given.     

Time‐varying modeling of a nonstationary signal

In this paper, a method for modeling a nonstationary signal using timevarying parameters by considering that the signal is generated by a linear, timevarying (LTV) system with a stationary white noise input is presented. This method is based on the Wold–Cramer (WC) representation of a nonstationary signal. Because the relationship between the generalized transfer function of an LTV system and the timevarying coefficients of the difference equation of a discretetime system is not addressed so far in the literature, therefore, in this paper a solution to this problem is proposed. A simple relationship between the system generalized transfer function and the timevarying parameters of the system is derived, then an MLS algorithm is developed to solve for the system timevarying parameters. Computer simulation illustrating the effectiveness of our algorithm is presented.     

A Performance Analysis of Pragmatic MPSK TCM

The performance of 8-PSK, 16-PSK and 32-PSK TCM are examined in the additive white gaussian noise (AWGN), Rician fading and Rayleigh fading channels. The TCM is implemented using the Pragmatic Approach to TCM based on the common rate , constraint length 7, 64-state convolutional code. The analytic performance model has been enhanced to account for the unencoded bit(s) resulting from implementation of TCM using the Pragmatic Approach. Averaging of the Euclidean error weight profiles is also employed. The results provide an improved upper bound on published data from simulations and measurements. The results are then employed to facilitate the evaluation of a concatenated Reed-Solomon (RS) MPSK TCM code, as well as, TCM with diversity in the form of symbol repetition.     

A scalable wireless virtual LAN

This paper presents a Wireless Virtual Local Area Network (WVLAN) to support mobility in IPoverATM local area networks. Mobility is handled by a joint ATMlayer handoff for connection rerouting and MAClayer handoff for location tracking, such that the effects of mobility are localized and transparent to the higherlayer protocols. Different functions, such as Address Resolution Protocol (ARP), mobile location, and ATM connection admission are combined to reduce protocol overhead and frontend delay for connectionless packet transmission in connectionoriented ATM networks. The proposed WVLAN, through the use of ATM technology, provides a scalable wireless virtual LAN solution for IP mobile hosts.     

Consistency management in Deno

We describe a new replicatedobject protocol designed for use in mobile and weaklyconnected environments. The protocol differs from previous protocols in combining epidemic information propagation with voting, and in using fixed perobject currencies for voting. The advantage of epidemic protocols is that data movement only requires pairwise communication. Hence, there is no need for a majority quorum to be available and simultaneously connected at any single time. The protocols increase availability by using voting, rather than primarycopy or primarycommit schemes. Finally, the use of perobject currencies allows voting to take place in an entirely decentralized fashion, without any server having complete knowledge of group membership. We show that currency allocation can be used to implement diverse policies. For example, uniform currency distributions emulate traditional voting schemes, while allocating all currency to a single server emulates a primarycopy scheme. We present simulation results showing both schemes, as well as the performance advantages of using currency proxies to temporarily reallocate currency during planned disconnections. Furthermore, we discuss an initial design of the underlying replicatedobject system and present a basic API.     

The Complex Bootstrap Algorithm for Blind Separation of QAM Multiuser CDMA Signals

The bootstrap separator for multiuser signals is principally composed of cancelers, each one using the output of the other cancelers to facilitate control of its adaptive weight. In fact, such a structure performs as a signal separator rather than an interference canceler. Since for its separation there is no need for a reference signal (as in LMS cancelers), it is sometimes justifiably called a Blind Separator. However, for its operation the bootstrap separator requires a signal distinguisher termed discriminator. The algorithm was used in the past in applications such as dually polarized satellite communications and microwave terrestrial links. It was particularly reported for multiuser CDMA signal separating, with the signum function as discriminator. Especially for QAM signals, complex presentation is important. Therefore, we will concentrate in this report on what we call the Complex Bootstrap Algorithm. It is an extension to the previously reported bootstrap structure of [5]. We will examine its performance and emphasize the hardware saving in its implementation, and the ease of using it in simulation.     

Microsystems Engineering: A Great Stride Forward in Microelectronics Technology

The development of new-generation technological and engineering concepts by the example of microsystems technology and microsystems engineering approaches is considered.     

Fault Models and Test Generation for OpAmp Circuits—The FFM

The analog VLSI technology processes are reaching the matureness, nevertheless, there is a big constraint, regarding their use on complex electronic products: the test. The Design for Testability paradigm was developed to permit the test plan implementation early in the design cycle. However to succeed onto this strategy, the fault simulation should be carried out in order to evaluate appropriate test patterns, fault grade and so forth. Consequently adequate fault models must be established. Due to the lack of fault models, suitable to fault simulation on OpAmps, we propose in this work a methodology for Functional Fault Modeling-FFM, and some methods for test generation. A fault dictionary for OpAmps is built and a procedure for compact test vector construction is proposed. The results have shown that high level OpAmp requirements, as slew-rate, common mode rejection ration etc., can be checked by this approach with good compromise between the fault modeling problem, the analog nature of the circuit and the circuit complexity by itself.     

A 1.2 V Rail-to-Rail Analog CMOS Rank-Order Filter with k-WTA Capability

In this paper, we design a rank-order filter with k-WTA capability for 1.2 V supply voltage. The circuit can find a rank order among a set of input voltages by setting different binary signals. Moreover, without modifying the circuit, the k-WTA function can be easily configured. The circuit has been designed using a 0.5 m DPDM CMOS technology. Seven input voltages are used to verify the performance of the circuit. The results of HSPICE post-layout simulation show that the response time of the circuit is 10 s for each rank-order operation, the input dynamic range is rail-to-rail, and the resolution is 10 mV for 1.2 V supply voltage. An experimental chip has been fabricated, in which accuracy of the comparator is measured as 40 mV for low-voltage operation. The dynamic power dissipation of the chip is 550 W.     

1 V All-MOS ΣΔ A/D Converters in the Log-domain

This paper presents novel low-voltage all-MOS analog circuit techniques for the synthesis of oversampling A/D converters. The new approach exploits the possibilities of Log-domain processing by using the MOSFET in subthreshold operation. Based on this strategy, a complete set of very low-voltage (down to 1 V) low-power (below 100 W) all-MOS basic building blocks is proposed. The resulting analog circuit techniques allow the integration of A/D converters for low-frequency (below 100 KHz) applications in digital CMOS technologies. Examples are given for a standard 0.35 m VLSI process.     

On the convergence rate ofs-numbers of compact Hankel operators

It is well known that the sequence ofs-numbers {s_n},n=0, 1,..., of a compact operator, and particularly a compact Hankel operator =[h _j+k –1], converges monotonically to zero. Since the (n + 1)sts-number s_n measures the error ofL (¦z¦=1) approximation, modulo an additive H function, by nth degree proper rational functions whose poles are restricted to ¦z¦ < 1, it is very important to study how fast {s _n } converges to zero. It is not difficult to see that ifh _n =O(n ^–), for some > 1, thens _n =O(n ^–). In this paper we construct, for any given sequence _n 0, a compact Hankel operator such thats _{n n} for alln.The research of C. K. Chui was supported by the SDIO/IST managed by the U.S. Army under Contract No. DAAL-03-87-K-0025, and by the NSF under Grant No. DMS-8901345. X. Li's research was supported by the SDIO/IST managed by the U.S. Army under Contract No. DAAL-03-87-K-0025. The research of J. D. Ward was supported by the NSF under Grant No. DMS-8901345.     

mPERSONA: Personalized Portals for the Wireless User: An Agent Approach

The needs of the wireless and mobile user regarding information access and services are quite different than those of the desktop user. This need is not about browsing the Web but about receiving personalized services that are highly sensitive to the immediate environment and requirements of the user. Personalization appears to be the most appropriate solution to this need. It comes into aid by creating personalized portals that are specific for the wireless user, which (a) are focus on the local content and (b) directly tones down factors that break up the functionally of the Internet/wireless services when viewed through wireless devices; factors like the click count, user response time (the choice factor) and the size of the wireless network traffic. In this paper we present a flexible personalization system for the wireless user that takes into consideration user mobility, the local environment and the user and device profile. The system utilizes the various characteristics of mobile agents to support flexibility, scalability, modularity and user mobility. We present metrics appropriate to the wireless environment, and an initial performance evaluation indicating improvement ranging from 33% up to, for certain metrics, 60%.     

Order selection statistical test for nonstationary AR models

A new statistical test for selecting the order of a nonstationary AR modelyk is presented based on the predictive least-squares principle. This test is of the same order as the accumulated cost function _n = _k=1 ⁿ ( _k ^* – _k )²;i.e., ^* wherey _k ^* is the predictive least-square estimate. It is constructed to show how many times the integrated AR processy _k is differenced in order to obtain a stationary AR process given that the exact order of the process is unknown.