Performance enhancement of strained-Si MOSFETs fabricated on a chemical-mechanical-polished SiGe substrate

Chemical-mechanical-polishing (CMP) was used to smooth the surface of a SiGe substrate, on which strained-Si n- and p-MOSFETs were fabricated. By applying CMP after growing the SiGe buffer layer, the surface roughness was considerably reduced, namely, to 0.4 nm (rms). A strained-Si layer was then successfully grown on the CMP-treated SiGe substrate. The fabricated strained-Si MOSFETs showed good turn-off characteristics, (i.e., equivalent to those of Si control devices). Moreover, capacitance-voltage (CV) measurements revealed that the quality of the gate oxide of the strained-Si devices was the same as that of the Si control devices. Flat-band and threshold voltages of the strained-Si devices were different from those of the Si control devices mainly due to band discontinuity. Electron and hole mobilities of strained-Si MOSFETs under a vertical field up to 1.5 MV/cm increased by 120% and 42%, respectively, compared to the universal mobility. Furthermore, current drive of the n- and p-MOSFETs (L/sub eff//spl ges/0.3 /spl mu/m) was increased roughly by 70% and 50%, respectively. These improvements in characteristics indicate that CMP of the SiGe substrate is a critical technique for developing high-performance strained-Si CMOS.     

Tradeoff between mobility and subthreshold characteristics in dual-channel heterostructure n- and p-MOSFETs

The mobility and subthreshold characteristics of TiN-gate, dual-channel heterostructure MOSFETs consisting of strained-Si-Si/sub 0.4/Ge/sub 0.6/ on relaxed Si/sub 0.7/Ge/sub 0.3/ are studied for strained-Si cap layer thicknesses ranging from 3 to 10 nm. The thinnest Si cap sample (3 nm) yields the lowest subthreshold swing (80 mV/dec) and the highest hole mobility enhancement (2.3X at a vertical effective field of 1 MV/cm). N-MOSFETs show the expected electron mobility enhancement (1.8X) for 10- and 5-nm-thick Si cap samples, which reduces to 1.6X for an Si cap thickness of 3 nm. For Si cap and gate oxide thicknesses both equal to 1 nm, simulations predict a moderate degradation in p-MOSFET subthreshold swing, from 73 to 85 mV/dec, compared to that for the Si control.     

Scalability of strained-Si nMOSFETs down to 25 nm gate length

Strained-Si nMOSFETs with a standard polysilicon gate process were fabricated down to 25 nm gate length with well-behaved characteristics and small difference in short channel effects. The performance enhancement degrades linearly as the gate length becomes shorter, due to not only the parasitic resistance but also heavy halo implant. Thus the key integration issues are how to manage threshold difference and As diffusion without excess doping. With comparable doping and well controlled parasitic resistance, up to 45% improvement in drive current is predicted for sub-50 nm gate length strained-Si nMOSFETs on the Si/sub 0.8/Ge/sub 0.2/ substrate. In this work approximately 45% enhancement is in fact demonstrated for 35 nm gate length devices, through advanced channel engineering and implementation of metal gates.     

A physically based analytical model for the threshold voltage of strained-Si n-MOSFETs

A physically based analytic model for the threshold voltage V/sub t/ of long-channel strained-Si--Si/sub 1-x/Ge/sub x/ n-MOSFETs is presented and confirmed using numerical simulations for a wide range of channel doping concentration, gate-oxide thicknesses, and strained-Si layer thicknesses. The threshold voltage is sensitive to both the electron affinity and bandgap of the strained-Si cap material and the relaxed-Si/sub 1-x/Ge/sub x/ substrate. It is shown that the threshold voltage difference between strained- and unstrained-Si devices increases with channel doping, but that the increase is mitigated by gate oxide thickness reduction. Strained Si devices with constant, high channel doping have a threshold voltage difference that is sensitive to Si cap thickness, for thicknesses below the equilibrium critical thickness for strain relaxation.     

Scaling fully depleted SOI CMOS

Quasi-two-dimensional (2-D) device analyses, 2-D numerical device simulations, and circuit simulations of nanoscale conventional, single-gate fully depleted (FD) silicon-on-insulator (SOI) CMOS are done to examine the scalability and performance potential of the technology. The quasi-2-D analyses, which can apply to double-gate devices as well, also provide a simple expression to estimate the effective channel length (L/sub eff/) of FD/SOI MOSFETs. The insightful results show that threshold-voltage control via channel doping and polysilicon gates is not a viable option for extremely scaled FD/SOI CMOS, and hence that undoped channels and metal gate(s) with tuned work function(s) must be employed. Quantitative as well as qualitative insights gained on the short-channel effects reveal the need for ultrathin films (t/sub Si/ < 10 nm) for L/sub eff/ < 50 nm. However, the implied manufacturing burden, compounded by effects of carrier-energy quantization for ultrathin t/sub Si/, forces a pragmatic limit on t/sub Si/ of about 5 nm, which in turn limits the scalability to L/sub eff/ = 25-30 nm. Unloaded CMOS-inverter ring-oscillator simulations, done with our process/physics-based compact model (UFDG) in SPICE3, show very good performance for L/sub eff/ = 35 nm, and suggest viable technology designs for low-power as well as high-performance applications. These simulations also reveal that moderate variations in t/sub Si/ can be tolerated, and that the energy quantization significantly influences the scaled-technology performance and hence must be properly accounted for in optimal FD/SOI MOSFET design.     

Advanced SOI p-MOSFETs with strained-Si channel onSiGe-on-insulator substrate fabricated by SIMOX technology

We have newly developed an advanced SOI p-MOSFET with strained-Si channel on insulator (strained-SOI) structure fabricated by SIMOX (separation-by-implanted-oxygen) technology. The characteristics of this strained-SOI substrate and electrical properties of strained-SOI MOSFETs have been experimentally studied. Using strained-Si/relaxed-SiGe epitaxy technology and usual SIMOX process, we have successfully formed the layered structure of fully-strained-Si (20 nm)/fully-relaxed-SiGe film (290 nm) on uniform buried oxide layer (85 nm) inside SiGe layer. Good drain current characteristics have been obtained in strained-SOI MOSFETs. It is found that the hole mobility is enhanced in strained-SOI p-MOSFETs, compared to the universal hole mobility in an inversion layer and the mobility of control SOI p-MOSFETs. The enhancement of the drive current has been kept constant down to 0.3 μm of the effective channel length     

A 90-nm logic technology featuring strained-silicon

A leading-edge 90-nm technology with 1.2-nm physical gate oxide, 45-nm gate length, strained silicon, NiSi, seven layers of Cu interconnects, and low-/spl kappa/ CDO for high-performance dense logic is presented. Strained silicon is used to increase saturated n-type and p-type metal-oxide-semiconductor field-effect transistors (MOSFETs) drive currents by 10% and 25%, respectively. Using selective epitaxial Si/sub 1-x/Ge/sub x/ in the source and drain regions, longitudinal uniaxial compressive stress is introduced into the p-type MOSEFT to increase hole mobility by >50%. A tensile silicon nitride-capping layer is used to introduce tensile strain into the n-type MOSFET and enhance electron mobility by 20%. Unlike all past strained-Si work, the hole mobility enhancement in this paper is present at large vertical electric fields in nanoscale transistors making this strain technique useful for advanced logic technologies. Furthermore, using piezoresistance coefficients it is shown that significantly less strain (/spl sim/5 /spl times/) is needed for a given PMOS mobility enhancement when applied via longitudinal uniaxial compression versus in-plane biaxial tension using the conventional Si/sub 1-x/Ge/sub x/ substrate approach.     

FABRICATION OF STRAINED-Si CHANNEL P-MOSFET’s ON ULTRA-THIN SiGe VIRTUAL SUBSTRATES

In the ultra-thin relaxed SiGe virtual substrates, a strained-Si channel p-type Metal Oxide Semiconductor Field Effect Transistor （p-MOSFET） is presented. Built on strained-Si/240nm relaxed-Si0.8 Ge0.2/ 100nm Low Temperature Si （LT-Si）/10nm S i buffer was grown by Molecular Beam Epitaxy （MBE）, in which LT-Si layer is used to release stress of the SiGe layer and made it relaxed. Measurement indicates that the strained-Si p-MOSFET＇s （L=4.2μm） transconductance and the hole mobility are enhanced 30% and 50% respectively, compared with that of conventional bulk-Si. The maximum hole mobility for strained-Si device is 140cm^2/Vs. The device performance is comparable to devices achieved on several μm thick composition graded buffers and relaxed-SiGe layer virtual substrates.     

Fabrication of Strained-Si/Strained-Ge Heterostructures on Insulator

Ultrathin strained-Si/strained-Ge heterostructures on insulator have been fabricated using a bond and etch-back technique. The substrate consists of a trilayer of 9 nm strained-Si/4 nm strained-Ge/3 nm strained-Si on a 400-nm-thick buried oxide. The epitaxial trilayer structure was originally grown pseudomorphic to a relaxed Si_0.5Ge_0.5 layer on a donor substrate. Raman analysis of the as-grown and final transferred layer structures indicates that there is little change in the strain in the Si and Ge layers after layer transfer. These ultrathin Si and Ge films have very high levels of strain (∼1.8% biaxial tension and 1.4% compression, respectively), and are suitable for enhanced-mobility field-effect transistor applications.     

A logic nanotechnology featuring strained-silicon

Strained-silicon (Si) is incorporated into a leading edge 90-nm logic technology . Strained-Si increases saturated n-type and p-type metal-oxide-semiconductor field-effect transistors (MOSFETs) drive currents by 10 and 25%, respectively. The process flow consists of selective epitaxial Si/sub 1-x/Ge/sub x/ in the source/drain regions to create longitudinal uniaxial compressive strain in the p-type MOSFET. A tensile Si nitride-capping layer is used to introduce tensile uniaxial strain into the n-type MOSFET and enhance electron mobility. Unlike past strained-Si work: 1) the amount of strain for the n-type and p-type MOSFET can be controlled independently on the same wafer and 2) the hole mobility enhancement in this letter is present at large vertical electric fields, thus, making this flow useful for nanoscale transistors in advanced logic technologies.     

双栅双应变沟道全耗尽SOI MOSFETs的特性分析

提出了一种全新的器件结构--双栅双应变沟道全耗尽SOI MOSFETs,模拟了沟道长度为25nm时器件的电学特性.工作在单栅模式下,应变沟道(Ge=0.3)驱动能力与体Si沟道相比,nMOS提高了43%,pMOS提高了67%;工作在双栅模式下,应变沟道(Ge=0.3)与体Si沟道相比较,驱动电流的提高nMOS为31%,pMOS为60%.仿真结果表明,双栅模式比单栅模式有更为陡直的亚阈值斜率,更高的跨导以及更强的抑制短沟道效应的能力.综合国内外相关报道,该结构可以在现今工艺条件下实现.     

Thin-film strained-SOI CMOS Devices-physical mechanisms for reduction of carrier mobility

We have examined physical mechanisms responsible for the reduction in both electron and hole mobility in strained-silicon-on-insulator (SOI) CMOS devices with thin strained-Si layers. A slight decrease in the electron mobility with thinning strained-Si layers is attributable to the quantum-mechanical confinement effect of the inversion layer electrons, originating in the conduction band offset of the strained-Si layers. Also, the diffusion of Ge atoms into the SiO/sub 2//strained-Si interface is found to generate interface states near the valence band edge, leading to the reduction in hole mobility in the lower E/sub eff/ region through Coulomb scattering. Moreover, the decrease in hole mobility enhancement in both thin and thick strained-Si structures at the higher electric field is caused by the reduction of the energy splitting between the heavy and the light hole bands, with an increase in the electric field. Based on considerations of these factors affecting the mobility reduction, the strained-Si thickness and the Ge content have been designed to realize high-speed strained-SOI CMOS under the 90-nm technology and beyond.     

Implementation of both high-hole and electron mobility in strained Si/strained Si/sub 1-y/Ge/sub y/ on relaxed Si/sub 1-x/Ge/sub x/ (x

Jongwan Jung Lee  M.L. Shaofeng Yu Fitzgerald  E.A. Antoniadis  D.A. 《Electron Device Letters, IEEE》2003,24(7):460-462

High-performance nMOSFETs using a novel strained Si/SiGe CMOS architecture

Performance enhancements of up to 170% in drain current, maximum transconductance, and field-effect mobility are presented for nMOSFETs fabricated with strained-Si channels compared with identically processed bulk Si MOSFETs. A novel layer structure comprising Si/Si/sub 0.7/Ge/sub 0.3/ on an Si/sub 0.85/Ge/sub 0.15/ virtual substrate (VS) offers improved performance advantages and a strain-compensated structure. A high thermal budget process produces devices having excellent on/off-state drain-current characteristics, transconductance, and subthreshold characteristics. The virtual substrate does not require chemical-mechanical polishing and the same performance enhancement is achieved with and without a titanium salicide process.     

The impact of uniform strain applied via bonding onto plastic substrate on MOSFET performance

For the first time, this letter presents a novel post-backend strain applying technique and the study of its impact on MOSFET device performance. By bonding the Si wafer after transistor fabrication onto a plastic substrate (a conventional packaging material FR-4), a biaxial-tensile strain (/spl sim/0.026%) was achieved globally and uniformly across the wafer due to the shrinkage of the bonded adhesive. A drain-current improvement (average /spl Delta/I/sub d//I/sub d//spl sim/10%) for n-MOSFETs uniformly across the 8-in wafer is observed, independent of the gate dimensions (L/sub g//spl sim/55 nm -0.530 /spl mu/m/W /spl sim/2-20 /spl mu/m). The p-MOSFETs also exhibited I/sub d/-improvement by /spl sim/7% under the same biaxial-tensile strain. The strain impact on overall device characteristics was also studied, including increased gate-induced drain leakage and short-channel effects.     

采用低温Si技术的Si/SiGe异质结P-MOSFET

针对S i/S iG e p-M O SFET的虚拟S iG e衬底厚度较大(大于1μm)的问题,采用低温S i技术在S i缓冲层和虚拟S iG e衬底之间M BE生长低温-S i层。S iG e层应力通过低温-S i层释放,达到应变弛豫。XRD和AFM测试表明,S i0.8G e0.2层厚度可减薄至300 nm,其弛豫度大于85%,表面平均粗糙度仅为1.02 nm。试制出应变S i/S iG e p-M O SFET器件,最大空穴迁移率达到112 cm2/V s,其性能略优于目前多采用1μm厚虚拟S iG e衬底的器件。     

Simulation study of the 20 nm gate-length Ge implant-free quantum well p-MOSFET

In this paper a drift diffusion simulation study of a 20 nm gate-length implant-free quantum well germanium p-MOSFET is presented, which covers the impact of mobility, velocity saturation and density of interface states on the transistor performance. The parasitic gate capacitance was also studied. The simulations show that the 20 nm gate-length implant-free quantum-well transistor design has good electrostatic integrity and performance potential.     

Low noise RF MOSFETs on flexible plastic substrates

We report a low minimum noise figure (NF/sub min/) of 1.1 dB and high associated gain (12 dB at 10 GHz) for 16 gate-finger 0.18-/spl mu/m RF MOSFETs, after thinning down the Si substrate to 30 /spl mu/m and mounting it on plastic. The device performance was improved by flexing the substrate to create stress, which produced a 25% enhancement of the saturation drain current and lowered NF/sub min/ to 0.92 dB at 10 GHz. These excellent results for mechanically strained RF MOSFETs on plastic compare well with 0.13-/spl mu/m node (L/sub g/=80 nm) devices.     

低温硅结合离子注入技术制备应变Si材料

为制作应变硅MOS器件,给出了一种制备具有高表面质量和超薄SiGe虚拟衬底应变Si材料的方法。通过在Si缓冲层与赝晶Si0.8Ge0.2之间设置低温硅（LT-Si）层,由于失配位错限制在LT-Si层中且抑制线位错穿透到Si0.8Ge0.2层,使表面粗糙度均方根值（RMS）为1.02nm,缺陷密度系106cm-2。又经过P+注入和快速热退火,使Si0.8Ge0.2层的应变弛豫度从85.09%增加到96.41%,且弛豫更加均匀。同时,RMS（1.1nm）改变较小,缺陷密度基本没变。由实验结果可见,采用LT-Si层与离子注入相结合的方法,可以制备出满足高性能器件要求的具有高弛豫度、超薄SiGe虚拟衬底的高质量应变Si材料。     

La/sub 2/O/sub 3//Si/sub 0.3/Ge/sub 0.7/ p-MOSFETs with high hole mobility and good device characteristics

We have studied high-k La/sub 2/O/sub 3/ p-MOSFETs on Si/sub 0.3/Ge/sub 0.7/ substrate. Nearly identical gate oxide current, capacitance density, and time-dependent dielectric breakdown (TDDB) are obtained for La/sub 2/O/sub 3//Si and La/sub 2/O/sub 3//Si/sub 0.3/Ge/sub 0.7/ devices, indicating excellent Si/sub 0.3/Ge/sub 0.7/ quality without any side effects. The measured hole mobility in nitrided La/sub 2/O/sub 3//Si p-MOSFETs is 31 cm/sup 2//V-s and comparable with published data in nitrided HfO/sub 2//Si p-MOSFETs. In sharp contrast, a higher mobility of 55 cm/sup 2//V-s is measured in La/sub 2/O/sub 3//Si/sub 0.3/Ge/sub 0.7/ p-MOSFET, an improvement by 1.8 times compared with La/sub 2/O/sub 3//Si control devices. The high mobility in Si/sub 0.3/Ge/sub 0.7/ p-MOSFETs gives another step for integrating high-k gate dielectrics into the VLSI process.