Optimized sensing scheme of DRAMs

The half-V_cc sensing scheme of CMOS dynamic RAMs (DRAMs) has been analyzed. It has been found that fluctuations of the cell-plate bias must be taken into account since they can degrade the sense signal. An improvement is possible by connecting the bit lines to the cell plate and its half-V_cc generator during precharge. Optimum performance of the sense amplifier is achieved if the PMOS and NMOS latches are activated simultaneously. The advantages are: (1) the sensitivity is improved due to the elimination of the offset contribution caused by unmatched capacitive loads; (2) the sensing speed is enhanced due to faster sense signal amplification; and (3) the peak current is reduced since the NMOS latch does not lower the voltage level of both bit line and reference bit line     

High-speed sensing scheme for CMOS DRAMs

A significant improvement in sensing speed over the half-V_DD bit-line precharge sensing scheme is obtained by precharging the bit line to approximately 2/3 V_DD. The 2/3-V_DD sensing scheme also results in higher-bit-line capacitance, asymmetrical bit-line swing, and higher power consumption. However, the speed advantage of 2/3-V_DD sensing may outweigh the disadvantages and can significantly improve DRAM performance. For the unboosted word-line case, symmetrical bit-line swing can be retained by limiting the bit-line downward voltage swing through a clamping circuit added to the sense amplifier, resulting in almost no loss of stored charge in a cell. The authors show that the 2/3-V_DD sensing with a limited bit-line swing has several distinct advantages over the half-V_DD sensing scheme and is particularly suitable for high-performance high density CMOS DRAMs     

Cell-plate-line/bit-line complementary sensing (CBCS) architecturefor ultra low-power DRAMs

In the realization of gigabit scale DRAMs, one of the most serious problems is how to reduce the array power consumption without degradation of the operating margin and other characteristics. This paper proposes a new array architecture called cell-plate-line/bit-line complementary sensing (CBCS) architecture which realizes drastic array power reduction for both read/write operations and refresh operations, and develops a large readout voltage difference on the bit-line and cell-plate-line. For read/write operations, the array power reduces to only 0.2%, and for refresh operations becomes 36%, This architecture requires no unique process technology and no additional chip area. Using a test device with a 64-Mb DRAM process, the basic operation has been successfully demonstrated. This new memory core design realizes a high-density DRAM suitable for the 1-Gb level and beyond with power consumption significantly reduced     

A dual-phase-controlled dynamic latched amplifier for high-speedand low-power DRAMs

A dual-phase-controlled dynamic latched (DDL) amplifier for a differential data transfer scheme designed to achieve both high speed and low power in DRAMs is described. This circuit reduces the excessive operating margin caused by device fluctuations by using a pair of dynamic latched amplifiers, controlled by a dual-phase clock, to automatically correct the output data. Two circuit technologies are used in the DDL amplifier to achieve 200-MHz operation in a 1-Gb SDRAM using 0.13-μm technology: a cycle-time-progressive control circuit that increases the operating frequency and a shared DDL amplifier technique that reduces the area penalty of the DDL amplifier. These techniques and circuits reduce the access time to 10 ns, which is 1.2 ns less than that of the conventional dynamic amplifier, while also reducing the operating current to less than 10% that of the static amplifier     

Half-V/SUB DD/ bit-line sensing scheme in CMOS DRAMs

A sensing scheme in which the bit line is precharged to half V/SUB DD/ is introduced for CMOS DRAMs. The proposed circuitry uses a PMOS memory array and incorporates the following features: (1) a complementary sense amplifier consisting of NMOS and PMOS cross-coupled pairs; (2) clocked pulldown of the latching node; (3) complementary clocking of the PMOS pullup; (4) full-sized dummy cell generation of reference potential for sensing; (5) shorting transistor to equalize precharge potential of bit lines; and (6) depletion NMOS decoupling transistors for multiplexing bit lines. The study shows that the half-V/SUB DD/ bit-line sensing scheme has several unique advantages, especially for high-performance high-density CMOS DRAMs, which compared to the full-V/SUB DD/ bit-line sensing scheme used for NMOS memory arrays or the grounded bit-line sensing scheme for PMOS arrays in CMOS DRAMs.     

A low-power 256-Mb SDRAM with an on-chip thermometer and biased reference line sensing scheme

In order to achieve small self-refresh current (ICC/sub 6/), the first 256-Mb SDRAM with an on-chip thermometer in the DRAM industry is implemented with a new self-refresh scheme. In addition, the biased reference line (BRL) sensing scheme improving refresh characteristics is proposed to increase refresh period and reduce ICC/sub 6/. The on-chip thermometer is characterized by a small area of 0.43 mm/sup 2/, low power consumption with less than 1-/spl mu/A average current, and good accuracy of 5.85/spl deg/C in the worst case. Good accuracy is achieved by incorporating many generic design techniques, including offset-free operational amplifiers and the chopping method, and small area is achieved by applying DRAM cell technology to integrating analog-digital converter. A 75% reduction in ICC/sub 6/ at 60/spl deg/C is achieved with on-chip thermometer and BRL sensing scheme improving 30% of refresh characteristic.     

A low-power content-addressable memory (CAM) using pipelined hierarchical search scheme

This paper presents two techniques to reduce power consumption in content-addressable memories (CAMs). The first technique is to pipeline the search operation by breaking the match-lines into several segments. Since most stored words fail to match in their first segments, the search operation is discontinued for subsequent segments, hence reducing power. The second technique is to broadcast small-swing search data on less capacitive global search-lines, and only amplify this signal to full swing on a shorter local search-line. As few match-line segments are active, few local search-lines will be enabled, again saving power. We have employed the proposed schemes in a 1024/spl times/144-bit ternary CAM in 1.8-V 0.18-/spl mu/m CMOS, illustrating an overall power reduction of 60% compared to a nonpipelined, nonhierarchical architecture. The ternary CAM achieves a 7-ns search cycle time at 2.89fJ/bit/search.     

A multiple clocking scheme for low-power RTL design

This paper presents a resource allocation technique to design low-power register-transfer-level datapaths. The basis of this technique is to use a multiple clocking scheme of n nonoverlapping clocks, by dividing the frequency f of a single clock into n cycles, to partition the circuit into n disjoint modules and assign each module to a distinct clock, and to operate each module only during its corresponding duty cycle, thus clocking each module by a frequency f/n to reduce power. However, the overall effective frequency of the circuit remains f, i.e., the single clock frequency. Further power reduction is also obtained by tradeoffs between voltage, power, and delay across multiple clock partitions. Power savings up to 50% of the proposed multiple clocking scheme in comparison to single gated clock designs are also reported     

A well-synchronized sensing/equalizing method for sub-1.0-Voperating advanced DRAMs

Proposes an advanced DRAM array driving technique which can achieve low-voltage operation, a well-synchronized sensing and equalizing method. This method sets the DRAM array free from the body effect, achieves a small influence of the short channel effect, and reduces the leakage current. The sense and restore amplifier and equalizer can operate rapidly under a low-voltage operating condition such as 1.0 V V_CC. Therefore, one can make determining the V _th easy for the satisfaction of the high-speed, the low-power dissipation, and a simple device structure. The well-synchronized sensing and equalizing method is applicable to low-voltage operating DRAMs with capacity of 256 Mbits and more     

A novel spectrum sensing scheme with sensing time optimization for energy-efficient CRSNs

Wireless Networks - The cognitive radio technology enables secondary users (SUs) to occupy licensed bands when primary users (PUs) are not occupy them. Spectrum sensing is a key technology for SUs...     

A low-voltage low-power threshold voltage monitor for CMOS process sensing

In this paper a low-voltage low-power threshold voltage monitor for CMOS process sensing is presented. This circuit works in weak inversion and it can be used as an elementary circuit block for on-chip compensation of the intra-die or inter-die threshold voltage variations in low-power analog and mixed-signal SoC, since it is robust to temperature and power supply voltage variations (similar to the bandgap voltage reference). The proposed threshold voltage monitor has been successfully verified in a standard 0.35-μm n-well CMOS TSMC process. Experimental results have confirmed that the circuit generates an average reference voltage of 758 mV (very close to the typical threshold voltage when extrapolated to absolute zero) for a 950 mV power supply voltage, with a variation of 39 ppm/°C for the −20 to 80°C temperature range.     

A real-time, low-power implementation for high-resolution eigenvalue-based spectrum sensing

In this paper, a novel multiple antenna, high-resolution eigenvalue-based spectrum sensing algorithm based on the FFT of the received signal is introduced. The proposed platform overcomes the SNR wall problem in the conventional energy detection (ED) algorithm, enabling the detection of the weak signals at ?10 dB SNR. Moreover, the utilization of FFT for the input signal channelization provides a simple, low-power design for a high-resolution spectrum sensing regime. A real-time, low-area, and low-power VLSI architecture is also developed for the algorithm, which is implemented in a 0.18 μm CMOS technology. The implemented design is the first eigenvalue-based detection (EBD) architecture proposed to-date capable of detecting weak signals at ?10 dB. Despite having more algorithmic complexity in comparison to the ED, the proposed EBD architecture shows no significant increase in the core area and the power consumption, due to the FFT utilization for the input signal channelization. The proposed design occupies a total area of 3.4 mm² and dissipates 78 mW for a 40 MHz sensing bandwidth consisting of 32 sub-channels.     

A dictionary-based en/decoding scheme for low-power data buses

As bus lengths on multihundred-million transistor systems-on-a-chip (SoC) grow, and as interwire capacitances of sub-0.10 /spl mu/m technologies advance, the resulting high-switching capacitances of buses (and interconnects in general) have a nonnegligible impact on the power consumption of a whole SoC. This trend has been recognized and recently addressed by various research groups. We address this problem by introducing our bus encoding technique, adaptive dictionary-encoding scheme "ADES" that minimizes the power consumption of data buses through a dictionary-based encoding technique. Based on exploration of data properties on buses, our technique saves on average more than 25% of bus energy compared to the nonencoded cases using a large set of real-world applications for both address and data buses. Furthermore, we compare our technique to the best-known data bus encoding techniques to date and we find that it exceeds all of them in terms of energy savings for the same set of applications.     

Dual-period self-refresh scheme for low-power DRAM's with on-chipPROM mode register

A dual-period self-refresh (DPS-refresh) scheme for low-power DRAM's is proposed. Word lines are classified into two groups according to retention test data which are stored in a PROM mode register implemented in the chip periphery. The word lines are controlled individually by combining the memory-mat-select signal and the classification signal from the PROM register. The effective refresh period can be extended by four to six times compared to the conventional self-refresh period. Data-retention current of a 64-Mb DRAM test chip featuring the proposed DPS-refresh scheme is reduced to half the conventional self-refresh current without considerable area penalty     

Promising storage capacitor structures with thin Ta2O5 film for low-power high-density DRAMs

To ensure the required capacitance for low-power DRAMs (dynamic RAMs) beyond 4 Mb, three kinds of capacitor structures are proposed: (a) poly-Si/SiO₂/Ta₂O₅/SiO₂ /poly-Si or poly-Si/Si₃N₄/Ta₂O ₅/SiO₂/poly-Si (SIS), (b) W/Ta₂O₅ /SiO₂/poly-Si (MIS), and (c) W/Ta₂O₅ W (MIM). The investigation of time-dependent dielectric breakdown and leakage current characteristics indicates that capacitor dielectrics that have equivalent SiO₂ thicknesses of 5, 4, and 3 nm can be applied to 3.3-V operated 16-Mb DRAMs having stacked capacitor cells (STCs) by using SIS, MIS, and MIM structures, respectively, and that 3 and 1.5 nm can be applied to 1.5-V operated 64-Mb DRAMs having STCs by using MIS and MIM structures, respectively. This can be accomplished while maintaining a low enough leakage current for favorable refresh characteristics. In addition, all these capacitors show good heat endurance at 950°C for 30 min. Therefore, these capacitors allow the fabrication of low-power high-density DRAMs beyond 4 Mb using conventional fabrication processes at temperatures up to 950°C. Use of the SIS structure confirms the compatability of the fabrication process of a storage capacitor using Ta₂O₅ film and the conventional DRAM fabrication processes by successful application to the fabrication process of an experimental memory array with 1.5-μm×3.6-μm stacked-capacitor DRAM cells     

High-speed low-power voltage-programmed driving scheme for AMOLED displays

A new voltage-programmed driving scheme named the mixed parallel addressing scheme is presented for AMOLED displays, in which one compensation interval can be divided into the first compensation frame and the consequent N-1 post-compensation frames without periods of initialization and threshold voltage detection. The proposed driving scheme has the advantages of both high speed and low driving power due to the mixture of the pipeline technology and the threshold voltage one-time detection technology. Corresponding to the proposed driving scheme, we also propose a new voltage-programmed compensation pixel circuit, which consists of five TFTs and two capacitors(5T2C). In-Zn-O thin-film transistors(IZO TFTs) are used to build the proposed 5T2C pixel circuit. It is shown that the non-uniformity of the proposed pixel circuit is considerably reduced compared with that of the conventional 2T1C pixel circuit. The number of frames(N) preserved in the proposed driving scheme are measured and can be up to 35 with the variation of the OLED current remaining in an acceptable range. Moreover, the proposed voltage-programmed driving scheme can be more valuable for an AMOLED display with high resolution, and may also be applied to other compensation pixel circuits.     

Variable supply-voltage scheme for low-power high-speed CMOSdigital design

This paper describes a variable supply-voltage (VS) scheme. From an external supply, the VS scheme automatically generates minimum internal supply voltages by feedback control of a buck converter, a speed detector, and a timing controller so that they meet the demand on its operation frequency. A 32-b RISC core processor is developed in a 0.4-μm CMOS technology which optimally controls the internal supple voltages with the VS scheme and the threshold voltages through substrate bias control. Performance in MIPS/W is improved by a factor of more than two compared with its conventional CMOS design     

Novel scheme for low-power classified vector quantisation imagecoding

A novel scheme for low-power image coding and decoding based on classified vector quantisation is presented. The main idea is the replacement of the memory accesses to large background memories (most power-consuming operations), by arithmetic and/or application-specific computations. Specifically, the proposed image coding scheme uses small sub-codebooks to reduce the memory requirements and memory-related power consumption in comparison with classical vector quantisation schemes. By applying simple transformations on the codewords during coding, the proposed scheme extends the small sub-codebooks, compensating for the quality degradation introduced by their small size. Thus, the main coding task becomes computation-based rather than memory-based, leading to a significant reduction in power consumption. The proposed scheme achieves image qualities comparable with, or better than, those of traditional vector quantisation schemes, as the parameters of the transformations depend on the image block under coding, and the small sub-codebooks are dynamically adapted each time to this specific image block. The main disadvantage of the proposed scheme is the decrease in the compression ratio in comparison with classical vector quantisation. A joint (quality-compression ratio) optimisation procedure is used to keep this side-effect as small as possible     

The stabilized reference-line (SRL) technique for scaled DRAMs

The stabilized reference-line (SRL) technique, which reduces bit-line interference noise, is described. This technique can eliminate the capacitance coupling noise generated when the cell data are transferred to the bit line. As a result, the noise generated by the sensing timing difference, which is caused by the coupling noise, does not arise. Furthermore, the SRL technique can be realized by modifying the conventional folded bit-line architecture. Therefore, it is easy to apply the SRL technique to high-density DRAMs     

A low-power and high-performance CMOS fingerprint sensing andencoding architecture

A CMOS fingerprint sensor architecture with embedded cellular logic for image processing is presented. The system senses a fingerprint image with a capacitive technique and performs several image-processing algorithms, including thinning the ridges of the fingerprint structure and encoding it to its characteristic features. Image processing is achieved by application of hexagonal local operators implemented in pixel-parallel mixed neuron-MOS/CMOS logic circuits. The massive parallelism of the architecture leads to a very low power dissipation. Results of simulations and measurements on a demonstrator chip in 0.65-μm double-poly standard CMOS technology are shown. The approach is well suited for person-identification applications, especially in small and low-cost portable systems, such as smart cards