一种用于电视调谐器的宽带CMOS低噪声放大器设计

介绍了一种宽带CMOS低噪声放大器设计方法,采用噪声抵消技术消除输入MOS管的噪声贡献.芯片采用TSMC 0.25μm 1P5M RF CMOS工艺实现.测试结果表明:在50～860MHz工作频率内,电压增益约为13.4dB;噪声系数在2.4～3.5dB之间;增益1dB压缩点为-6.7dBm;输入参考三阶交调点为3.3dBm.在2.5V直流电压下测得的功耗约为30mW.     

CMOS宽带线性可变增益低噪声放大器设计

文章设计了一种48MHz~860MHz宽带线性可变增益低噪声放大器,该放大器采用信号相加式结构电路、控制信号转换电路和电压并联负反馈技术实现。详细分析了线性增益控制、输入宽带匹配和噪声优化方法。采用TSMC0.18μm RF CMOS工艺对电路进行设计,仿真结果表明,对数增益线性变化范围为-5dB~18dB,最小噪声系数为2.9dB,S11和S22小于-10dB,输入1dB压缩点大于-14.5dBm,在1.8V电源电压下,功耗为45mW。     

低噪声宽带放大器的设计实例

低噪声微波放大器是决定雷达接收机灵敏度的关键因素，而宽频带特性又是电子侦察和电磁兼容测量的关键特性。针对上述要求，研制了工作在3-6GHz的C波段低噪声宽带放大器。该场放经某基地使用，证明性能良好，满足军方要求。     

5.6GHz CMOS低噪声放大器设计

分析了一种射频COMS共源-共栅低噪声放大器的设计电路,采用TSMC 90nm低功耗工艺实现。仿真结果表明:在5.6GHz工作频率,电压增益约为18.5dB;噪声系数为1.78dB;增益1dB压缩点为-21.72dBm;输入参考三阶交调点为-11.75dBm。在1.2V直流电压下测得的功耗约为25mW。     

宽带CMOS低噪声放大器的设计

文章主要介绍应用于集群接收机系统的350MHz～470MHz低噪声放大器,采用0.6μm CMOS工艺。探讨了优化低噪声放大器的噪声系数、增益与线性度的设计方法,同时对宽带输入输出匹配进行了分析。这种宽带低噪声放大器的工作带宽350MHz～470MHz,噪声系数小于3dB,增益为24dB,增益平坦度为±1dB,输入1dB压缩点大于-15dBm。     

电视调谐器中电阻负反馈结构的宽带低噪声放大器设计

设计了一种应用于DVB-S标准的数字电视调谐器的宽带放大器.采用电阻负反馈输入匹配结构,把交流反馈和直流偏置结合在一起,在噪声、增益和线性度方面达到了很好的性能,满足射频电视调谐器的应用需要.此低噪声放大器有约2.5 GHz的3 dB带宽,大于20 dB的电压增益,输入匹配优于-14 dB,噪声系数低于3.3 dB,IIP3在2.5 dBm之上.此LNA的输入匹配、线性度、噪声性能作了较为详细的讨论.     

一种用于电视协调器的CMOS无电感互补噪声抵消低噪声放大器设计

本文介绍了一个用于电视协调器的CMOS无电感互补噪声抵消低噪声放大器。放大器包括一个共栅极和一个共源级,实现单端转差分的功能。采用的互补结构能够节省功耗和改善噪声系数。线性度也通过采用多个晶体管并联技术来增强。芯片采用SMIC 0.18μm CMOS 工艺。测试结果表明,在50MHz到860MHz频段内,电压增益达到13.5到16dB,噪声系数小于4.5dB,最小达到2.9dB,在860MHz频率处,输入1dB压缩点为-7.5dBm。核心电路在1.8V电源电压下,消耗6mA电流,芯片面积是0.2×0.2mm2     

一种用于地面和有线接收机的宽带低噪声放大器

提出并设计了一种用于数字电视接收调谐芯片的宽带低噪声放大器.该设计采用0.35μm SiGe BiCMOS工艺,器件的主要性能为:增益等于18.8dB,增益平坦度小于1.4dB,噪声系数小于5dB,1dB压缩点为-2dBm,输入三阶交调为8dBm.在5V供电的情况下,直流功耗为120mW.     

一种专用宽带低噪声前置放大器

描述了一种专用双极单片宽带噪声前置放大器。该放大器的开环增益60dB－3dB带宽2．5MHz,等效输入噪声电压1．6V√Hz。     

基于ADS仿真的宽带低噪声放大器设计

设计了一个S频段宽带低噪声放大器.该放大器采用两级E-PHEMT晶体管(ATF541M4)级联结构,单电源供电模式.应用微波仿真软件ADS对匹配电路进行了优化设计,最后通过S参数及谐波平衡仿真得到放大器的各项性能参数,在2.7～3.1 GHz频率范围内噪声系数小于0.6 dB,带内增益大于30 dB,带内平坦度小于±1 dB,输入输出驻波比小于1.6 dB,1 dB增益压缩点输入功率不小于-15 dBm.仿真结果表明,该设计完全满足性能指标要求.     

A Wide-Band Low Noise Amplifier for Terrestrial and Cable Receptions

提出并设计了一种用于数字电视接收调谐芯片的宽带低噪声放大器.该设计采用0.35μm SiGe BiCMOS工艺,器件的主要性能为:增益等于18.8dB,增益平坦度小于1.4dB,噪声系数小于5dB,1dB压缩点为-2dBm,输入三阶交调为8dBm.在5V供电的情况下,直流功耗为120mW.     

2.4 GHz、增益可控的CMOS低噪声放大器

介绍了一种基于 0 35 μmCMOS工艺、2 4GHz增益可控的低噪声放大器。从噪声优化、阻抗匹配及增益的角度详细分析了电路的设计方法 ,讨论了寄生效应对低噪声放大器性能的影响。仿真结果表明在考虑了高频寄生参数的情况下 ,低噪声放大器依然具有良好的性能指标 :在 2 4GHz工作频率下 ,3dB带宽为 6 6 0MHz,噪声系数NF为 1 5 8dB ,增益S2 1为 14dB ,匹配参数S11约为 - 13 2dB。     

Design Guidelines for the Noise Optimization of a 0.18 μm CMOS Low-Noise Amplifier

This paper presents the design considerations for the noise optimization of fully integrated tuned low-noise amplifiers (LNA) based on the four noise parameters and two-port noise theory. Specifically, this paper provides the design guidelines for a 0.18 μm CMOS tuned LNA. These guidelines give a useful indication to the design tradeoffs associated with noise figure, power dissipation and gate overdrive voltage for the LNA designed using this technology. As a case study, a 10 GHz LNA has been designed using 0.18 μm CMOS technology for a wireless LAN application. The amplifier has a 2.4 dB noise figure with a −13 dBm third-order input intercept point, while drawing 5 mW from a 1.8 V power supply. The results show that the proposed theoretical contours of constant noise figure which relate the gate overdrive voltage and power dissipation can accurately predict the noise performance of a 0.18 μm CMOS LNA design Ahmed A. Youssef received the B.Sc. (Hon.) and M.Sc. degrees both in electrical engineering from Ain Shams University, Cairo, Egypt, in 1998 and 2002, respectively. Since 2003, he has been with the University of Calgary, AB, Canada, where he is currently working toward the Ph.D. degree in RF integrated circuits and systems. Mr. Youssef has joined the Wireless Research Center at TRLab, Alberta, Canada as a research associate in 2004. His research interests include the analog high speed integrated circuit for the wireless LAN applications. Mr. Youssef is the recipient of the Mobinil Telecommunication Inc. Pre-master Fellowship in 1999. He also received the Young Scientist award at the Maastricht General Assembly of the International Union of Radio Science in 2002 and an Honorable Mention at 2003 in the Symposium of the Microelectronics Research & Development in Canada, Montreal. Mr. Youssef received the Gordon Lewis Hedberg Doctoral Scholarship in 2005.     

A Highly Linear Wideband CMOS Low-Noise Amplifier Based on Current Amplification for Digital TV Tuner Applications

A differential wideband low-noise amplifier (LNA) based on the current amplification scheme is presented for digital TV tuners. In order to highly improve the linearity and exploit the noise cancellation, a common-gate stage with positive current feedback is integrated in parallel with a common-source stage using the current mirror amplifier. The proposed 0.18-mum CMOS LNA exhibits a power gain of 20.5 dB, an IIP3 of 2.7 dBm, an IIP2 of 43 dBm, and an average noise figure of 3.3 dB with 32.4 mW power consumption at a 1.8-V power supply and 0.12 mm² area.     

低功耗CMOS射频低噪声放大器的设计

介绍了一个针对无线通讯应用的2.1 GHz低噪声放大器(LNA)的设计.该电路采用Chartered 0.25 μm CMOS工艺,电源电压为2.5 V,设计中使用了多个电感,详述了设计过程并给出了优化仿真结果. 模拟结果显示,该电路能提供21.63 dB的正向增益(S21),功耗为12.5 mW,噪声系数为2.1 dB,1 dB压缩点为-19.054 1 dBm.芯片面积为0.8 mm×0.6 mm.测试结果达到了设计指标,一致性良好.     

A CMOS Resistive Feedback Differential Low-Noise Amplifier With Enhanced Loop Gain for Digital TV Tuner Applications

A resistive feedback differential low-noise amplifier (LNA) with enhanced loop gain is implemented as a part of a digital TV (DTV) tuner using a 0.18-$mu{hbox{m}}$ CMOS process. A voltage buffer having higher gain, higher linearity, and lower noise figure (NF) than those of the conventional differential source follower (DSF), which is called the differential hybrid voltage buffer (DHVB) in this paper, is designed by combining the common source amplifier and source follower. By adopting the DHVB with optimized performance as a voltage buffer of the conventional resistive feedback differential LNA, the loop gain of the LNA can be increased. This leads to a highly linear resistive feedback LNA with higher gain and lower NF compared to the conventional resistive feedback LNA. For the wide gain range, the proposed LNA includes the variable gain function based on the resistive attenuator employing the T-switch. The measurement results of the proposed LNA exhibit a maximum gain of 16 dB and a gain range of 50 dB. At maximum gain, the LNA shows an average NF of 2.8 dB, a third-order input-referred intercept point of $-{hbox{1 dBm}}$, a second-order input-referred intercept point of 40 dBm, and S11 of under $-{hbox{9 dB}}$ in a frequency range from 48 to 860 MHz. The power consumption is 30.6 mW at a 1.8-V power supply and the chip area is ${hbox{0.25 mm}}^{2}$.      

用于数字电视调谐芯片的高线性CMOS VGA

设计了一种适于DVB-C标准的中频可变增益放大器。该放大器由三部分构成:电流调节型可变增益单元、基于差分对管传输特性的指数控制电压产生电路以及一高线性输出级。采用Chartered0.25μm RFCMOS工艺库下流片。测试结果表明,4～49dB的连续增益范围,100MHz的3dB带宽,50Ω负载下的OIP3为16.8dBm。