A comprehensive analytical study of an undoped symmetrical double-gate MOSFET after considering quantum confinement parameter

This paper presents analytical models of threshold voltage, carrier concentration and drain current for undoped symmetrical double-gate (SDG) MOS devices. The analytical models are derived after solving the Poisson's equation under Gradual Channel Approximation (GCA). Quantum mechanical effect in ultrathin silicon film is studied by introducing quantum confinement parameter and quantum corrected potential in the Poisson's equation instead of solving complex Schrödinger–Poisson's equation. The confinement parameter, which depends on film thickness, work function and gate bias decreases with film thickness. Quantum corrected potential attains its maximum value near the interface and minimum value at the centre of the silicon film. The mobile carrier density and surface potential are reduced due to quantum confinement effect. The simulation result of the threshold voltage shows excellent agreement with quantum numerical results.     

An explicit analytical charge-based model of undoped independent double gate MOSFET

This paper describes an explicit analytical charge-based model of an undoped independent double gate (DG) MOSFET. This model is based on Poisson equation resolution and field continuity equations. Without any fitting parameter or charge sheet approximation, it provides explicit analytical expressions of both inversion charge and drain current considering long undoped transistor. Consequently, this is a fully analytical and predictive model allowing describing planar DG MOSFET as well as FinFET structures. The validity of this model is demonstrated by comparison with Atlas simulations.     

带有P型埋层的新型双栅SOI MOSFET

本文提出一种超低比导通电阻(Ron,sp)可集成的SOI 双栅triple RESURF (reduced surface field)的n型MOSFET (DG T-RESURF)。这种MOSFET具有两个特点：平面栅和拓展槽栅构成的集成双栅结构(DG),以及位于n型漂移区中的P型埋层。首先, DG形成双导电通道并且缩短正向导电路径,降低了比导通电阻。DG结构在反向耐压时起到了纵向场板作用,提高了器件的击穿电压特性。其次, P型埋层形成triple RESURF结构 (T-RESURF),这不仅增加了漂移区的浓度,而且调节了器件的电场。这在降低了比导通电阻的同时提高了击穿电压。最后,与p-body区连接在一起的P埋层和拓展槽栅结构,可以显著降低击穿电压对P型埋层位置的敏感性。通过仿真,DG T-RESURF的击穿电压为325V,比导通电阻为8.6 mΩ?cm2,与平面栅single RESURF MOSFET(PG S-RESURF)相比,DG T-RESURF的比导通电阻下降了63.4%,击穿电压上升9.8%。     

Analytical I-V relationship incorporating field-dependent mobility for a symmetrical DG MOSFET with an undoped body

A simple expression explicitly relating the surface potential to the surface electric field of a symmetrical double-gate (DG) MOS capacitor is proposed. The expression does not contain the floating-body potential as an implicit variable. It is used to derive, assuming the validity of the gradual-channel approximation, an analytical model expression for the current-voltage relationship of a DG MOS field-effect transistor. The effects of mobility degradation at high vertical electric field and velocity saturation at high lateral electric field are incorporated. The model expression is continuously valid from the subthreshold to the quasi-linear regimes of operation and up to a well-defined drain saturation voltage. Beyond this saturation voltage, the gradual-channel approximation breaks down within a region near the drain end of the channel. The electric-field distribution within this region is estimated by solving a two-dimensional Poisson's equation. Further implications of the model are derived by simplifying the expression in different regimes of operation using various approximations.     

FinFET-a self-aligned double-gate MOSFET scalable to 20 nm

MOSFETs with gate length down to 17 nm are reported. To suppress the short channel effect, a novel self-aligned double-gate MOSFET, FinFET, is proposed. By using boron-doped Si/sub 0.4/Ge/sub 0.6/ as a gate material, the desired threshold voltage was achieved for the ultrathin body device. The quasiplanar nature of this new variant of the vertical double-gate MOSFETs can be fabricated relatively easily using the conventional planar MOSFET process technologies.     

An analytical expression for MOSFET gate leakage current

Integral expressions for the gate leakage current in a MOSFET are derived on the basis of Schottky emission across the gate insulator and on the internal self-heating due to device power dissipation. Computer evaluation of these integrals yields gate leakage current curves that exhibit the same characteristics observed experimentally.     

An analytical model for the threshold voltage of a narrow-width MOSFET

A closed form analytical expression is derived to predict the threshold voltage of a narrow-width MOSFET. The present calculation utilizes the Fourier transform technique to analyze the voltage over the width cross section of the basic MOS device structure. No fitting parameter with experimental data is necessary because the fringe electric field is calculated directly from the relevant physical parameters to deduce the threshold voltage. The dependence of threshold voltage on channel width and substrate bias thus obtained is in reasonable agreement with experimental and numerical results. The effects of field doping and field oxide thickness on the threshold voltage are also taken into consideration. A comparison is made of the present analytical expression for threshold voltage with that, based on an adjustable weighting factor, of earlier analytical models.     

An analytical avalanche breakdown model for double gate MOSFET

An analytical model of avalanche breakdown for double gate (DG) metal-oxide-semiconductor field-effect transistor (MOSFET) is presented. First of all, the effective mobility (μ_eff) model is defined to replace the constant mobility model. The channel length modulation (CLM) effect is modeled by solving the Poisson’s equation. The avalanche multiplication factor (M) is calculated using the length of saturation region (ΔL). It is shown that the avalanche breakdown characteristics calculated from the analytical model agree well with commercially available 2D numerical simulation results. Based on the results, the reliability of the DG MOSFET can be estimated using the proposed analytical model.     

An analytical expression for the threshold voltage of a small geometry MOSFET

A closed form analytical expression for the threshold voltage of a small geometry MOSFET is developed. The threshold voltage expression is derived from a three dimensional geometrical approximation of the bulk charge. The threshold voltage is expressed as a function of gate oxide thickness, channel doping concentraton, junction-depth, backgate bias and channel length and width. The theory is compared with experimental results and the agreement is close.     

An analytical solution to the microstrip line problem

An analytical method for determining the line capacitance of a microstrip line is presented. The solution is exact, but it is expressed by means of the solution of an infinite system of linear equations whose coefficients are the result of certain numerical quadratures. The analysis is carried out for the case of two dielectric substrates. Changes to include additional stratified layers are readily available using the transfer matrix method described by P.M. van Berg et al. (1985). Comparison of the results obtained using the proposed formula with those obtained using exact formulas (available in particular cases) shows that, in cases of practical interest, it is sufficient to consider only the first two equations in the above-mentioned infinite set of linear equations     

An analytical model for floating-gate MOSFET including the effectsof the overlapping capacitance

An analytical model for the current-voltage characteristics of a floating-gate MOSFET are developed. The effects of the overlapping capacitance are included. The model was tested on experimental data obtained from fabricated devices. Good agreement was observed between measurement results and the model     

A physical compact DC drain current model for long-channel undoped ultra-thin body (UTB) SOI and asymmetric double-gate (DG) MOSFETs with independent gate operation

In this paper, a new compact charge based DC model for the drain current of long channel fully depleted ultra-thin body SOI MOSFETs and asymmetric double-gate MOSFETs with independent gate operation (ADGMOSFETs) is presented. The model was validated by both TCAD simulations and electrical measurements with a good agreement. In particular, great care was taken during the derivation of the model in order to respect the physics of the device and to make the correct approximations. The obtained solutions can be viewed as a generalization of classical MOS theory to the case of undoped fully depleted ADGMOS. As a result, the model consists of relatively simple equations and is a promising approach for the compact modeling and parameter extraction of fully depleted SOI transistors.     

Self-aligned vertical double-gate MOSFET (VDGM) with the oblique rotating ion implantation (ORI) method

A process of making a symmetrical self-aligned n-type vertical double-gate MOSFET (n-VDGM) over a silicon pillar is revealed. This process utilizes the technique of oblique rotating ion implantation (ORI). The self-aligned region forms a sharp vertical channel profile and decreases the channel length L_g. A tremendous improvement in the drive-on current is noted. The electron concentration profile obtained demonstrates an increased number of electrons in the channel injected from the source end as the drain voltage increases. The enhanced carrier concentration results in significant reduction in the off-state leakage current and improves the drain-induced barrier-lowering (DIBL) effect. These simulated characteristics when compared to those in a fabricated device without the ORI method show the distinct advantage of the technique reported for suppression of short-channel effects (SCE) in nanoscale vertical MOSFET.     

An analytical drain current model for graded channel cylindrical/surrounding gate MOSFET

In the present paper, a comprehensive drain current model incorporating various effects such as drain-induced barrier lowering (DIBL), channel length modulation and impact ionization has been developed for graded channel cylindrical/surrounding gate MOSFET (GC CGT/SGT) and the expressions for transconductance and drain conductance have been obtained. It is shown that GC design leads to drain current enhancement, reduced output conductance and improved breakdown voltage. The effectiveness of GC design was examined by comparing uniformly doped (UD) devices with GC devices of various L₁/L₂ ratios and doping concentrations and it was found that GC devices offer superior characteristics as compared to the UD devices. The results so obtained have been compared with those obtained from 3D device simulator ATLAS and are found to be in good agreement.     

无畸变传输线方程的解析解

对均匀传输线方程作拉氏变换，得出线上电压电流的复频域解，在无畸变的条件下，根据拉氏变换表和拉氏变换的有关性质，得出了线上电压电流在阶跃激励下的时域解，通过计算实例验证了该算法的有效性。     

An analytical solution to the diffraction problem of diagnosing the position and size of a sphere

A method for determining the position and dimensions of a body from the scattered field is described. The body (a metal solid sphere) is situated in the near-field zone of a transmitting antenna, and the receiving antenna is situated in the near zone of the body. The parameters of the body are calculated from the measured wave amplitudes in the dielectric waveguide of the receiving antenna. For calibration of the antenna, the body is replaced by a metal mirror.     

An analytical drain current model for dual material engineered cylindrical/surrounded gate MOSFET

In this paper, a drain current model incorporating drain-induced barrier lowering (DIBL) has been developed for Dual Material gate Cylindrical/Surrounding gate MOSFET (DMG CGT/SGT MOSFET) and the expressions for transconductance and drain conductance have been obtained. It is shown that DMG design leads to drain current enhancement and reduced output conductance. The effectiveness of DMG design was scrutinized by comparing with single metal gate (SMG) CGT/SGT MOSFET. Moreover, the effect of technology parameters variations workfunction difference has also been presented in terms of gate bias, drain bias, transconductance and drain conductance. Results reveal that the DMG SGT/CGT devices offer superior characteristics as compared to single material gate CGT/SGT devices. A good agreement between modeled and simulated results has also been obtained thus providing the validity of proposed model.     

SOI MOSFET with buried body strap by wafer bonding

Although the buried oxide in the silicon-on-insulator (SOI) MOSFET makes possible higher performance circuits, it is also responsible for various floating body effects, including the kink effect, drain current transients, and history dependence of output characteristics. It is difficult to incorporate an effective contact to the body because of limitations imposed by the SOI structure. One candidate, which maintains device symmetry, is the lateral body contact. However, high lateral body resistance makes the contact effective only in narrow width devices. In this work, a buried lateral body contact in SOI is described which consists of a low-resistance polysilicon strap running under the MOSFET body along the device width. MOSFET's with effective channel length of 0.17 μm have been fabricated incorporating this buried body strap, showing improved breakdown characteristics. Low leakage of the source and drain junctions demonstrates that the buried strap is compatible with deep submicron devices. Device modeling and analysis are used to quantify the effect of strap resistance on device performance. By accounting for the lateral resistance of the body, the model can be used to determine the maximum allowable device width, given the requirement of maintaining an adequate body contact