Electron-beam fabrication of GaAs low-noise MESFET's using a new trilayer resist technique

A LO/HI/LO resist system has been developed to produce sub-half-micrometer T-shaped cross section metal lines using e-beam lithography. The system provides T-shaped resist cavities with undercut profiles. T-shaped metal lines as narrow as 0.15 µm have been produced. GaAs MESFET's with 0.25-µm T-shaped Ti/Pt/Au gates have also been fabricated on MBE wafers using this resist technique. Measured end-to, end 0.25-µm gate resistance was 80 ω/mm, dc transconductance gmas high as 300 mS/mm was observed. At 18 GHz, a noise figure as low as 1.4 dB with an associated gain of 7.9 dB has also been measured. This is the lowest noise figure ever reported for conventional GaAs MESFET's at this frequency. These superior results are mainly attributed to the high-quality MBE material and the advanced T-gate fabrication technique employing e-beam lithography.     

Double-layer resist films for submicrometer electron-beam lithography

This paper describes a double-layer resist-film technique for submicrometer electron-beam lithography. The results of computer simulation and lithography experiments carried out on PMMA/MPR (LO/HI) and MPR/PMMA (HI/LO) double-layer films are reported in full detail. It is shown that an undercut profile suitable for the lift-off processing can be reproducibly obtained by the use of the LO/HI structure over a wide range of electron-beam exposure dose, while the HI/LO structure is of great advantage in the fabrication of lift-off metal gates with a mushroom-like cross section.     

Double-Layer Resist Films for Submicrometer Electron-Beam Lithography

This paper describes a double-layer resist-film technique for submicrometer electron-beam lithography. The results of computer simulation and lithography experiments carried out on PMMA/MPR (LO/HI) and MPR/PMMA (HI/LO) double-layer films are reported in full detail. It is shown that an undercut profile suitable for the lift-off processing can be reproducibly obtained by the use of the LO/HI structure over a wide range of electron-beam exposure dose, while the HI/LO structure is of great advantage in the fabrication of lift-off metal gates with a mushroom-like cross section.     

Optimization of the composition of a new MRS-type negative resist

Sensitizer concentration is optimized for a new negative photoresist, MRL (Micro Resist for Longer wavelengths) with the assistance of computer simulation. The resist, which has photosensitivity in the ordinary UV region, resembles a deep UV resist MRS in terms of light absorption characteristic. It is found that a photosensitizer concentration of 20 wt% (based on the resin) is suitable for a reduction projection exposure system that utilizes UV light at 365 nm. A steep profile resist image of 0.7-µm lines and 0.7-µm spaces in a 1.0-µm thick resist layer is obtained using the MRL of optimized composition and the exposure system.     

Analysis of pattern accuracy in submicrometer electron-beam direct writing

To create submicrometer patterns with high accuracy on thick single-layer negative resist, error factors that degrade pattern accuracy have been investigated. Pattern accuracy was analyzed using a new evaluation method based on the difference between the resist development energy and the exposure energy at points on the edge of each shape. By introducing a new evaluation parameter, we were able to clarify error factors from the exposure conditions, the proximity effect correction method, and the machine exposure fluctuation. The evaluation parameterKisQ/Q_{0}whereQis the exposure dose appropriate for the desired resist thickness and Q0is the interface gel dose. It was found that the resist resolution and the rounding error of the exposure dose were serious error factors, especially in delineation on submicrometer patterns. To achieve 0.5-µm patterns with ±0.1-µm accuracy on 1-µm-thick negative resist, the resist evaluation parameterKmust be less than 2, the rounding error of the exposure dose must be less than 2.5 percent of the dose, and the beam addressing unit (LSB) must be less than 0.025 µm.     

Variable-shaped electron-beam direct writing technology for 1-µm VLSI fabrication

A 1-µm 256K MOS RAM has been fabricated using a variable-shaped electron-beam (EB) direct writing technology. EB drawing data are prepared using a new program, PEBL, which includes a new algorithm for shot division. PEBL plays an important role in obtaining high EB system throughput and high quality patterns. A new proximity correction technique, DCA, has also been proposed. This technique is simple and very effective in fabricating 1-µm VLSI patterns. Negative resist CMS or positive resist FPM are used appropriately, according to process levels. In fabrication of a 1-µm 256K MOS RAM, ±0.2-µm overlay accuracy and ±0.1-µm linewidth accuracy were achieved.     

Dry etching technology for 1-µm VLSI fabrication

A dry etching technology for 1-µm VLSI has been developed. This technology led to successful fabrication of a 1-µm 256-kbit MOS RAM using electon-beam direct writing and molybdenum-polysilicon double-gate structure. Silicon nitride, silicon dioxide, phosphosilicate glass, polysilicon, single-crystal silicon, molybdenum, and aluminum are etched by parallel-plate RF diode reactors. Resist patterns are used as etching masks. The negative resist is CMS and the positive resist is FPM. Plasma polymerization is found to have significant effect on etching selectivity, undercutting, and residue. Directional etching profiles are realized and 1-µm patterns with less than 0.05-µm undercutting are obtained. High etching selectivities are achieved. Methods for preventing and removing contamination as well as damage are established. With these, dry etching proves to bring no adverse effects on device characteristics. Pattern-width fluctuations caused by negative-resist pattern foot are decreased to below 0.1 µm by a new foot trimming technique. Resist step coverage is also clarified.     

GaAs LSI-directed MESFET's with self-aligned implantation for n+-layer technology (SAINT)

Self-aligned implantation for n⁺-layer technology (SAINT) has been developed for improvement in normally-off GaAs MESFET's to be used in LSI's. This technology has made it possible to arbitrarily control the spacing between the n⁺-implanted layer and gate contact by a dielectric lift-off process utilizing a multilayer resist with an undercut wall shape. SAINT FET's with a 1-µm gate length have above 200 mS/ mm transconductance in the normally-off region. The K value along the square-lawI - Vfitting has been improved by a factor of 3.4, compared to conventional FET's without the n⁺-layer. Thermal emission for carriers from the source n⁺-layer in the subthreshold region has been experimentally formulated. Threshold-voltage shift due to gate shortening for [011] gate FET's is definitely smaller than that for [011] gate FET's. The threshold-voltage standard deviations for [011] gate FET's with 2- and 1-µm gate lengths, obtained from a 6-mm × 9-mm area, are 9 and 34 mV, respectively. An E/D direct-coupled FET logics (DCFL) 15-stage ring oscillator with a 1-µm gate length shows a high switching speed of 45 ps/gate at a low supply voltage of 0.91 V.     

Projection photolithography-liftoff techniques for production of 0.2-µm metal patterns

A technique which allows the use of projection photolithography with the photoresist liftoff process, for fabrication of Submicrometer metal patterns, is described. Through-the-substrate (back-projection) exposure of the photoresist produces the undercut profiles necessary for liftoff processing. Metal lines and superconducting microbridges of 0.2-µm width have been fabricated with this technique. Experimental details and process limits are discussed.     

Resolution, overlay, and field size for lithography systems

Resolution, overlay, and field size limits for UV, X-ray, electron beam, and ion beam lithography are described. The following conclusions emerge in the discussion. 1) At 1-µm linewidth, contrast for optical projection can be higher than that for electron beam. 2) Optical cameras using mirror optics and deep UV radiation can potentially produce linewidths approaching 0.5 µm. 3) For the purpose of comparing the resolution of electron beam and optical exposure, it is useful to define the minimum linewidth as twice the linewidth at which the contrast of the exposure system has fallen to 30 percent. 4) X-ray lithography offers the highest contrast and resist aspect ratio for linewidths above about 0.1 µm, but for dimensions below 0.1 µm, highest aspect ratio is obtained with electron beam. 5) With electron beam exposure on a bulk sample, contrast for a 50-nm linewidth is the same as that for 1-µm linewidth, provided the resist is thin. Higher accelerating voltages make it easier to correct for proximity effects and to maintain resolution with thick resist. 6) Ultimately the range of secondary electrons limits resolution in electron beam lithography, just as the range of photoelectrons limits resolution in X-ray lithography. In both cases, minimum linewidth and spacing in dense patterns is about 20 nm. Resolution with ion beams will probably be about the same because the interaction range of the ions will be similar to the electrons.     

Deep UV 1:1 projection lithography utilizing negative resist MRS

A negative deep UV resist Micro Resist for Shorter wavelengths (MRS) is successfully applied to 1:1 projection printing. The MRS is characterized by strong absorption of deep UV light and absence of swelling in the developer. It resolves steep profile images of 1-µm linewidth in 1-µm-thick films. The resist has extremely high sensitivity to deep UV light. Scanning exposure time necessary for a 4-in wafer is about 25 s. The MRS exhibits dry etching resistance superior to that of an AZ-type positive resist. Furthermore, MRS is not adversely affected by reflected light from stepped aluminum surfaces. Application of MRS should open the way to realization of a practical deep UV 1:1 projection lithography featuring high resolution and throughput.     

Linewidth control in projection lithography using a multilayer resist process

Linewidth control using a tri-layer resist system on wafers with topography is investigated. An absorbing dye is incorporated in the bottom layer to improve the usable resolution. Resist patterns of 1-µm lines and spaces over aluminized topography are demonstrated using a projection aligner. The advantages of a multilayer system are investigated using an exposure and development simulation program for optical lithography. The relative contributions of planarization and reflection suppression are discussed.     

Alignment signals from resist-coated marks for direct wafer writing

Monte Carlo (MC) calculations based on a continuous-slowing-down approximation and experimental techniques are used to characterize the backscattered alignment signals from resist-covered Si tapered step marks. Effects of the coated thickness and the resist profile slope are separated by using MC simulation. A 1-µm resist coating on a 2-µm Si step reduces the maximum differenceDeltaSin the back-scattered signal for 20-keV electrons by a factor of 2 and about ⅓ of this reduction is due to the fact that the resist does not conformally follow the step. The rate of reduction inDeltaSwith resist coating was found to be faster for signals collected from low takeoff angles, however, the low takeoff angle signals are still preferred. For a 1-µm resist coating and 20-keV electrons, backscattered electrons with less than half the incident energy contain more information about the substrate but the use of energy analysis techniques would only improve the contrast slightly with a tradeoff in reduced signal-to-noise ratio. For best results alignment marks should a) be covered by a resist thickness less than 0.4 RB(RB= Bethe range) so that electrons will "see" the underlying material, and b) have a depth larger than ⅓ the resist thickness, so that the resist profiles will adequately reflect the underlying mark topography.     

Influence of n+-layer-gate gap on short-channel effects of GaAs self-aligned MESFET's (SAINT)

Short-channel effects of GaAs n⁺-gate self-aligned MESFET's are investigated for different n⁺-layer-gate gaps. The gate lengths range from 0.1 to 1.5 µm. The fabrication features are self-aligned implantation for n⁺-layer technology (SAINT) and an electron-beam direct writing. The n+-layer-gate gap is controlled by the undercut process in the bottom resist of a multilayer resist acting as n⁺ion implantation mask. It is shown that the short-channel effects such as an increase in subthreshold current and a negative shift of threshold voltage can be substantially alleviated by enlarging the n⁺-layer-gate gap from 0.15 to 0.3 µm.     

0.4-µm gate-length devices fabricated by contrast-enhanced lithography

This letter describes the fabrication of submicrometer polysilicon-gate MOS devices by an advanced optical process called contrast enhancement. Functional devices having gate lengths as small as 0.4 µm were fabricated with this process. Contrast-enhanced lithography (CEL) allows usable photoresist patterns to be fabricated at smaller dimensions than is possible with conventional resist. The simultaneous replication of mask dimensions for isolated lines at 0.35 µm and above was achieved in this work using a single exposure on an Optimetrix 10:1 DSW system. Contrast enhancement has been applied to the fabrication of n-channel MOS devices having gate lengths from 0.4 to 1.5 µm in steps of 0.1 µm. Long-channel devices were also fabricated. The transconductance of the 0.4-µm devices is 40 mS/mm at Vds= 5 V. Threshold voltages (Vds= 0) are nearly independent of gate length, ranging from 1.21 to 1.31 V over the 7.5- to 0.4-µm range in gate length. The effective mobility for long-channel devices is 430 cm²/V.s.     

Determination of wavelength and excitation voltage for X-ray lithography

The exposure time of an X-ray lithography system is minimized by the appropriate choice of X-ray wavelength and target excitation voltage, within the constraints of a specified resolution and contrast in the exposed resist pattern. The factors that must be considered in making this choice are the X-ray source brightness of various target materials, the continuum emission spectrum of the target, the wavelength-dependent transmission of the X-ray mask and the vacuum window, and the wavelength-dependent absorption in the resist. The relative exposure time, as a function of wavelength, is predicted for a system using a 25-µm-thick beryllium window and PMMA resist with three choices of mask substrate: 12.5- µm-thick Mylar, 4.0-µm-thick silicon, and 8.5-µm-thick beryllium. A new mask substrate, 0.2-µm-thick aluminum oxide, is presented and shown to be suitable for exposure in vacuum with a 2.5-µm-thick aluminum filter at 13.3-Å wavelength (copper target). X-ray emission spectra from an aluminum target were measured at electron energies of 4.5, 7.9, 10.4, 12.5, 15.5, 19.5, and 28.5 keV. These spectra showed that the continuum radiation contributes little to the degradation of contrast with a gold-on-silicon X-ray mask. Thus a 20-kV electron beam may be used for maximum X-ray production efficiency.     

Mo- and Ti-silicided low-resistance shallow junctions formed using the ion implantation through metal technique

Mo-and Ti-silicided junctions were formed using the ITM technique, which consists of ion implantation through metal (ITM) to induce metal-Si interface mixing and subsequent thermal annealing. Double ion implantation, using nondopant ions (Si or Ar) implantation for the metal-Si interface mixing and dopant ion (As or B) implantation for doping, has resulted in ultrashallow ( ≤ 0.1-µm) p⁺-n or n⁺-p junctions with ∼30-Ω sheet resistance for Mo-silicided junctions and ∼5.5-Ω sheet resistance for Ti-silicided junctions. The leakage current levels for the Mo-silicided n⁺-p junctions (0.1-µm junction depth) and the Mo-silicided p⁺-n junction (0.16-µm junction depth) are comparable to that for unsilicided n⁺-p junction with greater junction depth ( ∼0.25 µm).     

0.2 Micron length T-shaped gate fabrication using angle evaporation

A new technique has been developed to generate sub-half-micron T-shaped gates in GaAs MESFET's. The technique uses a single-level resist and an angle evaporation process. By using this technique, T-shaped gates with lengths as short as 0.2 µm near the Schottky interface have been fabricated. Measured gate resistance from this structure was 6.1 Ω/mm gate width which is the lowest value ever reported for gates of equal length. GaAs single- and dual-gate MESFET's with 0.3 µm long T-shaped gates have also been fabricated. At 18 GHz, maximum available gain of 9.5 dB in the single-gate FET and maximum stable gain of 19.5 dB in the dual-gate device have been measured.     

Resolution and linewidth tolerances in electron beam and optical projection lithography

In order to understand the practical limits of electron beam direct-write and optical projection lithography techniques in device fabrication with micrometer and submicrometer geometries, we have exercised two computer simulation programs to estimate resolution limits and linewidth control. Latent image contrast and developed resist thickness contrast were calculated as a function of line-array spatial frequency. The linewidth tolerances were calculated by varying exposure, development time, focusing, line/space Pattern, resist thickness, etc. These simulation results indicate that the lithographic performance of the two techniques using state-of-the-art exposure tools are comparable at 1-µm dimensions. Some relevant experimental data also are presented.     

Electron-beam fabrication of submicrometer gates for a GaAs MESFET logic

A direct electron-beam lithography is applied to the fabrication of a submicrometer gate for an enhancement-mode GaAs MESFET logic. Exposure doses to produce submicrometer stripes in the positive PMMA resist on a GaAs wafer are investigated for different beam scans of a 0.1-µm-diameter spot. The resist adhesion against a GaAs etchant under the gate recessing is tested to make a fine control of an epitaxial layer thickness with good results. A propagation delay of 64 ps with an associated power consumption of 0.4 mW is obtained with a 0.5 × 20-µm-gate GaAs MESFET, which demonstrates the fastest speed among the enhancement-mode logics.