高速OTDM系统的时钟恢复技术

介绍了高速光时分复用(OTDM)系统时钟恢复技术的三条实现思路，给出了具体的实验系统，指出了它们的适用场合。     

4×10 GHz的OTDM系统时钟提取及解复用实验研究

对4×10 GHz光时分复用(OTDM)系统中,基于LiNbO3调制器的注入光电混合振荡器的时钟提取方法进行了实验验证,提取的时钟抖动小于0.5 ps.从实验上分析了入射光功率对时钟信号的影响.同时利用提取的时钟实现了基于电吸收调制(EAM)晶体的各个信道的解复用,解复用信号基本无邻道串扰.     

OTDM中时钟提取技术的发展及前景

光时钟提取是光时分复用的关键技术之一，得到了广泛的关注。目前，OTDM系统中用于时钟提取的技术方案有多种，本文对各种光时钟提取技术进行了综述和分析，并对其发展前景进行了展望。     

Monolithic Mode-Locked Laser and Optical Amplifier for Regenerative Pulsed Optical Clock Recovery

We experimentally demonstrate optical clock recovery using a novel mode-locked laser (MLL) monolithically integrated with an output semiconductor optical amplifier. The laser's mirror placement is determined using lithography, allowing for mode locking and clock recovery at the exact frequency of the design (35.00 GHz), which is easily scalable to 40 GHz or higher. The design is compatible with other photonic integrated circuit components, enabling integrated signal processing with MLLs. The device generates pulses at 35.0-GHz repetition rate with 6-ps pulsewidth, over 12-dB extinction ratio (ER), and 8.3-dBm output power. Among other regenerative capabilities, the device performs optical clock recovery with 50% jitter reduction from a degraded input signal with low ER     

一种用于622 Mb/s光纤通讯的时钟恢复电路

提出了一种用于622Mb／s光纤通讯系统的时钟恢复电路。该电路采用改善的正交相关器结构，以改善传统的锁相环捕获范围窄、因环境噪声干扰而失锁的问题。同时，很好地解决了数据恢复电路中时钟和数据的校准问题。压控振荡器(VCO)采用全差分和延时插入技术，以抑制电源和衬底噪声，提高振荡频率范围。该电路采用2μm双板型工艺，在3．3V电压下工作，用Cadence软件进行模拟，捕获时间小于16μs，输出时钟抖动小于0．005UI。     

基于内插的OFDM系统采样时钟恢复研究

数字内插滤波器全数字化恢复采样时钟已广泛应用于OFDM系统数字接收机中.文中给出了基于数字内插采样时钟恢复的完整推导过程,采用Farrow结构的数字滤波器,同时用拉格朗日内插方法对采样信号进行数字内插,完成收发两端之间采样时钟的完全匹配.仿真结果表明,该方案能够很好地跟踪采样时钟偏差,快速实现采样时钟的恢复.     

A Simulation Study of Clock Recovery in QPSK and 9QPRS Systems

Computer simulation is employed to assess jitter performance of a clock recovery circuit as a function of the characteristics of the rectifier being used. Several types of rectifiers are compared, some operating at baseband, others at intermediate frequency (IF). It is shown that the best choice between them depends both on the modulation format and on the excess bandwidth factor of the pulse spectrum. In QPSK systems, fourth-law rectifiers outperform the others for rolloff factors up to 0.2 while, for higher values, baseband absolutevalue rectifiers are preferable. In the case of 9QPRS, baseband absolutevalue rectifiers provide jitter reductions of one order of magnitude at high signal-to-noise ratios.     

一种自适应时钟恢复方法

针对高速传输系统的接收端芯片去开销后的低功耗时钟产生问题,此部分电路最合适的工作时钟应为与有效数据速率相等的时钟频率,文中提出一种产生此时钟的方法。通过虚拟一个数据缓冲,以其缓冲的数据量的变化量作为频率偏差的标志,并以此为基础通过压控晶体振荡器对时钟进行调整。通过仿真证实,这种方法能实现时钟的调整,并能使前后时钟之间的真实数据缓冲区处于最安全的数据存量状态。     

A Novel Clock Recovery Scheme for ATSC Receivers

This paper presents a method of using the field sync signal to perform clock recovery for ATSC receivers. This approach ensures a fast, reliable, and accurate receiver clock recovery even under severely distorted channel conditions.     

一种快速以太网卡芯片时钟恢复电路

提出了一种快速以太网卡芯片时钟恢复电路的设计 ,包括体系结构、用于 10 0BASE TX的改进MuellerMuller算法、用于 10 0BASE FX的鉴相器以及产生多相时钟的电荷泵锁相环。该时钟产生电路经过TSMC 0 .35 μm1P5MCMOS工艺验证 ,工作电压为 3.3V。实验结果表明该时钟恢复电路能够满足以太网卡芯片的要求。     

全光再生中的时钟恢复技术

随着超高速大容量的光网络的发展,全光再生技术成为目前的研究热点.其中全光的时钟恢复是全光再生技术的重要组成部分, 是全光再生中定时、整形的基础.文章在阐述了目前各种全光时钟恢复技术研究所取得的进展的基础上,分析了各类技术的优缺点,并对进一步研究作了展望.     

一种适用于NRZ数据的时钟数据恢复电路

提出了一种基于传统电荷泵锁相环结构的时钟数据恢复电路.采用一种适用于NRZ数据的新型鉴频鉴相器电路,以克服传统鉴频鉴相器在恢复NRZ信号时出现错误脉冲的问题,从而准确地恢复出NRZ数据.同时,对其他电路也采用优化的结构,以提高时钟数据恢复电路的性能.设计的电路可在1.1 V超低电压下工作,适合RF ID等需要低电压、低功耗的系统使用.     

用于能量回收逻辑的正弦功率时钟电路

分析了功率时钟对电容负载充电与回收的物理过程，研完了正弦功率时钟产生电路的基本结构，考虑了功率时钟的频率与相位的稳定性。在此基础上，提出了稳定功率时钟频率与相位的功率时钟产生电路，即接入外部参考时钟，使振荡电路与参考时钟同步。用0．8μm DPDM CMOS工艺实现了一个简化的两相正弦功率时钟产生电路，通过物理测试，验证了电路的工作原理。     

一种高速跳频信号跳时钟恢复方法

针对非合作环境下高速跳频信号的特点,提出了一种跳时钟恢复方法,为对抗中的跟踪干扰提供了前提条件.该方法在处理中使用了高速采样并行处理、频域检测估计信号载频、多相正交下变频抽取滤波、双滑窗检测能量跳变与锁相跟踪等方法,算法结构简单,便于在FPGA上实现.结合仿真详细描述了信号检测和跳时钟恢复的工作原理,对算法中的关键技术进行了分析,经过实际验证表明本方法稳定可靠.     

All-Optical NRZ-DPSK Clock Recovery Using Chromatic-Dispersion-Induced Clock Tone

All-optical clock recovery (CR) from 10-Gb/s nonreturn-to-zero differential phase-shift-keying (NRZ-DPSK) signal is demonstrated experimentally by introducing the chromatic-dispersion-induced clock tone into a free-running semiconductor optical amplifier (SOA)-based fiber ring laser for achieving mode-locking. Since no special component is required for NRZ-DPSK demodulation, our proposed method is very promising because of its simple configuration and better stability. The good performance of our proposed configuration is fulfilled with a 20-km standard single-mode fiber to regenerate clock tone of the NRZ-DPSK signal. The recovered clock signal with the extinction ratio of 17 dB and the root-mean-square timing jitter of 718 fs is achieved under 2³¹-1 pseudorandom binary sequence NRZ-DPSK signals measurement     

A Wide-Tracking Range Clock and Data Recovery Circuit

A hybrid analog-digital quarter-rate clock and data recovery circuit (CDR) that achieves a wide-tracking range and excellent frequency and phase tracking resolution is presented in this paper. A split-tuned analog phase-locked loop (PLL) provides eight equally spaced phases needed for quarter-rate data recovery and the digital CDR loop adjusts the phase of the PLL output clocks in a precise manner to facilitate plesiochronous clocking. The CDR employs a second-order digital loop filter and combines delta-sigma modulation with the analog PLL to achieve sub-picosecond phase resolution and better than 2 ppm frequency resolution. A test chip fabricated in a 0.18 mum CMOS process achieves BER <10^-12 and consumes 14 mW power while operating at 2 Gb/s. The tracking range is greater than plusmn5000 ppm and plusmn2500 ppm at 10 kHz and 20 kHz modulation frequencies, respectively, making this CDR suitable for systems employing spread-spectrum clocking.     

A High-Speed Low-Voltage Phase Detector for Clock Recovery From NRZ Data

A novel topology of phase detector (PD) for applications in clock recovery systems from nonreturn-to-zero data is presented in this paper. The PD operates directly on the data stream, without requiring preprocessing, and behaves like a sampling-type PD, providing a sinusoidal phase characteristic. The triple-tail cell principle is exploited to obtain a circuit topology suitable to low-voltage high-speed applications, with a very simple structure and thus limited jitter generation. A model is proposed to understand circuit behavior and optimize its design. The PD has been used in a clock-and-data recovery circuit for 10-Gb/s optical communications, and measurements in agreement with SONET specifications are reported.     

利用锁模光纤激光器做时钟提取器的OTDM通信系统

简短评述了大容量和超大容量光通信系统的ＷＤＭ和ＯＴＤＭ技术，提出了一个在ＯＴＤＭ通信系统中用锁模光纤激光器做时钟提取器的新方法，给出了一个利用设置波分预标时钟脉冲方案构成的新的全光型ＯＴＤＭ通信实验系统结构。     

脉幅有序变化OTDM信号的支路及群路全光时钟提取

将含暗帧脉冲的 4× 2 .5GHz的光时分复用 (OTDM)信号注入一含半导体光放大器 (SOA)的锁模光纤激光器 ,利用SOA的交叉增益调制效应 ,提取出 2 .5GHz的支路时钟信号和 5GHz,10GHz的群路时钟信号 ;群路时钟的提取机制是有理数谐波锁模机制。光时分复用信号采用暗帧脉冲不但可以用来识别支路信号 ,而且显著提高了支路时钟信号的质量     

4×10Gbit/sOTDM系统中10GHz帧时钟提取技术

本文介绍了利用非等幅原理进行帧时钟分量提取的原理;阐述了40Gbit/s光时分复用(OTDM)系统中利用电时钟提取技术实现10GHz帧时钟的理论模型和实验框图;分析了OTDM光信号参数和时钟提取单元参数对系统的影响,并给出了理论分析结果;分析了应用于实际中的时钟提取单元的实现过程和实验结果;并对理论结果和实验结果进行了分析和比较.