基于FPGA的ISA总线/MMИ总线数据转换电路设计

某型导弹测试设备控制总线为通用的ISA总线,而通信接口总线为非标准的MMИ总线。在此以FPGA为核心设计了一种ISA总线/MMИ总线转换电路,该电路可以完成2种制式的数据和控制指令转换。给出了转换电路原理框图、FPGA配置电路和地址比较电路原理图。实验结果表明该电路具有转换数据准确,工作可靠等优点。实际应用表明,该电路完全能达到测试设备的要求。     

Portierung von LAN-Kommunikationseigenschaften auf einen Feldbus

There is no universally applicable programming interface to address the existent shortcomings for field buses. A number of field buses have come into widespread use and the implementers of field bus-based systems tend to have problems to employ the field bus efficiently. Within the project described a LAN-oriented field bus-independent protocol has been defined and implemented, to speed up the implementation process for the implementer.     

Utilizing the effect of relative delay on energy dissipation in low-power on-chip buses

This paper presents an analysis of how the power dissipation of on-chip buses is affected by introducing a relative delay between the switching lines. Relative delay is shown to reduce the dissipated power of oppositely switching lines while causing a power penalty for similarly switching lines. A new low-power bus scheme that uses this effect is proposed and analyzed. As the introduced delay increases, the achieved power reduction increases while decreasing the bus throughput. Thus, a tradeoff between power reduction and throughput is required when selecting the imposed relative delay. The proposed low-power scheme, dynamic delayed line bus (DDL) scheme, led to a power reduction of up to 25%, 33%, and 42% when applied to data, address, and differential buses, respectively. Simple DDL hardware is designed and implemented in a 0.18-/spl mu/m TSMC CMOS technology and applied to a 4500-/spl mu/m long Metal4 bus. Circuit simulation results for different bus widths are presented.     

Bus-switch coding for reducing power dissipation in off-chip buses

We present a novel coding scheme for reducing bus power dissipation. The presented approach is well suited to driving off-chip buses, where the line capacitance is a dominant factor. A distinctive feature of the technique is the dynamic reordering of bus line positions, in order to minimize the toggling activity on physical bus wires. The effectiveness of the approach is demonstrated through cycle-accurate simulation of industrial benchmarks in conjunction with post-layout evaluation of speed, power and area overhead.     

Design and analysis of spatial encoding circuits for peak power reduction in on-chip buses

We propose various low-latency spatial encoder circuits based on bus-invert coding for reducing peak energy and current in on-chip buses with minimum penalty on total latency. The encoders are implemented in dual-rail domino logic with interfaces for static inputs and static buses. A spatial and temporally encoded dynamic bus technique is also proposed for higher performance targets. Comparisons to standard on-chip buses of various lengths with optimal repeater configurations at the 130-nm node show the energy-delay and peak current-delay design space in which the different encoder circuits are beneficial. A 9-mm spatially encoded static bus exhibits peak energy gains beyond that achievable through repeater optimization for a single-cycle operation at 1 GHz, with delay and energy overhead of the encoding included. For throughput-constrained buses, the spatially encoded static bus can provide up to 31% reduction in peak energy, while the spatially and temporally encoded dynamic bus yields peak current reductions of more than 50% for all bus lengths. The encoder circuits show good scaling properties since the performance penalty from encoding decreases with scaled interconnects.     

Modeling of multiconductor buses and analysis of crosstalk,propagation delay and pulse distortion in high speed GaAs logic circuits

Crosstalk, propagation delay, pulse distortion in multiconductor buses for high-speed GaAs logic circuits are analyzed. A simple but accurate quasi-TEM model of the bus is developed, and a critical analysis is carried out both on the accuracy of different approximate lumped and distributed models and on the impact of such approximations on the time-domain response. Results on the behavior of multiconductor buses in the presence of realistic input waveforms, are presented and design criteria are obtained     

A TDM-based multibus packet switch

A new packet switch architecture using two sets of time-division multiplexed buses is proposed. The horizontal buses collect packets from the input links, while the vertical buses distribute the packets to the output links. The two sets of buses are connected by a set of switching elements which coordinate the connections between the horizontal buses and the vertical buses so that each vertical bus is connected to only one horizontal bus at a time. The switch has the advantages of: (1) adding input and output links without increasing the bus and I/O adaptor speed; (2) being internally unbuffered; (3) having a very simple control circuit; and (4) having 100% throughput under uniform traffic. A combined analytical-simulation method is used to obtain the packet delay and packet loss probability. Numerical results show that for satisfactory performance, the buses need to run about 30% faster than the input line rate. With this speedup, even at a utilization factor of 0.9, each input adaptor requires only 31 buffers for a packet loss rate of 10^-6. The output queue behaves essentially as an M/D/1 queue     

A modular multirate video distribution system-design anddimensioning

A modular architecture is proposed for distributing broadcast and switched video. The architecture consists of a set of concentration buses (or input buses), a TDM-based bus matrix and a set of distribution buses (or output buses). The transmission time in each output bus is divided into fixed size frames. Dedicated time slots in a frame are reserved for broadcast video. The remaining time slots are allocated to switched video on a first-come-first-served basis. Videos are switched via time slot assignments which determine the connections within the bus matrix. Two slot assignment algorithms are designed, one for point-to-point transmissions and the other for point-to-multipoint transmissions. The advantages of this architecture include: (1) accommodation of multirate video, (2) support of video broadcasting and multicasting, and (3) modular growth at distributed locations     

Buses for Anonymous Message Delivery

Abstract. This work develops a novel approach to hide the senders and the receivers of messages. The intuition is taken from an everyday activity that hides the ``communication pattern'—the public transportation system. To describe our protocols, buses are used as a metaphor: Buses, i.e., messages, are traveling on the network, each piece of information is allocated a seat within the bus. Routes are chosen and buses are scheduled to traverse these routes. Deterministic and randomized protocols are presented, the protocols differ in the number of buses in the system, the worst case traveling time, and the required buffer size in a ``station.' In particular, a protocol that is based on cluster partition of the network is presented; in this protocol there is one bus traversing each cluster. The clusters' size in the partition gives time and communication tradeoffs. One advantage of our protocols over previous works is that they are not based on statistical properties for the communication pattern. Another advantage is that they only require the processors in the communication network to be busy periodically.     

Estimating data bus size for custom processors in embedded systems

We propose a method to estimate the data bus width to the requirements of an application that is to run on a custom processor. The proposed estimation method is a simulation-based tool that uses Extreme Value Theory to estimate the width of an off-chip or on-chip data bus based on the characteristics of the application. It finds the minimum number of bus lines needed for the bus connecting the custom processor to other units so that the probability of a multicycle data transfer on the bus is extremely unlikely. The potential target platforms include embedded systems where a custom processor (i.e. an ASIC or a FPGA) in a system-on-a-chip or a system-on-a-board is connected to memory, I/O and other processors through a shared bus or through point-to-point links. Our experimental and analytical results show that our estimation method can reduce the data bus width and cost by up to 66% with an average of 38% for nine benchmarks. The narrower data bus allows us to increase the spacing between the bus lines using the silicon area freed from the eliminated bus lines. This reduces interwire capacitance, which in turn leads to a significant reduction of bus energy consumption. Bus energy can potentially be reduced up to 89% for on-chip data buses with an average of 74% for seven benchmarks. Also, reduction in the interwire capacitance improves the bus propagation delay and on-chip bus propagation delay can be reduced up to 68% with an average of 51% for seven benchmarks using a narrower custom data bus.     

Vidibus: a low-cost, modular bus system for real-time videoprocessing

The ability to connect only those modules required to perform a given task has both technical and commercial advantages over a system with a fixed architecture which cannot be easily expanded or updated. Although such bus standards have proliferated in the microprocessor field, a general purpose low-cost standard for digital video processing has yet to gain acceptance. The authors describe the likely requirements of such a system, and discuss three currently available commercial systems. A new bus specification known as Vidibus, developed to fulfil these requirements, is presented. Results from applications already implemented using this real-time bus system are also given     

ANALYSIS OF THE TRANSMISSION PROPERTIES OF TAPERED MUTLICONDUCTOR INTERCONNECTING BUSES IN HIGH-SPEED INTEGRATED CIRCUITS

Analysis approach and formulas for the transmission properties of uniform multicon-ductor interconnecting buses in high-speed integrated circuits are presented in this article. And further, by using a network approach, a tapered bus system can be analyzed as a set of cascaded uniform buses with slightly different strip widths. Obtained results are in good agreement with the experimental data.     

Adaptive Internet Integration of Field Bus Systems

Field buses are used to network sensors, actuators, and control devices inside automation systems. The Internet integration of field bus systems enables information from these devices to be exchanged across enterprises and businesses. An essential prerequisite to this aim is the interoperability of field bus systems with external systems and applications. Therefore, many efforts are made to establish a common information exchange standard which all field bus systems are supposed to support. However, the longer these efforts are ongoing the less it seems that they will ever yield the expected breakthrough. The present paper introduces an substantially different approach to interoperability. Field bus systems may keep their individual application interfaces and data exchange formats. All the same, external infrastructures do not have to be redesigned to match the specific needs of certain field bus systems. Rather, field bus systems become capable of adapting the information exchange flexibly according to the needs of the outside environment     

Sequence-switch coding for low-power data transmission

Reducing the power dissipated by buses becomes one of the most important elements in low-power VLSI design. A new coding scheme called sequence-switch coding (SSC) is proposed in this paper. It is a general-purpose coding scheme that employs the sequence of data in reducing the number of transitions on buses. A simple switching algorithm is presented to show the feasibility of SSC. According to simulations, this algorithm reduces around 10% of bus transitions in the transmission of benchmark files. SSC can be used for burst data transfer in any application. In particular, it is suitable for internet and multimedia applications that have stream-type data transfer pattern.     

Simultaneous On-Chip Bus Synthesis and Voltage Scaling Under Random On-Chip Data Traffic

This paper presents a statistical approach to synthesize an energy conscious the optimal bus width and the number of buses. The slack is exploited to maximize bus sharing and to reduce energy consumption by simultaneously scaling the voltage during the synthesis of on-chip communication bus. An assumption for bus synthesis is that a system has been partitioned and mapped onto the appropriate modules of a system-on-chip (SoC). Because of the diversity of applications to be run on a single SoC, there exists a variability of data size to be transferred among the on-chip communicating modules. This variability of data size is modeled as a random variable with a known distribution function. The resulting synthesis problem is relaxed to a convex quadratic optimization problem and solved efficiently using a convex optimization tool. The effectiveness of our approach is demonstrated by applying optimization to an automatically generated benchmark and a real-life application. By scaling voltage of a bus, a tradeoff between communication bus cost (bus width and the number of buses) and energy reduction is explored. The experimental results show the significant reduction in communication energy with scaling voltage. However, it offers a limitation to minimize the communication bus cost, if the voltage is scaled beyond its minimum limit. Furthermore, we also estimate the distribution of voltage under a random data size using an analytical method and the Monte Carlo simulation. The results show that the analytically estimated statistical parameters of voltage are close to the simulated results.     

高速集成电路中多导体渐变互连线传输特性的分析

本文首先给出高速集成电路中多导体均匀互连线传输特性的分析方法和计算公式。再将渐变互连线近似为线宽略有变化的多节均匀线级联,通过网络理论,分析出渐变线的传输特性。计算结果与测量值吻合很好。     

A bus-oriented multiprocessor fast Fourier transform

A bus-oriented multiprocessor architecture specialized for computation of the discrete Fourier transform (DFT) of a length N =2^M sequential data stream is developed. The architecture distributes computation and memory requirements evenly among the processors and allows flexibility in the number of processors and in the choice of a fast Fourier transform (FFT) algorithm. With three buses, the bus bandwidth equals the input data rate. A single time-multiplexed bus with a bandwidth of three times the input data rate can alternatively be used. The architecture requires processors that have identical hardware, which makes it more attractive than the cascade (pipeline) FFT for multiprocessor implementation     

Topology/Floorplan/Pipeline Co-Design of Cascaded Crossbar Bus

On-chip bus design has a significant impact on the die area, power consumption, performance and design cycle of complex system-on-chips (SoCs). Especially, for high frequency systems having on-chip buses pipelined extensively to cope with long wire delay, a naive bus design may yield a significant area/power cost mostly due to bus pipeline cost. The topology, floorplan, and pipeline are the most important design factors that affect the cost and frequency of the on-chip bus. Since they are strongly correlated with each other, it is imperative to codesign all of the three. In this paper, we present an automated codesign method for cascaded crossbar bus design. We present CADBUS (CAscadeD crossbar BUS design tool), an automated tool for AXI-based cascaded crossbar bus architecture design. The primary objective of this study is to design a cascaded crossbar bus, including the topology/floorplan/bus pipelines, having minimum area/power cost while satisfying the given constraints of communication bandwidth/latency or frequency. Experimental results of the three industrial strength SoCs show that, compared to the existing approach, the proposed method gives as much as 11.6%–34.2% (9.9%–33.5%) savings in bus area (power consumption).      

RATO-net: a random-access protocol for unidirectionalultra-high-speed optical fiber network

The local network medium is a pair of unidirectional fiber optic buses to which stations are connected via passive taps. For this configuration, a random-access protocol called RATO (random-access time-out) is presented. RATO provides random access, fairness, and bounded delay access to all stations, and is particularly suited for ultra-high-speed transmission when the performance of the popular Ethernet becomes unattractive. Simplicity and ease of hardware implementation of RATO under ultra-high-speed environment is emphasized because the only control requirements are the sensing of activity in the bus and a fixed time delay between consecutive transmissions from the same station. Results of simulation and performance comparisons of RATO with other schemes are given. In ultra-high-speed wide-area networks, RATO outperforms all these other schemes     

Adaptive low-power address encoding techniques using self-organizing lists

Off-chip bus transitions are a major source of power dissipation for embedded systems. In this paper, new adaptive encoding schemes are proposed that significantly reduce transition activity on data and multiplexed address buses. These adaptive techniques are based on self-organizing lists to achieve reduction in transition activity by exploiting the spatial and temporal locality of the addresses. Also the proposed techniques do not require any extra bit lines and have minimal delay overhead. The techniques are evaluated for efficiency using a wide variety of application programs including SPEC 95 benchmark set. Unlike previous approaches that focus on instruction address buses, experiments demonstrate significant reduction in transition activity of up to 54% in data address buses and up to 59% in multiplexed address buses. The average reductions are twice those obtained using current schemes on a data address bus and more than twice those obtained on a multiplexed address bus.