General-purpose high-speed integrated lock-in amplifier with 30 dB dynamic reserve at 20 MHz

We present the design of a general-purpose high-speed integrated lock-in amplifier (LIA). The LIA measures the amplitude and phase of the input signal with frequencies from 15 to 20 MHz at SNR as low as ?30 dB. The magnitude measurement circuitry relies on the band-pass filter and current integrator to extract the signal amplitude. The phase measurement circuitry relies on the phase-locked loop to extract the phase difference between the input signal and the reference signal. The designed LIA is fabricated in TSMC 0.18 μm technology. The LIA consumes 37 mW of power. The output signal dynamic range is 300 mV for 600 mV input signal variation, and therefore the output-to-input sensitivity is approximately 0.5 V/V.     

A low power CMOS voltage reference generator with temperature and process compensation

A low power CMOS voltage reference with process compensation is presented in TSMC 0.18-μm standard CMOS technology. Detailed analysis of the process compensation technique is discussed. The circuit is simulated with Spectre. Simulation results show that, without any trimming procedure, the output voltage achieves a maximum deviation of 0.35 % across different process corners. The temperature coefficient of the proposed circuit is 12.7 ppm/°C in a temperature range from ?40 to 85 °C and the line sensitivity is 0.036 mV/V with a supply voltage range from 1.2 to 2.5 V under typical condition. The maximum supply current is 390.4 nA at maximum supply voltage and ?40 °C. The power supply rejection ratio is ?68.3 dB at 100 Hz and 2.5 V without any filtering capacitor.     

一种新型高精度宽电压范围的CMOS温度传感器

介绍了一种用于环境温度监测的新型高精度宽电压范围的CMOS温度传感器,采用0.13μm标准CMOS工艺的厚氧器件实现,芯片面积为37μm×41μm。该温度传感器在-20～60°C的温度范围内,采用两点校正方法之后,温度误差为-0.2°C/0.5°C。该温度传感器可以在1.8～3.6V的电源电压范围内安全可靠地工作,并且具有较高的电源抑制比。测试结果表明,其输出电压斜率为3.9mV/°C,1.8V下功耗为1.3μW。     

Nano Watt CMOS temperature sensor

In this paper, an ultra-low power embedded full CMOS temperature sensor based on sub-threshold MOS operation is designed in a 0.18 μm CMOS technology. It focuses on temperature measurement using the difference between the gate-source voltages of transistors operated in sub-threshold region that is proportional to absolute temperature. By using the proposed scheme the wide range supply voltage of 0.6–2.5 V with inaccuracy of +0.55 °C/V and total power consumption of merely 7 nW at 120 °C is achieved. The performance of the sensor is highly linear and the predicted temperature error is ±2 °C in the range of 10–120 °C. The sensor occupies a small area of 67 × 31 μm². Ultra-low power consumption of the sensor illustrates proper operation for low power applications such as battery powered portable devices, passive RFID tags and wireless sensor network applications.     

A 10 b 120 MS/s 108 mW 0.18 μm CMOS ADC with a PVT-insensitive current reference

This paper proposes a 10 b 120 MS/s CMOS ADC with a PVT-insensitive current reference. The designed current reference shows a mean temperature drift of 35.2 ppm/°C in the temperature range from −25 to 100°C and a supply rejection of 1.1%/V between 1.6 and 2.0 V. The prototype ADC fabricated in a 0.18 μm 1P6M CMOS technology demonstrates a measured DNL and INL of 0.18LSB and 0.53LSB with a maximum SNDR and SFDR of 53 and 68 dB at 120 MS/s. The ADC with an active chip area of 1.8 mm² consumes 108 mW at 120 MS/s and 1.8 V while the proposed on-chip current reference consumes 0.35 mW with a die area of 0.02 mm².     

0.75 V supply nanowatt resistorless sub-bandgap curvature-compensated CMOS voltage reference

This work presents a resistorless self-biased and small area sub-bandgap voltage reference that works in the nano-ampere consumption range with 0.75 V of power supply. The circuit applies a curvature compensation technique that allows an extended temperature range without compromising the temperature stability. The behavior of the circuit is analytically described, and a design methodology is proposed which allows the separate adjustment of the bipolar junction transistor bias current and its curvature compensation. Simulation results are presented for a 180 nm CMOS process, where a reference voltage of 469 mV is designed, with a temperature coefficient of 5 ppm/°C for the ?40 to 125 °C extended temperature range. The power consumption of the whole circuit is 16.3 nW under a 0.75 V power supply at 27 °C. The estimated silicon area is 0.0053 mm².     

A 0.003-mm2, 0.35-V, 82-pJ/conversion ultra-low power CMOS all digital temperature sensor for on-die thermal management

In this paper, a 0.35 V, 82 pJ/conversion ring oscillator based ultra-low power CMOS all digital temperature sensor is presented for on-die thermal management. We utilize subthreshold circuit operation to reduce power and adopt an all-digital architecture, consisting of only standard digital gates. Additionally, a linearization technique is proposed to correct the nonlinear characteristics of subthreshold MOSFETs. A bulk-driven 1-bit gated digitally controlled oscillator is designed for the temperature sensing node. Also, a 1-bit time-to-digital converter is employed in order to double the fine effective resolution of the sensor. The proposed digital temperature sensor has been designed in a 90-nm regular V _T CMOS process. After a two-point calibration, the sensor has a maximum error of ?0.68 to +0.61 °C over the operating temperature range from 0 to 100 °C, while the effective resolution reaches 0.069 °C/LSB. Under a supply voltage of 0.35 V, the power dissipation is only 820 nW with the conversion rate of 10K samples/s at room temperature. Also, the sensor occupies a small area of 0.003 mm².     

A low-power and low-complexity continuous-time Gm-C based Delta-Sigma modulator for WCDMA/UMTS

This article describes the implementation of a continuous-time Delta-Sigma modulator for WCDMA/UMTS in wireless communication. The Delta-Sigma modulator employs a Gm-C based integrator to form a fourth-order noise-shaping loop. The modulator samples at 160 MHz and has an over-sampling ratio of 40 in 2 MHz bandwidth. To reduce power consumption and design complexity, single-bit quantisation is employed. The modulator is implemented in 0.25 µm 1-ploy 5-metal CMOS technology and has an area of 0.13 mm². The modulator can achieve 70.7 dB of signal-to-noise-plus-distortion-ratio and 74 dB of dynamic range. Finally, the modulator consumes 3.5 mW of power with a reduced power supply of 1.8 V.     

Low-voltage temperature sensor for micro-power harvesters in silicon-on-sapphire CMOS

A low-voltage temperature sensor designed for MEMS power harvesting systems is fabricated. The core of the sensor is a bandgap voltage reference circuit operating with a supply voltage in the range 1-1.5 V. The prototype was fabricated on a conventional 0.5 /spl mu/m silicon-on-sapphire (SOS) process. The sensor design consumes 15 /spl mu/A of current at 1 V. The internal reference voltage is 550 mV. The temperature sensor has a digital square wave output the frequency of which is proportional to temperature. A linear model of the dependency of output frequency with temperature has a conversion factor of 1.6 kHz//spl deg/C. The output is also independent of supply voltage in the range 1-1.5 V. Measured results and targeted applications for the proposed circuit are reported.     

A 3 V 110 μW 3.1 ppm/°C curvature-compensated CMOS bandgap reference

This paper presents design of a high-precision curvature-compensated bandgap reference (BGR) circuit implemented in a 0.35 μm CMOS technology. The circuit delivers an output voltage of 1.09 V and achieves the lowest reported temperature coefficient of ~3.1 ppm/°C over a wide temperature range of [?20°C/+100°C] after trimming, a power supply rejection ratio of ?80 dB at 1 kHz and an output noise level of 1.43 μV $ \sqrt {\text{Hz}} $ at 1 kHz. The BGR circuit consumes a very low current of 37 μA at 3 V and works for a power supply down to 1.5 V. The BGR circuit has a die size of 980 μm × 830 μm.     

A linear and wide dynamic range transimpedance amplifier with adaptive gain control technique

A linear and wide dynamic range transimpedance amplifier (TIA) for the pulsed time-of-flight imaging LADAR application has been designed and simulated in a 0.18 μm 3.3 V CMOS technology. Specific design techniques, including adaptive gain control technique to widen linear dynamic range, pseudo-differential structure of the front end to decrease the common-mode noise and noise minimization to improve SNR, have been proposed to achieve challenging designs goals with linear dynamic range of 5000:1, high transimpedance gain of 89 dB Ω, bandwidth up to 150 MHz, equivalent input-referred noise current less than 8 \({\text{pA}}/\sqrt {\text{Hz}}\), in 2 pF photodiode parasitic capacitance. The proposed TIA consumes 165 mW with 3.3 V power supply.     

光接收机用0.5mV高灵敏度带有接收信号强度指示的200MbpsCMOS限幅放大器

采用CSMC 0.6μm 2P2M CMOS工艺设计并实现了0.5mV高灵敏度,72dB超宽动态范围的200Mbps CMOS限幅放大器.该电路详细分析和设计了一种新型的有源直流漂移消除环路获得这一性能.利用信号通路中的限幅放大器,实现了基于分段线性近似的接收信号强度指示电路.信号检测的动态范围高达60dB,对数精度小于2dB.整个电路在5V单电源下工作,功耗为60mW.芯片有效面积为1.05mm2.     

A 0.5-V low power analog front-end for heart-rate detector

This paper presents a low power analog front-end for heart-rate detector at a supply voltage of 0.5 V in 0.18 μm CMOS technology. A fully differential preamplifier is designed with a low power consumption of 300 nW. A 150 nW fourth order Switched-opamp switched capacitor bandpass filter is designed with passband 8–32 Hz. To digitize the analog signal, a low power second-order ΣΔ ADC is designed. The dynamic range and SNR of the converter are 46 dB and 54 dB respectively and it consumes a power of 125 nW. The overall front-end system including preamplifier, SO-SC bandpass filter, ΣΔ modulator and the biasing circuits are integrated and the total system consumes a power of 0.975 μW from 0.5 V supply.     

A high speed single-pole two-stage fully differential amplifier with intrinsic CMFB

A two-stage, fully differential amplifier is presented in this work. The proposed amplifier enjoys from an intrinsic common-mode feedback scheme, which eliminates the extra common-mode circuitries that are essential in typical fully differential circuits. Besides, the proposed architecture introduces a left-half-plane zero which can be adjusted to cancel out the dominant pole and thus to extend the structure’s bandwidth. The simulation results with TSMC 180 nm standard CMOS technology shows the 92.2 dB DC gain and 49 MHz gain bandwidth product with 89° of phase margin. The amplifier consumes 0.45 mW from 1.8 V power supply.     

A high-order curvature compensation technique for bandgap voltage reference using subthreshold MOSFETs

A bandgap voltage reference with high-order curvature compensation is presented in this study. It exploits subtraction and derivative equalisation of currents generated from two complementary NMOS and PMOS bandgap references (BGRs) using subthreshold MOSFETs. By equating the derivative with respect to temperature of the two currents, generated by the complementary bandgaps, and subtracting these currents, an accurate high-order curvature compensation is achieved. To overcome problems due to the limited input common-mode range of opamps used in BGRs, a transimpedance amplifier with new accurate current compensation that tracks the temperature variation is proposed. This bandgap is implemented using the 0.18 μm CMOS process with a supply voltage as low as 0.7 V. At 0.8 V power supply and an output reference voltage of 386 mV, the proposed circuit achieves a temperature coefficient of 19 ppm/°C from 0 to 130°C. The power consumption is 119 μW and the power supply reduction ratio is 24 dB at 1 kHz.     

A 2.1 μA wake-up circuit for Chinese ETC system

This paper proposes a low power wake-up baseband circuit used in Chinese Electronic Toll Collection (ETC) system. To reduce the static power consumption, a low power biasing strategy is proposed. The proposed circuit is fabricated in TSMC 0.18 μm technology with an area of 0.09 mm 2 . Its current consumption is only 2.1 μA under 1.8 V power supply. It achieves a sensitivity of 0.95 mV at room temperature with a variation of only ±28% over -35℃ to 105℃.     

A high-speed latched comparator with low offset voltage and low dissipation

An ultra high-speed latched comparator using a controlled amount of positive feedback cell has been designed in TSMC 0.18 μm CMOS technique. Transmission gate (TG) switches are used to implement the preamplifier circuit. The use of TG switches results in a reduction in the power consumption of the high-speed comparator as well as clock feedthrough and the effect of charge injection. The simulation results demonstrate that it can work at 1.25 GHz suitable for high speed applications, and consumes 273.6 μW with a power supply of 1.8 V at 100 MHz and Monte Carlo simulation shows that the comparator has a low offset voltage approximately 0.499 mV.     

A precision low-power analog front end in 180 nm CMOS for wireless implantable capacitive pressure sensors

This paper presents a new capacitance to voltage analog-front end (AFE) designed in 180 nm CMOS technology for wireless implantable applications. This AFE consists of a Low-dropout regulator (LDO), bandgap reference (BGR), switched-capacitor (SC) sampler, SC op-amp and oscillator. The LDO regulates the wireless power supply coming from an off-chip rectifier and provides a stable and accurate DC voltage. Capacitance is converted to a discrete voltage by a SC sampling circuit and then amplified by a SC op-amp. Both of SC sampling and SC op amp circuits form a correlated double sampling scheme. This AFE is designed to sense a capacitance range from 6 pF to 7 pF (300–1000 mmHg) corresponding to a 0.68 V–1.07 V discrete output voltage with a sampling frequency of 1.63 KHz. This AFE has a sensitivity of 0.39 mV/fF, average power consumption of 201 μW and 3.25% accuracy operating over a 2.1 V–3.3 V rectified wireless supply voltage and −40 °C ~125 °C temperature range.     

2.5Gbps发接器系统均衡器电路的设计

采用片上可编程均衡技术 ,设计了用于数据率为 2 .5 Gbps发接器系统接收端的均衡器电路。电路采用 0 .1 8μm标准 CMOS工艺和 1 .8V单电源。用 UMC模型 Cadence Spectre S软件进行了仿真 ,电路在 0～1 2 5°C范围内 ,三种工艺角和电源电压变化± 1 0 %的条件下能够正确地工作。在 1 .8V电源、75°C和 tt工艺角条件下 ,电路的总功耗为 40 m W。     

A 2.5-Gb/s fully-integrated, low-power clock and recovery circuit in 0.18-μm CMOS

Based on the devised system-level design methodology, a 2.5-Gb/s monolithic bang-bang phase-locked clock and data recovery (CDR) circuit has been designed and fabricated in SMIC's 0.18-μm CMOS technology. The Pottbacker phase frequency detector and a differential 4-stage inductorless ring VCO are adopted, where an additional current source is added to the VCO cell to improve the linearity of the VCO characteristic. The CDR has an active area of 340 × 440μm2, and consumes a power of only about 60 mW from a 1.8 V supply voltage, with an input sensitivity of less than 25 mV, and an output single-ended swing of more than 300 mV. It has a pull-in range of 800 MHz, and a phase noise of-111.54 dBc/Hz at 10 kHz offset. The CDR works reliably at any input data rate between 1.8 Gb/s and 2.6 Gb/s without any need for reference clock, off-chip tuning, or external components.