Characterization of spiral inductors with patterned floating structures

The impact of two different types of floating patterns on spiral inductors was investigated. Both patterned trench isolation with a floating p/n junction and floating metal poles were implemented underneath reference spiral inductors. All three types of inductors have an identical spiral geometry. Combination of patterned trench isolation with a floating p/n junction increases maximum quality factor (Q/sub max/) by 17% compared to the reference inductors. The floating metal poles enable adjustment of the frequency at Q/sub max/ (f/sub max/) without hampering the Q/sub max/. A ladder-type lump-element model was employed to analyze inductor performance after it was demonstrated to precisely capture behavior of all three inductors. Enhancement of the quality factor due to patterned trench isolation with a floating p/n junction was found to result from an increment of effective resistivity in substrates. Reduction of the frequency f/sub max/ due to the floating metal poles was caused by increasing effective coupling capacitance between the spiral inductors and substrate.     

Selective metal parallel shunting inductor and its VCO application

The methodology to calculate the parasitic capacitances in differential symmetric inductors will be presented in this paper. Inspired by the proposed methodology, a method called selective metal parallel shunting (SMPS) can move f/sub Qmax/ onto the desired frequency without additional processing steps. Based on the proposed methodology, a customized program is developed to predict Q/sub max/s and f/sub Qmax/s of on-chip inductors. Differential symmetric inductors and spiral ones with planar, all metal parallel shunting (AMPS), and SMPS configurations have been implemented in a 1P4M 0.35-/spl mu/m CMOS process to verify the proposed method. Moreover, three 2.3-2.4 GHz voltage-controlled oscillators (VCOs) using planar, AMPS, and SMPS inductors, have also been realized. The phase noise of the VCO using SMPS inductors can be improved by 9.3 and 6 dB at 100-kHz offset frequency, respectively, compared to the VCOs using planar and AMPS inductors. The proposed SMPS technique can not only be applicable to VCO but also other RF circuits.     

High-performance inductors integrated on porous silicon

To study the substrate effect on inductor performance, several types of spiral inductors were fabricated on porous silicon (PS), p/sup -/ and p/sup +/ silicon substrate. /spl pi/-network analysis results show that the use of PS effectively reduces the shunt conductance and capacitance. The analysis further shows that the use of PS significantly reduces the eddy current portion of series resistance of inductor, leading to slower increase of the apparent series resistance with increasing frequency. Higher Q-factor and resonant frequency (f/sub r/) result from the reduced shunt conductance, shunt capacitance, and frequency dependence of series resistance. Inductors fabricated on PS regions are subjected to a much less stringent set of constraints than those on bulk Si substrate, allowing for much higher inductance to be achieved without severe sacrifice in Q-factor and f/sub r/. Similarly, much higher Q-factor can be obtained for reasonable inductance and f/sub r/.     

用分布电容模型分析和优化差分电感

建立了预测片上等效寄生电容的片上电感分布电容模型.预测和解释了差分电感的自激振荡频率的差异.实测数据显示,与单端驱动模式下的相同对称电感相比,差分驱动模式电感提高最大品质因数127%,具有更大的工作频率范围.设计和验证了低寄生电容的差分电感.     

Analysis and Optimum Design of Differential Inductors Using Distributed Capacitance Model

A distributed capacitance model for monolithic inductors is developed to predict the equivalently parasitical capacitances of the inductor.The ratio of the self-resonant frequency (fSR) of the differential-driven symmetric inductor to the fSR of the single-ended driven inductor is firstly predicted and explained.Compared with a single-ended configuration,experimental data demonstrate that the differential inductor offers a 127% greater maximum quality factor and a broader range of operating frequencies.Two differential inductors with low parasitical capacitance are developed and validated.     

Microwave Varactor Tuned Transistor Oscillator Design

An analysis is made of the common base microwave transistor oscillator circuit which uses a varactor in series with the colIector to tune over octave bandwidths. Equations are derived giving the required feedback capacitances and resonating elements required for octave tuning. Normally, the collector-emitter capacitance C/sub ce/ is made approximately equal to the transistor collector capacitance C/sub c/. The emitter-base capacitance C/sub eb/ is important only at very high frequencies. It is shown that a high-Q varactor must be used and that only a limited amount of collector-base capacitance C/sub cb/ may be added if the circuit is to be resonated over an octave. The output power for such a circuit is normally about 1/5 the maximum power available from the transistor. Experimental oscillators were made from 0.5 to 1 GHz and 1 to 2 GHz which substantially verified the analysis. Using the TIXS13 transistor, an output power of 200 mW was obtained from 430 to 860 MHz tuning from -2 to -115 volts. In the 1 to 2 GHz range a TIXS13 transistor oscillator was tuned from 1.09-1.96 GHz with about 40 mW power tuning from -2 to -115 volts. By use of a lower case capacitance varactor, the 1 to 2 GHz oscillator could be made to tune over the full octave.     

Improving the Characteristics of integrated EMI filters by embedded conductive Layers

Discrete electromagnetic interference (EMI) filters have been used for power electronics converters to attenuate switching noise and meet EMI standards for many years. Because of the unavoidable structural parasitic parameters of the discrete filter components, such as equivalent parallel capacitance (EPC) of inductors and equivalent series inductance (ESL) of capacitors, the effective frequency range of the discrete filter is normally limited. Aiming at improving high frequency performance and reducing size and profile, the integrated EMI filter structure has been proposed based on advanced integration and packaging technologies , . Some improvements have been made but further progress is limited by EPCs of the filter inductors, which is restricted by dimension, size and physical structure. In this paper, a new structural winding capacitance cancellation method for inductors is proposed. Other than trying to reduce EPCs, a conductive ground layer is embedded in the planar inductor windings and the structural capacitance between the inductor winding and this embedded layer is utilized to cancel the parasitic winding capacitance. In order to obtain the best cancellation effect, the structural winding capacitance model of the planar spiral winding structure is given and the equivalent circuit is derived. The design methodology of the layout and area of the embedded ground layer is presented. Applying this method, an improved integrated EMI filter is designed and constructed. The experimental results show that the embedded conductive layer can effectively cancel the parasitic winding capacitance, hence ideal inductor characteristics can be obtained. With the help of this embedded conductive layer, the improved EMI filter has much smaller volume and profile and much better characteristics over a wide frequency range, compared to the former integrated EMI filter and the discrete EMI filter.     

Effect of extrinsic impedance and parasitic capacitance on figure of merit of RF MOSFET

This paper investigates the impact of source/drain impedance, gate-to-bulk capacitance, and gate resistance on device properties from 0 to 50 GHz for 0.13-/spl mu/m MOSFETs. Better device characteristics (g/sub m/ and C/sub gg/) can be found on MOSFETs with lower metal (or source/drain) resistance. But the best frequency characteristics (f/sub T/ and f/sub max/) occurred on MOSFETs with medium metal (or source/drain) resistance due to the increased interconnection capacitances. For radio frequency MOSFETs with finger-gate structure, better high-frequency behavior occurred on devices with medium finger-gate width W/sub f/ because of the tradeoff between gate (or source/drain) resistance and parasitic capacitance.     

A simple method to extract intrinsic and extrinsic base-collector capacitances of bipolar transistors

A new and direct method is proposed to determine intrinsic (C/sub /spl mu//) and extrinsic (C/sub /spl mu/x/) base-collector junction capacitances of bipolar junction transistors (BJTs). The voltage dependent curves of C/sub /spl mu// and C/sub /spl mu/x/ are obtained by using a new Y-parameter equation that is derived from a simplified "cut-off mode" equivalent circuit including ac current crowding capacitance. This new method is superior to several conventional ones, because it remains valid when there is ac emitter current crowding. The superiority of the new method has been verified by observing much better agreement of modeled gain with measured ones than the conventional method.     

Temperature and substrate-impedance dependence of noise figure of monolithic RF inductors on silicon

In this letter, we analyze the effects of temperature (from -50/spl deg/C to 200/spl deg/C) and substrate impedance on the noise figure (NF) and quality factor (Q-factor) performances of monolithic RF inductors on silicon. The results show a 0.75 dB (from 0.98 to 0.23 dB) reduction in minimum NF (NF/sub min/) at 8 GHz, an 86.1% (from 15.1 to 28.1) increase in maximum Q-factor (Q/sub max/), and a 4.8% (from 16.5 to 17.3 GHz) improvement in self-resonant frequency (f/sub SR/) were obtained if post-process of proton implantation had been done. This means the post-process of proton implantation is effective in improving the NF and Q-factor performances of inductors on silicon mainly due to the reduction of eddy current loss in the silicon substrate. In addition, it was found that NF increases with increasing temperature but show a reverse behavior within a higher frequency range. This phenomenon can be explained by the positive temperature coefficients of the series metal resistance (R/sub s/), the parallel substrate resistances (R/sub sub1/ and R/sub sub2/), and the resistance R/sub s1/ of the substrate transformer loop. The present analyzes are helpful for RF designers to design less temperature-sensitive high-performance fully on-chip low-noise-amplifiers (LNAs) and voltage-controlled-oscillators (VCOs) for single-chip receiver front-end applications.     

A Lower Limit on the Interaction Between Symmetrical Odd-Mode Fringing Capacitances (Letters)

Let us denote the familiar odd-mode fringing capacitance which is plotted in graphs given by Getsinger by C/sub f0/. It is further defined by Fig. 1(b) in the limit as the magnetic wall tends to infinity on the right. We also denote the corresponding fringing capacitance of the symmetrical coaxial structure of Fig. 1(a) by C/sub f0/. When the dimensions of Fig. 1(a) and (b) are such that s' = s, it is convenient to denote the difference between C/sub f0'/ and C/sub f0'/ by /spl utri/C/sub f0/, and define it as the interaction between the symmetrical odd-mode fringing capacitances. Clearly, /spl utri/C/sub f0/ has the property of approaching zero as w/ (b - t) /spl rarr/ 0 [w is defied in Fig. 1(a)]. Moreover, whenever /spl utri/C/sub f0/ is known, C/fub f0/ is also known.     

Physical modeling of spiral inductors on silicon

This paper presents a physical model for planar spiral inductors on silicon, which accounts for eddy current effect in the conductor, crossover capacitance between the spiral and center-tap, capacitance between the spiral and substrate, substrate ohmic loss, and substrate capacitance. The model has been confirmed with measured results of inductors having a wide range of layout and process parameters. This scalable inductor model enables the prediction and optimization of inductor performance     

Analysis of the gate-source/drain capacitance behavior of a narrow-channel FD SOI NMOS device considering the 3-D fringing capacitances using 3-D simulation

This paper reports an analysis of the gate-source/drain capacitance behavior of a narrow-channel fully depleted (FD) silicon-on-insulator (SOI) NMOS device considering the three-dimensional (3-D) fringing capacitances. Based on the 3-D simulation results, when the width of the FD SOI NMOS device is scaled down to 0.05 /spl mu/m, the inner-sidewall-oxide fringing capacitance (C/sub FIS/), due to the fringing electric field at the edge of the mesa-isolated structure of the FD SOI NMOS device biased at V/sub G/=0.3 V and V/sub D/=1 V, is the second largest contributor to the gate-source capacitance (C/sub GS/). Thus, when using nanometer CMOS devices with a channel width smaller than 0.1 /spl mu/m, C/sub FIS/ cannot be overlooked for modeling gate-source/drain capacitance (C/sub GS//C/sub GD/).     

SOI technology for radio-frequency integrated-circuit applications

This paper presents a silicon-on-insulator (SOI) integration technology, including structures and processes of OFF-gate power nMOSFETs, conventional lightly doped drain (LDD) nMOSFETs, and spiral inductors for radio frequency integrated circuit (RFIC) applications. In order to improve the performance of these integrated devices, body contact under the source (to suppress floating-body effects) and salicide (to reduce series resistance) techniques were developed for transistors; additionally, locally thickened oxide (to suppress substrate coupling) and ultra-thick aluminum up to 6 /spl mu/m (to reduce spiral resistance) were also implemented for spiral inductors on high-resistivity SOI substrate. All these approaches are fully compatible with the conventional CMOS processes, demonstrating devices with excellent performance in this paper: 0.25-/spl mu/m gate-length offset-gate power nMOSFET with breakdown voltage (BV/sub DS/) /spl sim/ 22.0 V, cutoff frequency (f/sub T/)/spl sim/15.2 GHz, and maximal oscillation frequency (f/sub max/)/spl sim/8.7 GHz; 0.25-/spl mu/m gate-length LDD nMOSFET with saturation current (I/sub DS/)/spl sim/390 /spl mu/A//spl mu/m, saturation transconductance (g/sub m/)/spl sim/197 /spl mu/S//spl mu/m, cutoff frequency /spl sim/ 25.6 GHz, and maximal oscillation frequency /spl sim/ 31.4 GHz; 2/5/9/10-nH inductors with maximal quality factors (Q/sub max/) 16.3/13.1/8.95/8.59 and self-resonance frequencies (f/sub sr/) 17.2/17.7/6.5/5.8 GHz, respectively. These devices are potentially feasible for RFIC applications.     

Calculation of distributed capacitances of spiral resonators

A method for calculating the distributed capacitances and resonant frequencies of spiral resonators is described. First, the charge distribution on a spiral is found by a simplified model and the moment method, then the distributed capacitance is calculated. The equivalent inductance of the spiral resonator is then evaluated according to a standard formula, and the resonant frequencies are finally computed. The calculated results are compared with experimental data, and a good agreement between them is shown     

General Treatment of Klystron Resonant Cavities

Klystron resonant cavities are treated for general cases and their equivalent circuits are theoretically determined, which allows a fairly accurate estimate of resonant properties. It is shown that a reentrant cavity is expressed as a low-frequency series LCR/sub se/ circuit or a shunt LCR/sub sh/ circuit, taking L as the inductance of a toroidal coil with one turn and with a cross section the same as the cavity, C as the gap capacitance plus the equivalent capacitance of the cavity, and R/sub se/ or R/sub sh/ as the equivalent series or shunt resistance of the cavity at resonance. The introduction of the equivalent cavity capacitance has proved to be very effective. The formulas derived here enable one to calculate the resonant frequency within an error of a few per cent and the shunt resistance and the Q within an error of several tenths of a per cent in most cases, and thus should prove to be very useful to the designer of microwave circuits.     

Micromachined high-Q inductors in a 0.18-μm copper interconnectlow-k dielectric CMOS process

On-chip spiral micromachined inductors fabricated in a 0.18-μm digital CMOS process with 6-level copper interconnect and low-K dielectric are described. A post-CMOS maskless micromachining process compatible with the CMOS materials and design rules has been developed to create inductors suspended above the substrate with the inter-turn dielectric removed. Such inductors have higher quality factors as substrate losses are eliminated by silicon removal and increased self-resonant frequency due to reduction of inter-turn and substrate parasitic capacitances. Quality factors up to 12 were obtained for a 3.2-nH micromachined inductor at 7.5 GHz. Improvements of up to 180% in maximum quality factor, along with 40%-70% increase in self-resonant frequency were seen over conventional inductors. The effects of micromachining on inductor performance was modeled using a physics-based model with predictive capability. The model was verified by measurements at various stages of the post-CMOS processing. Micromachined inductor quality factor is limited by series resistance up to a predicted metal thickness of between 6-10 μm     

A simple wide-band on-chip inductor model for silicon-based RF ICs

In this paper, we developed a simple wide-band inductor model that contains lateral substrate resistance and capacitance to model the decrease in the series resistance at high frequencies related to lateral coupling through the silicon substrate. The model accurately predicts the equivalent series resistance and inductance over a wide-frequency range. Since it has frequency-independent elements, the proposed model can be easily integrated in SPICE-compatible simulators. The proposed model has been verified with measured results of inductors fabricated in a 0.18-/spl mu/m six-metal CMOS process. We also demonstrate the validity of the proposed model for shielded inductors. The proposed model shows excellent agreement with measured data over the whole frequency range.     

Integrated solenoid inductors with patterned, sputter-deposited Cr/Fe/sub 10/Co/sub 90//Cr ferromagnetic cores

Ferromagnetic (FM) films suitable for implementation in between interconnect layers of a standard CMOS fabrication process are demonstrated to yield considerable size reduction of monolithic radio frequency (RF) inductors, leading to lower cost. The deposition of a FM Cr(5 nm)/Fe/sub 10/Co/sub 90/(500 nm)/Cr(15 nm) stack is performed by magnetron sputtering at room temperature under a dc magnetic field of /spl sim/ 10 mT along the magnetic easy-axis. A lift-off technique, using a four-layer shadow mask, is used for pattern transfer to the magnetic stack to circumvent apparent difficulties in the patterning of FM films. A series of solenoid-type inductors with FM cores are demonstrated and compared to control devices with air cores. A more than eight-fold enhancement of the inductance and a seven-fold improvement of the quality factor are achieved.     

A simple parameter extraction method of spiral on-chip inductors

Accurate measurement and parameter extraction for spiral inductors are very important in monolithic microwave integrated circuit (MMIC) design. In this paper, we have proposed an easy and simple model parameter extraction method of wide-band on-chip inductor. The simple extraction methodology is applied to extract parameters from the measured S-parameters of spiral inductors fabricated with 0.18-/spl mu/m CMOS technology. Model prediction shows excellent agreement with the measured data over a wide frequency region. Also, the model can be easily integrated in SPICE-compatible simulators because all the elements are frequency independent. This method will provide practical and useful circuit parameters for MMIC design.