Combining Functional and Structural Approaches for Switched-Current Circuit Testing

This paper aims at defining an efficient test strategy for switched-current circuit testing. Taking into account the specificity of these circuits, we propose an original structural test technique as an alternative to traditionally-used functional verification. This technique is validated both at the cell and block levels. Test results demonstrate that a high fault coverage can be achieved with a low cost test procedure. A mixed strategy combining benefits of functional and structural approaches is derived.     

A novel test compression algorithm for analog circuits to decrease production costs

Minimizing the manufacturing test time for ICs is one of the main keys to reducing the product cost. We introduce a methodology for automated test compression for electrical stress testing of analog and mixed signal circuits. This methodology optimally extracts only portions of a functional test that electrically stress the nets and devices of an analog circuit. We model test compression as a problem of optimizing functional of the transient response. We present a random tree based approach to find the minimum for these computationally hard integrals, which corresponds to the optimally compressed analog test. We demonstrate with an op-amp, VCO, and CMOS inverter that the method consistently reduces the length of each test by an average of 93%. Our technology can compress tests in the presence of process variation and utilize parallel processing to speed up the compression algorithm.     

MC‐MIPOG: A Parallel t‐Way Test Generation Strategy for Multicore Systems

Combinatorial testing has been an active research area in recent years. One challenge in this area is dealing with the combinatorial explosion problem, which typically requires a very expensive computational process to find a good test set that covers all the combinations for a given interaction strength (t). Parallelization can be an effective approach to manage this computational cost, that is, by taking advantage of the recent advancement of multicore architectures. In line with such alluring prospects, this paper presents a new deterministic strategy, called multicore modified input parameter order (MC‐MIPOG) based on an earlier strategy, input parameter order generalized (IPOG). Unlike its predecessor strategy, MC‐MIPOG adopts a novel approach by removing control and data dependency to permit the harnessing of multicore systems. Experiments are undertaken to demonstrate speedup gain and to compare the proposed strategy with other strategies, including IPOG. The overall results demonstrate that MC‐MIPOG outperforms most existing strategies (IPOG, IPOF, IPOF2, IPOG‐D, ITCH, TConfig, Jenny, and TVG) in terms of test size within acceptable execution time. Unlike most strategies, MC‐MIPOG is also capable of supporting high interaction strengths of t > 6.     

基于质量成本的软件测试模型研究及构建

通过分析和比较当前典型的软件测试类型．构建了一个新颖的QC 3-D软件测试模型。该模型融合了软件测试过程、软件质量成本和测试等级三个部分，并定义了软件质量成本的量化公式。通过软件质量成本均衡概念，平衡软件质量成本中的控制成本和故障成本，从而调整软件测试的阶段和等级，以达到软件质量最优同时成本消耗最小的最佳值目标。     

A Low-Cost Test Methodology for Dynamic Specification Testing of High-Speed Data Converters

Testing high-speed A/D converters for dynamic specifications needs test equipment running at high frequency. In this paper, a methodology to test high-speed A/D converters using low-frequency resources is described. It is based on the alternate testing approach. In the proposed methodology, models are built to map the signatures of an initial set of devices, obtained on the proposed low-cost test set-up, to the dynamic specifications of the same devices, obtained using high-precision test equipment. During production testing, the devices are tested on the low-cost test set-up. The dynamic specifications of the devices are estimated by capturing their signatures on the low cost test set-up and processing them with the pre-developed models. As opposed to the conventional method of dynamic specification testing of data converters, the proposed approach does not require the tester resources running at a frequency higher than the device-under-test (DUT). The test methodology was verified in simulations as well as in hardware with specification estimation error of less than 5%.

Efficient object-oriented integration and regression testing

This paper presents a model, a strategy and a methodology for planning integration and regression testing from an object-oriented model. It shows how to produce a model of structural system test dependencies which evolves with the refinement process of the object-oriented design. The model (test dependency graph) serves as a basis for ordering classes and methods to be tested for regression and integration purposes (minimization of test stubs). The mapping from unified modeling language to the defined model is detailed as well as the test methodology. While the complexity of optimal stub minimization is exponential with the size of the model, an algorithm is given that: computes a strategy for integration testing with a quadratic complexity in the worst case; and provides an efficient testing order for minimizing the number of stubs. Various integration strategies are compared with the optimized algorithm (a real-world case study illustrates this comparison). The results of the experiment seem to give nearly optimal stubs with a low cost despite the exponential complexity of getting optimal stubs. As being a part of a design-for-testability approach, the presented methodology also leads to the early repartition of testing resources during system integration for reducing integration duration     

Fuzzy thermal modeling for MCM placement

This paper introduces a fuzzy analytical model for the optimal component placement of the power dissipating chips on a multichip module substrate. Our methodology considers multiobjective component placement based on thermal reliability as well as routing length criteria. The objective of the coupled placement methodology is to enhance the performance and reliability of the multichip module system by obtaining an optimal cost during multichip module placement. Case studies of the coupled placement are presented. In addition, the thermal distribution of the coupled placement results is simulated using the finite element method.     

Mutation Analysis and Constraint-Based Criteria: Results from an Empirical Evaluation in the Context of Software Testing

Several software testing criteria have been proposed during last years with the goal of aiming the test set generation and revealing many faults as possible. They are considered complementary because can reveal different kind of faults and are based on different principles. For example, structural criteria use the internal structure of the program for deriving test cases; Mutation Analysis is a fault-based criterion; and Constraint Based Criteria use constraints to be satisfied during the program execution. Because of this, some questions can be posed, such as: “What criterion should be used or be first applied?”. Many research works compare criteria with the goal of answering these questions. However, some criteria as Mutation Analysis and Constraint Based Criteria are theoretically incomparable and only empirical studies can point out the relation between them. This work presents results from an empirical evaluation of Mutation Analysis and All-Constrained-Potential-Uses criterion considering the factors: cost (number of test cases), efficacy (number of revealed faults) and strength (difficulty of satisfying a criterion, given that another one has been satisfied). The obtained results show an empirical relation, which is used to propose a strategy for application of different testing criteria.     

一种便携式误码测试仪的设计

误码仪是数字通信系统性能测试的重要仪器。设计采用国外专用集成误码测试芯片DS2172、E1接口芯片DS21554和单片机芯片AT89C52联合设计,全部采用高效低功耗芯片,并使用单电源工作,它是一款体积小、重量轻、成本低、便携式的低速率误码测试仪。     

Test of a switched-capacitor ADC by a built-in charge sensor

A test methodology for switched capacitor circuits is described. The test approach uses a built-in sensor to analyze the charge transfer inside the circuit under test (CUT). The test methodology is applied to a 10-bit algorithmic analog to digital converter to obtain the static linearity and to the simulated fault coverage figures taking into account a catastrophic fault model. The goodness of the charge sensor has been experimentally evaluated with an SC integrator for fault detection and built-in sensor influence on the CUT performance.     

Test power reductions through computationally efficient, decoupled scan chain modifications

SOC test time minimization hinges on the attainment of core test parallelism; yet test power constraints hamper this parallelism as excessive power dissipation may damage the SOC being tested. We propose a test power reduction methodology for SOC cores through scan chain modification. By inserting logic gates between scan cells, a given set of test vectors & captured responses is transformed into a new set of inserted stimuli & observed responses that yield fewer scan chain transitions. In identifying the best possible scan chain modification, we pursue a decoupled strategy wherein test data are decomposed into blocks, which are optimized for power in a mutually independent manner. The decoupled handling of test data blocks not only ensures significantly high levels of overall power reduction but it furthermore delivers computational efficiency at the same time. The proposed methodology is applicable to both fully, and partially specified test data; test data analysis in the latter case is performed on the basis of stimuli-directed controllability measures which we introduce. To explore the tradeoff between the test power reduction attained by the proposed methodology & the computational cost, we carry out an analysis that establishes the relationship between block granularity & the number of scan chain modifications. Such an analysis enables the utilization of the proposed methodology in a computationally efficient manner, while delivering solutions that comply with the stringent area & layout constraints in SOC as well.     

Transparent random access memory testing for pattern sensitive faults

This paper presents a new methodology for RAM testing based on the PS(n, k) fault model (the k out of n pattern sensitive fault model). According to this model the contents of any memory cell which belongs to an n-bit memory block, or the ability to change the contents, is influenced by the contents of any k -1 cells from this block. The proposed methodology is a transparent BIST technique, which can be efficiently combined with on-line error detection. This approach preserves the initial contents of the memory after the test and provides for a high fault coverage for traditional fault and error models, as well as for pattern sensitive faults. This paper includes the investigation of testing approaches based on transparent pseudoexhaustive testing and its approximations by deterministic and pseudorandom circular tests. The proposed methodology can be used for periodic and manufacturing testing and require lower hardware and time overheads than the standard approaches.This work was supported by the NSF under Grant MIP9208487 and NATO under Grant 910411.     

LEAD: a methodology for learning efficient approaches to medical diagnosis.

Determining the most efficient use of diagnostic tests is one of the complex issues facing medical practitioners. With the soaring cost of healthcare, particularly in the US, there is a critical need for cutting costs of diagnostic tests, while achieving a higher level of diagnostic accuracy. This paper develops a learning based methodology that, based on patient information, recommends test(s) that optimize a suitable measure of diagnostic performance. A comprehensive performance measure is developed that accounts for the costs of testing, morbidity, and mortality associated with the tests, and time taken to reach diagnosis. The performance measure also accounts for the diagnostic ability of the tests. The methodology combines tools from the fields of data mining (rough set theory, in particular), utility theory, Markov decision processes (MDP), and reinforcement learning (RL). The rough set theory is used in extracting diagnostic information in the form of rules from the medical databases. Utility theory is used in bringing various nonhomogenous performance measures into one cost based measure. An MDP model together with an RL algorithm facilitates obtaining efficient testing strategies. The methodology is implemented on a sample problem of diagnosing solitary pulmonary nodule (SPN). The results obtained are compared with those from four alternative testing strategies. Our methodology holds significant promise to improve the process of medical diagnosis.     

Low-cost, on-line self-testing of processor cores based on embedded software routines☆

On-line testing for complex system-on-chip architectures requires a synergy of concurrent and non-concurrent fault detection mechanisms. While concurrent fault detection is mainly achieved by hardware or software redundancy, like duplication, non-concurrent fault detection, particularly useful for periodic testing, is usually achieved through hardware-based self-test.Software-based self-test has been recently proposed as an effective alternative to hardware-based self-test allowing at-speed testing while eliminating area, performance and power consumption overheads.In this paper, we investigate the applicability of software-based self-test to non-concurrent on-line testing of embedded processor cores and define, for the first time, the corresponding requirements. Low-cost, in-field testing requirements, particularly small test execution time and low power consumption guide the development of self-test routines. We show how self-test programs with a limited number of memory references and based on compact test routines provide an efficient low-cost on-line test strategy for an RISC processor core.     

A Statistical Sampler for a New On-Line Analog Test Method

This work shows a new strategy to the on-line test of analog circuits. The technique presents a very low analog overhead and it is completely digital. In the System-on-Chip (SoC) environment the on-line test can be developed by using processing power already available in the system. As all the signal processing is done in the digital domain, it allows use of a purely digital tester or a digital BIST technique. The main principle of operation is based on the observation of statistical properties of the circuit under test. Since it has low analog power and performance overhead, the proposed technique can be used to analyze the output of several stages of complex analog systems without the use of switches or analog multiplexors for reconfiguration, and no additional AD converter is needed. This paper presents the fundamentals of the proposed test method and some experimental results illustrating the operation of the Statistical Sampler concerning linear analog systems.     

Distributed BIST Architecture to Combat Delay Faults

To successfully combat delay faults there is an urgent need for a proper design for testability (DFT). The foundation of any DFT methodology rests on its scan design. This paper describes three versions of a new design of a shift register latch that lend themselves to distributed self-test and delay test. The advantages of this new SRL is faster application of test vectors, higher DC and AC fault coverages, with low performance impact. Adoption of this new DFT methodology brings us closer to the ideal target of one test-per-clock as opposed to one test-per-scan. Operation, cost, and other attributes are studied in detail. Results of adopting one of these SRLs are reported on ten pilot chips.     

PARALLEL FRAME SYNCHRONOUS SCHEME FOR STM-1 IN SDH NETWORKS

This paper presents a novel parallel processing-based frame synchronous methodology for 155·520 Mbit/s high speed networks according to ITU-T Recommendations G.707, G.708 and G.709. This scheme is expected to relax operating speed requirements of the circuits used in the system. The proposed methodology can be implemented using off-the-shelf low-rate integrated circuits (ICs). The performance of the devised methodology is analysed and found to be similar to that of traditional approaches. Finally, the proposed scheme is efficient and easy to implement at low cost without sacrificing performance.     

Reliability and routability consideration for MCM placement

This paper presents a methodology based on the fuzzy logic approach for the placement of the power dissipating chips on the multichip module substrate. Our methodology considers both thermal distribution and routing length constraints during multichip module placement. In this paper, the main design issue is the coupled placement for reliability and routability. The objective of the coupled placement is to enhance the system performance and reliability by obtaining an optimal cost during multichip module placement. For reliability considerations, the design methodology is addressed on the placement of the power dissipating chips to achieve uniform thermal distribution. The thermal placement analysis is based on the modified fuzzy force-directed placement method. Placement for routability is based on minimizing the total wire length estimated by semi-perimeter method. The placement trade-off between routability and reliability is illustrated by varying a weighting factor. Case studies of the coupled placement are presented. In addition, the thermal distribution of the coupled placement results is simulated with the finite element method.     

Implicit functional testing of switched current filter based on fault signatures

This article aims at defining an efficient test strategy for switched-current (SI) circuit testing. By checking the constructed signatures (impulse response samples) against the derived tolerance ranges, we can infer the correctness of the device under test without explicitly measuring the original performance parameters. We also describe a technique of mapping the tolerance ranges in the performance space to its associated tolerance ranges in the signature space (We call such a procedure implicit functional testing). Taking into account the specificity of SI circuit, catastrophic and parametric fault model for testing are constructed. A fifth order Butterworth low-pass filter and a sixth order Elliptic band-pass filter have been used as test benches to assess the effectiveness of the proposed technique. Test results demonstrate that high fault coverage can be achieved with low cost test equipments.     

基于边界扫描技术的板级BIT设计及测试策略

随着超大规模集成电路(VLSI)、表面安装器件(SMD)、多层印制电路板(MPCB)等技术的发展，常规BIT设计面临挑战。为解决上述问题，本文提出了一种基于边界扫描技术的板级BIT的扫描器件置入法及其测试策略。该方法操作简单，经济实用，一旦广泛使用，无疑将会有很好的军事经济效益。