一种桥梁目标识别方法的研究

在并行黑板模型研究的基础上,提出将写生式分割策略用于桥梁目标识别的图象分割思想。基于该分割思想,在黑板模型试验床ＣＰＥＳ上建立了问题求解模型,并进行了桥梁目标识别,实验结果表明,上述方法在识别速度和识别虚警概率等方面效果较好。     

一种使用黑板模型实现的图象分割策略及在桥梁目标识别中的应用

本文首先提出了一种用从自然背景中分割出人工物体的方法，即写生成分割策略，并把它用于一类桥梁目标的识别研究，本文接着研究了使用黑板模型实现写生成分割策略的问题，并在黑板模型试验床ＣＰＥＳ上使用写生式分割实现了桥梁目标的识别，取得了良好的识别效果。     

并行DSP处理器上JPEG算法的实现研究

ＪＰＥＧ算法由于效率高和实用性强获得了广泛的应用;而并行处理器ＤＳＰ具有高效的并行处理能力,因而适合于图象的实时处理。提出了在ＴＩ的并行处理器ＤＳＰ－Ｃ８０上并行和快速实现ＪＰＥＧ算法的方法,实现了高速实时图象压缩。     

PBASE的并行查询处理策略

本文详述了独具特色的ＰＢＡＳＥ并行查询处理策略及实现方法。ＰＢＡＳＥ的并行查询处理策略吸取了原型系统ＸＰＲＳ和Ｖｏｌｃａｎｏ中的先进技术，并基于原来的国产数据库系统ＣＯＢＡＳＥ中查询的流水线策略，具有更高的并行度和更好的可行性。     

多处理器MPEG2并行解码系统的设计

ＭＰＥＧ２运动图像及伴音压缩标准是许多视频服务应用的核心算法。基于软件结合多处理器的并行系统实现ＭＰＥＧ２算法解压，不仅灵活适用于多种ＭＰＥＧ２产品的回放功能，避免了硬件芯片解压的局限性，而且随着个人计算机的普及和性能的提高，这种系统适配卡方案可以令个人计算机拥有更多的ＭＰＥＧ２服务功能，对ＭＰＥＧ２系列标准更新算法的研究和测试工作也带来方便。本文分析了ＭＰＥＧ２解码对实现系统的要求，特别是解压处理时各部分运算量和数据传输、处理的要求。根据这些数据本文基于多种ＴＭＳ３２０Ｃ４０并行处理系统板，对ＭＰＥＧ２输入码流的数据分割，并行解码存储控制和通信、解码算法复杂度等问题进行了实验和分析，据此得到相应的设计选择和数据。最后提出了ＭＰＥＧ２并行处理解码系统的设计方案。     

从软件角度看多处理器

我们使用ＳＵＩＦ研究编译程序实现了对各种ＳＰＥＣｆｐ基准程序的并行化。另外，地在一台８个处理器的机器上运行这些程序，我们还达到了ＳＰＥＣｆｐ速度撮高纪录。     

应用嵌套排序的并行CHOLESKY分解算法

应用嵌套排序的并行ＣＨＯＬＥＳＫＹ分解算法迟学斌（中国科学院计算中心）ＰＡＲＡＬＬＥＬＣＨＯＬＥＳＫＹＤＥＣＯＭＰＯＳＩＴＩＯＮＵＳＩＮＧＮＥＳＴＥＤＤＩＳＳＥＣＴＩＯＮＴＥＣＨＮＯＬＯＧＹ￥ＣｈｉＸｕｅｂｉｎ（ＣｏｍｐｕｔｉｎｇＣｅｎｔｅｒ，Ａｃａ...     

SPECweb99：最晰Web服务器性能基准测试

１９９９年８月ＳＰＥＣ发布了最新Ｗｅｂ服务器性能基准测试ＳＰＥＣｗｅｂ９９,从而为信息系统建设中Ｗｅｂ服务器设备选型提供了有力的参考工具。简要介绍了ＳＰＥＣＷｅｂ９９,与ＳＰＥＣｗｅｂ９６作了比较,并指出了它存在的一些不足。     

一种基于二叉树的Cache一致性目录方法

本文提出了一种高度并发的Ｃａｃｈｅ一致性方法，着重描述了它的并发性，并且通过和ＩＥＥＥＳＣＩ协议的性能比较，表明这种Ｃａｃｈｅ一致性方法具有较好的伸缩能力，适于Ｓ２ＭＰ结构。     

基于TRANSPUTER网络的函数式语言的并行抽象机模型

本文基于函数式语言的并行ＬＥ计值语义，提出了一个针对ＴＲＡＮＳＰＵＴＥＲ网络的函数式语言的并行抽象机模型──并行ＬＥＭＡＣＨＩＮＥ．在该抽象机中由于ＬＥ计值分析方法的采用减少了函数式语言的惰性语义所带来的开销，并且在并行性开发中引入惰性计值的思想在保证充分利用系统中的并行处理能力的同时，基于ＴＨＲＥＡＤ的惰性进程生成法减少了一些不必要的并行性开发所带来的开销．双向链表的栈模型亦对并行进程的实现效率有较大的提高，原型系统的测试显示系统具有较高的执行效率．     

一个基于面向对象方法的并行黑板系统的设计

本文论述了用面向对象的系统分析与设计方法和面向对象的编程技术构造大型、复杂的并行黑板实时控制系统的思想和方法。文章以四辊冷连轧机为对象给出了一个设计实例并给出了一个通用的实时控制并行黑板结构ＲＴＣＢ。贯穿全文的一个很重要的思想就是要致力于开发面向对象方法和黑板模型的潜在的并行、并发特性以及所构造系统的可扩充性和易维护性。     

Parallel execution of Prolog with granularity control

This paper presents a system for parallel execution of Prolog supporting both independent conjunctive and disjunctive parallelism. The system is intended for distributed memory architecture and is composed of a set of workers with a hierarchical structure scheduler. The execution model has been designed in such a way that each worker's environment does not contain references to terms in other environments, thus reducing communication overhead. In order to guarantee the improvement of the performance by the parallelism exploitation, a granularity control has been introduced for each kind of parallelism. For conjunctive parallelism PDP applies a control based on the estimation provided by CASLOG. The features of the system allow to introduce this control without adding overhead. For disjunctive parallelism PDP controls granularity by applying a heuristic-based method, which can be adapted to other parallel Prolog systems. Different scheduling policies have also been tested. The system has been implemented on a transputer network and performance results show that it provides a high speedup for coarse grain parallel programs.     

Parallel Image Reconstruction in Real-Time Ultrasound Process Tomography for Two-phased Flow Measurements

This paper investigates different parallel-processing architectures as a means of achieving real-time ultrasound tomographic imaging capability. The real-time numerical image reconstruction is implemented by a parallel processor network and DSP controlled data acquisition electronics. The parallel imaging technique developed for the present work has been shown to be capable of achieving the necessary real-time image generation rate (100 frames per second on a 100 × 100 image array for software image reconstruction) and an average update frequency of 30 frames per second when acquiring data from the hardware. The parallel image processing algorithm which combines geometric and algorithmic parallelism aiming at optimizing the parallel efficiency of the processors of the array has been implemented and verified. The experimental imaging results generated by the parallel imaging system are presented and the dynamic performance of the parallel system are discussed.     

Metasystems: An Approach Combining Parallel Processing and Heterogeneous Distributed Computing Systems

A metasystem is a single computing resource composed of a heterogeneous group of autonomous computers linked together by a network. The interconnection network needed to construct large metasystems will soon be in place. To fully exploit these new systems, software that is easy to use, supports large degrees of parallelism, and hides the complexity of the underlying physical architecture must be developed. In this paper we describe our metasystem vision, our approach to constructing a metasystem testbed, and early experimental results. Our approach combines features from earlier work on both parallel processing systems and heterogeneous distributed computing systems. Using the testbed, we have found that data coercion costs are not a serious obstacle to high performance, but that load imbalance induced by differing processor capabilities can limit performance. We then present a mechanism to overcome load imbalance that utilizes user-provided callbacks.     

DIALOG — A dataflow model for parallel execution of logic programs

The paper presents a dataflow execution model, DIALOG, for logic programs which operates on an intermediate virtual machine. The virtual machine is granulated at clause argument level to exploit argument parallelism through unification. The model utilises a new variable binding scheme that eliminates dereference operations for accessing variables, and therefore supports OR-parallelism in the highly distributed dataflow environment. The model has been implemented in Occam. A conventional dataflow architecture in support of the model has been simulated as a testbed for the evaluation. The simulation indicates some encouraging results and suggests future improvements.     

A unified distance transform algorithm and architecture

Standard distance transform algorithms produce approximate results and are unsuitable for real-time implementation since they require massive parallelism. A new unified algorithm that computes distance and related nearest feature transforms concurrently for arbitrary bit maps based on any distance function from a broad class is presented. The algorithm has an efficient implementation on serial processors and a unified transform architecture is proposed for feasible real-time performance based on parallel row followed by parallel column scanning. Its importance lies in that it supports real-time performance and a broader set of machine vision applications than the standard approach.     

Embedded system for contrast enhancement in low-vision

This paper presents a real-time contrast enhancement system, implemented in FPGA and adapted to display the processed images on a Head Mounted Display (HMD). A novel visual processing scheme is proposed which combines a version of the algorithm known as Contrast Limited Adaptive Histogram Equalization (CLAHE) with a spatial filtering based on a bio-inspired retina model. The system is designed so that visually impaired people can improve their functionality in environments with non-uniform lighting or with abrupt changes in lighting conditions. The parallelism offered by FPGA devices allow to achieve real-time processing with VGA-resolution images, reaching up to 60 frames per second. This system, developed on a FPGA of reduced complexity, has been compared in performance with a parallel implementation on a portable platform based on GPU.