一种新型二元判定图器件和电路

提出了一种基于二元判定图(BDD)原理的新型逻辑器件和电路.BDD器件以电流模式的开关电流存储器为基本单元,具有符合二元判定图的两向通路的特点.用这种器件按照BDD树形图可以构成任意形式的组合逻辑电路.给出了或门、异或门及四位加法器电路的例子,并使用HSPICE仿真器进行了仿真,验证了这种器件及其电路的正确性.     

面向多输出电路的BDD拼接构造

二元判定图(Binary Decision Diagram,BDD)的有效描述将大大提高验证和测试生成效率。作者根据电路结构的特点,以标准门的BDD为基础,从原始输入到输出,通过逐级拼接,极有效地完成电路的BDD构造。另外根据验证和测试的需要,在BDD拼接过程中,提出通过可观值的定义获得有效路径的方法。实验证明,作者提出的方法简单、直观而且有效。     

时序电路的状态验证研究与设计

采用二元判定图(BDD)作为工具来描述时序电路是非常有意义和有效的.本文通过对BDD的简化达到对状态变换图(STG)输入、路径和状态的压缩,从而提高状态遍历的效率,另外根据电路的特点,提出状态冲突和不相交分解的启发技术以有效地完成验证.     

单电子晶体管全加器电路设计

基于单电子晶体管(SET)的I-V特性和二叉判别图数字电路的设计思想,改进了二叉判别图(BDD))单元,得到了一类基本逻辑门电路,进而提出了一种由11个BDD)单元即22个SET构成的全加器电路单元。SPICE宏模型仿真结果验证了设计的正确性。     

网络可靠性BDD分析中选择最优启发式边排序策略

网络可靠性二元决策图(BDD)分析方法的计算复杂度与BDD的尺度大小密切相关,而BDD的尺度大小取决于边排序策略。由于边排序问题是一个NP-完全问题,没有形式化的准则可为工程网络选择一个较好的启发式策略。文章中,使用基于边界集概念的启发式策略选择方法,为网络可靠性BDD分析做出了新的贡献。实验研究表明,所使用的选择方法可以使大部分的研究案例生成高性能的边排序,进而可以高效地实现基于BDD的大型网络可靠性分析。     

结合二叉判决图和布尔可满足性的等价性验证算法

本文提出了一种结合二叉判决图BDD和布尔可满足性SAT的新颖组合电路等价性验证技术.算法是在与/非图AIG中进行推理,并交替使用BDD扩展和基于电路SAT解算器简化电路.如尚未解决,将用基于合取范式SAT解算器进行推理.与已有算法相比主要有如下改进:在AIG中结合多种引擎进行简化,不存在误判可能;充分利用了基于电路解算器和基于合取范式解算器各自优点,减小了SAT推理的搜索空间.实验结果表明了本算法的有效性.     

MMIC—单片式微波集成电路

由于近年来半导体制造技术的发展，例如氮化物自我排列工艺的成熟，离子掺入控制水平的提高，所以才能生产出MMIC器件。在这种器件内，电阻器采用适合高频率应用的薄膜电阻器，且制作在芯片上，使器件内部的各零件之间几乎无连线，电路感抗可降到最低值，提高了MMIC的高频特性、MMIC工作频率实际可达18GHz以上，频宽高达4GHz。它的用途很广，可应用于所有的发射机或接收机的射频和中频电路。下面分5个方面介绍MMIC。1．典型的MMIC放大电路MMIC放大电路如图1所示，虚线框内的元件都包含在MMIC器件中。为了使V1、V2晶体管具有确…     

自动化技术、计算机技术

TP112005061345基于遗传禁忌混合策略的二叉判定图最小化算法研究/王明全,于海斌(中国科学院沈阳自动化研究所)//信息与控制.―2005,34(2).―142～146.提出了一种新的动态启发式二叉判定图(BDD)最小化算法,该算法将遗传算法的全局搜索能力和禁忌搜索的邻域搜索策略相结合来寻找BDD的最优变量排序,以实现BDD结点规模最小化。实验结果表明该算法性能优于其它启发式算法。图2表1参10TP132005061346不确定混沌系统的直接自适应神经网络控制/谭文,王耀南(湖南科技大学信息与电气工程学院)//模式识别与人工智能.―2005,18(1).―12～16.提出…     

使用布尔可满足性的组合电路等价性验证算法

该文提出了一种使用布尔可满足性SAT的新颖组合电路等价性验证技术。算法是在联接电路(Miter circuit)中进行推理来简化验证问题,推理中使用了与／非图结构简化、BDD扩展、隐含学习多种方法,最后使用有效SAT解算器zChaff解决验证任务。该算法综合了BDD和SAT的优点,限制BDD构建大小避免了内存爆炸,推理简化减小了SAT搜索空间。ISCAS85电路实验结果表明了本算法的有效性。     

一种基于状态转换图的时序电路等价验证算法

提出一种基于状态转换图的时序电路等价验证算法。此算法通过验证两时序电路的状态转换图是否同构．得到两电路是否等价的信息。若两状态转换图同构，则两图中的状态可一一匹配为等价状态对，算法将状态转换图存储为待验证等价状态对的形式，若所有待验证等价状态对均为等价，则两时序电路等价，反之，则不等价。此算法对ISCAS89测试电路进行验证，与基于BDD方法的SIS系统和基于时间帧展开算法相比，均有较好的结果。     

Single-electron logic device based on the binary decision diagram

The unit device consists of four tunnel junctions and operates as a two-way switch for single-electron transport. Any combinational logic can be implemented by connecting identical unit devices into a cascade to build the tree of a BDD graph. Several sample designs are presented for logic circuits of NAND, NOR, exclusive-OR, and AND-OR combinational logic. Computer simulation shows that the designed circuits perform the logic operations correctly     

单电子晶体管的I-V特性数学模型及逻辑应用

基于正统单电子理论，提出了单电子晶体管的I-V特性数学算法改进模型。该模型的优点是：考虑了背景电荷的影响，可由实际物理参数直接获得，支持双栅极工作，便于逻辑电路的分析。研究了背景电荷和各物理参数对I-V特性及跨导的影响，讨论了双栅极单电子晶体管的逻辑应用：简化了“异或”逻辑电路，改进了二叉判别图电路的逻辑单元。     

CPLD实现雷达自动增益控制的优化

复杂的可编程逻辑器件可以完成较大规模的组合逻辑电路设计，提高系统的集成化。本文介绍了复杂可编程逻辑器件和电路设计的一般流程，以及数字自动增益控制电路的组成和采用CPLD设计的实现。     

A single electron binary-decision-diagram quantum logic circuit based on Schottky wrap gate control of a GaAs nanowire hexagon

A novel hexagonal binary-decision-diagram (BDD) quantum logic circuit approach for III-V quantum large scale integrated circuits is proposed and its basic feasibility is demonstrated. In this approach, a III-V hexagonal nanowire network is controlled by Schottky wrap gates (WPGs) to implement BDD logic architecture by path switching. A novel single electron BDD OR logic circuit is successfully fabricated on a GaAs nanowire hexagon and correct circuit operation has been confirmed from 1.5 K to 120 K, showing that the WPG BDD circuit can operate over a wide temperature range by trading off between the power-delay product and the operation temperature.     

Exact reliability analysis of combinational logic circuits

A novel method is presented for the exact reliability analysis of combinational logic circuits. A model is developed that allows the logic circuit to be presented by a circuit equivalent graph (CEG). The reliability is analyzed by a systematic searching of certain subgraphs from the CEG. A computer algorithm and an example are given. The method gives the exact solution to the combinational logic circuit reliability-analysis problem. This is achieved by proper gate/circuit modeling, which allows the enumeration of all redundant fault vectors in a given circuit. Due to the concept of dominance among fault vectors, the number of necessary enumerations is appreciably reduced, and thus circuits with a few tens of gates can be efficiently analyzed     

BILCO: built in testing method for combinational logic circuits

The testing of digital logic circuits has become quite complex owing to miniaturisation and its associated increase in circuit function per unit area. Methods have been devised for testing ASIC products and, latterly, board level products. A new method (BILCO) is presented for probing asynchronous combinational logic circuits using a novel development of scan path principles     

一款消除浮空点并自锁存的老化预测传感器

针对负偏置温度不稳定性引起的组合逻辑电路老化,提出了一款消除浮空点并自锁存的老化预测传感器。该传感器不仅可以预测组合逻辑电路老化,而且能够通过传感器内部的反馈来锁存检测结果,同时解决稳定性校验器在锁存期间的浮空点问题,其延时单元为可控型延时单元,可以控制其工作状态。使用HSPICE软件进行仿真,验证了老化预测传感器的可行性,可以适用于多种环境中且不会影响传感器性能。与同类型结构相比,该传感器的稳定性校验器能够对检测结果进行自锁存,使用的晶体管数量减少了约8%,平均功耗降低了约20%。     

判奇电路实现方法探讨

以三输入判奇电路设计为例,通过对其输出函数表达式的形式变换,分别采用多种门电路及译码器、数据选择器等74系列器件进行电路设计,给出了7种电路实现形式,并分析了各种电路实现的优缺点。此例说明了组合逻辑电路设计的灵活性及电路实现的多样性。所采用的设计方法对其他组合逻辑电路设计具有一定的启发与指导意义。     

A stuck fault model for dynamic CMOS combinational circuits

This paper utilizes the logic transistor function (LTF), that was devised to model the static CMOS combinational circuits at the transistor and logic level, to model the dynamic CMOS combinational circuits. The LTF is a Boolean representation of the circuit output in terms of its input variables and its transistor topology. The LTF is automatically generated using the path algebra technique. The faulty behavior of the circuit can be obtained from the fault-free LTF using a systematic procedure. The model assumes the following logic values (0, 1, I, M), where I, and M imply an indeterminate logical value, and a memory element, respectively. The model is found to be efficient in describing a cluster of dynamic CMOS circuits at both the fault-free and faulty modes of operation. Both single and multiple transistor stuck faults are precisely described using this model. The classical stuck-at and non classical stuck open and short faults are analyzed. A systematic procedure to produce the fault-free and faulty LTFs for different implementations of the dynamic CMOS combinational circuits is presented.     

Synthesis of multiple input-change hazard-free combinational switching circuits without feedback†

This paper deals with hazards on outputs of combinational circuits without feedback for multiple input changes. A procedure is given to decompose a Boolean function into a feedback free circuit. The procedure either gives a logic hazard-free circuit or shows that the Boolean function cannot be broken down into a feedback free circuit which is free of logic hazards for multiple input changes. The procedure proves that all multiple input change combinational circuits cannot be implemented without dynamic logic hazards with no internal feedback. The result is therefore considerably different than the single input change and multiple input change static logic hazard cases.