A 10-bit 50 MS/s SAR ADC in 65 nm CMOS with on-chip reference voltage buffer

This paper presents the design of a 10-bit, 50 MS/s successive approximation register (SAR) analog-to-digital converter (ADC) with an on-chip reference voltage buffer implemented in 65 nm CMOS process. The speed limitation on SAR ADCs with off-chip reference voltage and the necessity of a fast-settling reference voltage buffer are elaborated. Design details of a high-speed reference voltage buffer which ensures precise settling of the DAC output voltage in the presence of bondwire inductances are provided. The ADC uses bootstrapped switches for input sampling, a double-tail high-speed dynamic comparator and split binary-weighted capacitive array charge redistribution DACs. The split binary-weighted array DAC topology helps us to achieve low area and less capacitive load and thus enhances power efficiency. Top-plate sampling is utilized in the DAC to reduce the number of switches. In post-layout simulation which includes the entire pad frame and associated parasitics, the ADC achieves an ENOB of 9.25 bits at a supply voltage of 1.2 V, typical process corner and sampling frequency of 50 MS/s for near-Nyquist input. Excluding the reference voltage buffer, the ADC consumes 697 μW and achieves an energy efficiency of 25 fJ/conversion-step while occupying a core area of 0.055 mm².     

Noise analysis and characterization of a sigma-delta capacitive microaccelerometer

This paper reports a high-sensitivity low-noise capacitive accelerometer system with one micro-g//spl radic/Hz resolution. The accelerometer and interface electronics together operate as a second-order electromechanical sigma-delta modulator. A detailed noise analysis of electromechanical sigma-delta capacitive accelerometers with a final goal of achieving sub-/spl mu/g resolution is also presented. The analysis and test results have shown that amplifier thermal and sensor charging reference voltage noises are dominant in open-loop mode of operation. For closed-loop mode of operation, mass-residual motion is the dominant noise source at low sampling frequencies. By increasing the sampling frequency, both open-loop and closed-loop overall noise can be reduced significantly. The interface circuit has more than 120 dB dynamic range and can resolve better than 10 aF. The complete module operates from a single 5-V supply and has a measured sensitivity of 960 mV/g with a noise floor of 1.08 /spl mu/g//spl radic/Hz in open-loop. This system can resolve better than 10 /spl mu/g//spl radic/Hz in closed-loop.     

Fixed-pattern noise in photomatrices

Two MOS photomatrix configurations, voltage sampling and recharge sampling, have been compared with regard to sources of fixed-pattern noise. Voltage sampling provides a high-amplitude low-impedance photosignal, with FPN primarily due to threshold variation in the amplifying MOST at each element. Recharge sampling is used for large high-yield rapidly scanned arrays, with FPN caused mostly by variations in spurious capacitive breakthrough. Production peak-to-peak signal to FPN ratios are 20:1 for voltage sampling and 50:1 for recharge sampling.     

Highly Adaptive Transducer Interface Circuit for Multiparameter Microsystems

A reconfigurable transducer interface circuit that combines the communication and signal conditioning necessary to link a variety of sensors and actuators to a microsystem controller is reported. The adaptive readout circuitry supports high-resolution signal acquisition from capacitive, resistive, voltage and current mode sensors with programmable control of gain and offset to match sensor range and sensitivity. The chip accommodates sensor self test and self calibration and supports several power management schemes. It provides digital and analog outputs to control actuators and a standard interface to peripheral components. The 2.2times2.2 mm CMOS chip was fabricated in 0.5-mum, 3-metal, 2-poly process, dissipates ~50 muW at 3.3 V in a typical multisensor application utilizing periodic sleep mode, and can read out a wide range of sensors with high sensitivity. A prototype microsystem with a microcontroller and MEMS pressure, humidity, and temperature sensors has been implemented to characterize interface chip performance     

A 4-Gb/s/pin low-power memory I/O interface using 4-level simultaneous bi-directional signaling

This paper presents a simultaneous bi-directional (SBD) 4-level I/O interface for high-speed DRAMs. The data rate of 4 Gb/s/pin was demonstrated using a 500-MHz clock generator and a full CMOS rail-to-rail power swing. The power consumed by the I/O circuit was measured to be 28 mW/pin, when connected to a 10-pF load, at a 1.8-V supply voltage. The transmitter uses a 4-level push-pull linear output driver and a 4-level automatic impedance controller, achieving the reduction of driver currents and the voltage margin as large as 200 mV. The receiver employs a hierarchical sampling scheme, wherein a differential amplifier selects three out of six reference voltage levels. This scheme ensures minimized sampling power and a wide common-mode sampling range. The 6-level reference voltage for sampling is generated by the combination of the transmitter replica. The proposed I/O interface circuits are fabricated using a 0.10-/spl mu/m, 2-metal layers DRAM process, and the active area is 330 /spl times/ 66 /spl mu/m/sup 2/. It exhibits 200 mV /spl times/ 690 ps eye windows on the given channel with a 1.8-V supply voltage.     

A 10-bit 50-MS/s Pipelined ADC With Opamp Current Reuse

Power and area saving concepts such as operational amplifier (opamp) bias current reuse and capacitive level shifting are used to lower the analog power of a 10-bit pipelined analog-to-digital converter (ADC) to 220 muW/MHz. Since a dual-input bias current reusing opamp performs as two opamps, the opamp summing nodes can be reset in every clock cycle. By using only N-channel MOS (NMOS) input stages, the capacitive level shifter simplifies the gain-boosting amplifier design and enables fast opamp settling with low power-consumption. The prototype achieves 9.2/8.8 effective number of bits (ENOB) for 1- and 20-MHz inputs at 50 MS/s. The ADC works within the temperature range of 0deg to 85 degC and the supply voltage from 1.62 to 1.96 V with little measured loss in the ENOB. The chip consumes 18 mW (11 mW for the analog portion of the ADC and 7 mW for the rest including buffers) at 1.8 V, and the active area occupies 1.1 times 1.3 mm² using a 0.18-mum complementary metal oxide semiconductor (CMOS) process     

Clock Delayed Domino Logic With Efficient Variable Threshold Voltage Keeper

In this paper, efficient clock delayed domino logic with variable strength voltage keeper is proposed. The variable strength of the keeper is achieved through applying two different body biases to the keeper. The circuits used to generate the body biases are called capacitive body bias generator and cross-coupled capacitive body bias generator. Compared to a previous work, the body bias generator circuits presented in this paper are simpler and do not require double or triple power supply while consuming less area and power. To show the efficiency of the proposed technique, the implementation of a carry generator circuit by the proposed techniques and the previous work are compared. The simulation results for standard CMOS technologies of 0.18 mum and 70 nm show considerable improvements in terms of power and power delay product. In addition, the proposed technique shows much less temperature dependence when compared to that of previous work     

基于三轴加速度计的倾斜角传感器的研究与设计

倾斜角度是生活或工业中需要测量的一个重要物理量,对于空间物体姿态的测量,传统的一轴、两轴倾斜角传感器在摆幅和方位上不能兼顾。在此对全固态电容式微加速度传感器进行研究,通过进行零刻度偏移补偿、横轴传感补偿、数据融合等方法提高测量精度。采用三轴加速度计设计了一个全摆幅、全方位、高精度的智能化三轴倾斜角传感器。     

A 90 μW continuous-time front-end with 10b SAR-ADC for capacitive MEMS accelerometers

This paper presents a low power read-out front-end for 3-axis MEMS capacitive accelerometer. The front-end includes the analog preamplifier (to sense the signal coming from the MEMS) and a Successive-Approximation 10b A/D Converter, for digitalization and off-chip digital-signal-processing. Power minimization is achieved by using a continuous-time sensing preamplifier (i.e. constant-charge capacitance-to-voltage conversion) and SAR-ADC with bridge capacitive reduction. Preamplifier programmable in-band gain allows to accommodate different MEMS sensitivities. A very high-impedance MOS transistor is used for MEMS biasing, thus providing very low frequency (<1 Hz) AC coupling. In a 0.13 μm CMOS technology, the full channel consumes 90 μW from a single 1.2 V supply voltage, and achieves an equivalent 67.9 dB_Full-Scale@SNR in [1 Hz–4 kHz] bandwidth by exploiting oversampling ratio.     

MEMS高精度电容读出电路的单芯片集成研究

MEMS电容式传感器的迅速发展为后续集成化读出电路的设计提出了巨大挑战.系统地分析了制约微传感器高精度电容读出电路设计的主要因素,回顾了目前主要的几种读出电路结构,阐述了这些电路的基本原理,并对影响电路分辨率的主要设计参数进行了分析和对比,最后探讨了电容式读出电路设计的发展趋势.     

A 10-b 20-Msample/s low-power CMOS ADC

A single-ended input but internally differential 10 b, 20 Msample/s pipelined analog-to-digital converter (ADC) is demonstrated with 4 mW per stage using a single 5 V supply. The prototype ADC made of an input sample and hold (S/H) plus 8 identical unscaled pipelined stages consumes 50 mW including power consumed by a bias generator and two internal buffer amplifiers driving common-mode bias lines. Key circuits developed for this low-power ADC are a dynamic comparator with a capacitive reference voltage divider that consumes no static power, a source-follower buffered op amp that achieves wide bandwidth using large input devices, and a self-biased cascode biasing circuit that tracks power supply variation. The ADC implemented using a double-poly 1.2 μm CMOS technology exhibits a DNL of ±0.65 LSB and a SNDR of 54 dB while sampling at 20 MHz. The chip die area is 13 mm²     

A novel low-power,low-offset,and high-speed CMOS dynamic latched comparator

A novel dynamic latched comparator with offset voltage compensation is presented. The proposed comparator uses one phase clock signal for its operation and can drive a larger capacitive load with complementary version of the regenerative output latch stage. As it provides a larger voltage gain up to 22 V/V to the regenerative latch, the input-referred offset voltage of the latch is reduced and metastability is improved. The proposed comparator is designed using 90 nm PTM technology and 1 V power supply voltage. It demonstrates up to 24.6% less offset voltage and 30.0% less sensitivity of delay to decreasing input voltage difference (17 ps/decade) than the conventional double-tail latched comparator at approximately the same area and power consumption. In addition, with a digitally controlled capacitive offset calibration technique, the offset voltage of the proposed comparator is further reduced from 6.03 to 1.10 mV at 1-sigma at the operating clock frequency of 3 GHz, and it consumes 54 μW/GHz after calibration.     

High voltage gain CMOS OTA for micropower SC filters

The letter describes a single stage operational transconductance amplifier (OTA) with cascoded output transistors, designed for micropower switched-capacitor filters. The device features high voltage gain (>90 dB) under capacitive load, large output swing, very low power consumption (5 ?W at 3 V supply voltage for 100 kHz bandwidth with 10 pF load) and reduced circuit area (<0.1 mm2).     

A new 0.35 μm CMOS electronic interface for wide range floating capacitive and grounded/floating resistive sensor applications

In this paper we propose a novel interface circuit suitable for the read-out of both wide range floating capacitive and grounded/floating resistive sensors. This solution, employing only two Operational Amplifiers (OAs) as active blocks and some passive components, is based on a square-wave oscillating circuit topology which, instead of a voltage integration typically performed by other solutions in the literature, operates a voltage differentiation. Therefore, the proposed circuit, performing an impedance-to-period (Z–T) conversion, results to be suitable as first analog front-end for both wide variation capacitive (e.g., relative humidity) and resistive (e.g., gas) sensors. Its sensitivity and dynamic range can be easily set through external passive components. Preliminary experimental measurements, which have characterized and validated this solution, have been conducted through a suitable prototype PCB fabricated with discrete commercial components. Then, the proposed interface has been also designed at transistor level, in a standard CMOS technology (AMS 0.35 um), developing a single-chip integrated circuit with low-voltage (1.8 V, single supply) low-power (about 350 μW) characteristics in a very small silicon area (lower than 0.6 mm²) which results to be suitable for sensor array configurations and portable applications. Further experimental results, achieved utilizing commercial sample resistors and capacitors to emulate sensor behavior, have shown a linear trend and a satisfactory accuracy in the evaluation of floating capacitive (in the range 10 pF–1 μF), grounded resistive (in the range 150 kΩ–1.5 MΩ) and floating resistive (in the range 10 MΩ–1 GΩ) variations, also when compared to other solutions presented in the literature. The satisfactory interface behavior has been also confirmed by the measurement of both relative humidity through the commercial sensor Honeywell HCH-1000 (capacitive) and carbon monoxide CO through the commercial air quality sensor FIGARO TGS-2600 (resistive).     

电容数字转换器AD7745的工作原理和应用

AD7745是AD公司生产的具有I2C总线接口的电容数字转换器。该转换器支持单端电容输入和差分式电容输入,同时在片内集成了温度传感器,可以用于代替系统中的温度传感器。该芯片广泛的应用于生化探测、压力探测、电压探测、杂质探测等领域。介绍AD7745的功能原理和工作模式,同时给出一种使用该芯片的实际应用。     

n沟6H-SiC MOSFET阈值电压的温度特性模拟与分析

分析了n沟6H—SiCMOSFET的杂质不完全离化和SiO2—SiC界面存在大量界面陷阱等问题，研究了影响6H—SiCMOSFET器件阅值电压温度特性的诸因素。通过解析式计算和MEDICI软件模拟，得到了多种因素共同作用下的器件闪值电压的温度特性。研究表明，体内杂质的不完全离化、表面空间电荷层中的杂质离化程度和特定分布的界面电荷，对阅值电压的温度特性有显著的影响。     

新型电容式MEMS加速度计数字接口电路设计

MEMS加速度计接口电路主要采用传统sigma-delta架构实现,但这种方式中的电路失调电压很容易产生积分饱和现象．为解决这个问题,本文设计了一种可以用于钻井、石油勘探等微弱信号检测的新型数字电容接口电路．该设计在电容式MEMS加速度传感器基础上,采用FPGA实现数字三阶环路滤波器,构成5阶sigma-delta系统．采用数字环路滤波器降低了ASIC模拟电路版图设计与芯片测试难度,利于快速优化环路滤波器设计参数,改善系统稳定性和优化系统噪声性能．前置放大器采用一种相对简单的相关双采样技术,能够有效减小前置放大器的失调电压．根据MEMS加速度计前置放大器输出信号符合正态分布的特点,设计了带有一定预测功能的8-bit瞬时浮点ADC,实现模拟与数字环路滤波器互联．在200Hz带宽内,该接口电路系统噪声基底达到53．09ng／rt（Hz）,满足系统噪声设计要求．前置放大器与ADC采用XFAB XH018混合信号CMOS工艺流片,开环测试表明,前置放大器的灵敏度和噪声分别为0．69V／pF和3．20μV／rt（Hz）．     

对电源及温度不敏感的电流可调的CMOS电荷泵电路的设计

设计了一种电流可调的CMOS电荷泵电路,其中采用了带隙基准源、低drop-out调压器及电容式直流-直流电压升压器为电荷泵电路提供电源电压,此电压不受外部供电电压及温度变化的影响;同时,电荷泵电路中的参考电流源本身也对温度变化不敏感.电路设计采用0.18μm 1.8V标准的数字CMOS工艺.模拟结果表明电路性能令人满意.     

Low noise accelerometer microsystem with highly configurable capacitive interface

This paper presents a low noise accelerometer microsystem with a highly configurable capacitive interface circuit. A programmable capacitive readout circuit is designed to minimize the offset and gain error due to the parasitic capacitance mismatch and the process variations. The interface circuit is implemented in a 0.5 μm 2P3M CMOS technology with EEPROM. The interface circuit and MEMS sensing element are integrated in a single package, and consist the accelerometer microsystem. The supply voltage and supply current of the system are 5 V and 1.17 mA, respectively. The input range and gain are 2.5 V and 0.5 V/g, respectively. The max–min gain error and max–min offset error after calibration was measured to be 1.2% FSO and 3.3% FSO, respectively. The signal to noise ratio (SNR) and noise equivalent resolution (NER) are measured to be 93.1 dB and 110.6 μg/√Hz, respectively, when a 40 Hz, 5 g sinusoidal input acceleration is applied.     

基于双极性脉冲电压的水电导率仪控制系统的设计

介绍了一种智能型水电导率仪的测量原理及软硬件结构.仪器采用双极性脉冲电压作为电导率测量的激励源,较好地解决高纯水电导率测量中的极化效应和电容效应对测量结果的影响.该仪器可以实现量程自动换档,温度自动补偿,电导率超限报警,清洗池进水和放水自动控制等功能;同时系统还具有人机交互界面,数据存储,与上位PC机通信等功能.上位机软件采用LabVIEW编程,通过串口实现了电导率数据的实时采集和显示.