Parallel transmission of vehicle mirror control signals by a singleoptical fiber

Describes a vehicle mirror control signal transmission system consisting of a transmitter, a single optical fiber, and a receiver terminal. The transmitter in the mirror controller to be operated by the driver controls the mirror functions, and the receiver terminal consists of a multifrequency receiver, a data processor, mirror control circuits to control an inner rearview mirror, and a pair of outside door mirrors. Multifrequency signals at 135, 235, 335, and 435 kHz are encoded to obtain 4-bit binary data that specifies the instructions to control these mirrors. The 4-bit multifrequency signal identified as 4-bit binary data is formed in accordance with the frequency division multiplexing (FDM) scheme, fed to the voltage-controlled oscillator (VCO) to obtain the square-wave frequency modulation (SWFM) signal in accordance with the SWFM scheme, and then transmitted from the transmitter to the receiver terminal through a single optical fiber. After the 4-bit binary data is reproduced from the 4-bit multifrequency signal, the mirrors are controlled by the data processor to accomplish their operating functions satisfactorily     

Digital adaptive phase noise reduction in coherent optical links

Coherent optical links enable high-density constellations and, consequently, a higher throughput. However, the phase noise associated with the transmitter and the receiver lasers is a challenging issue in coherent lightwave systems. The authors present an approach that relies on using digital signal processing techniques to compensate for the laser phase-noise effects. The proposed approach exploits the digital processing power to address the problems arising from optical imperfections. The authors present an adaptive filtering scheme that reduces the effect of the laser phase noise and, consequently, relaxes the laser linewidth requirement. The proposed approach shows how the signal processing techniques can be exploited to compensate for the optical impairments by utilizing the continuing scale down in size and power in very large scale integration (VLSI) technology.     

A low-power all-digital FSK receiver for space applications

A frequency-shift keying (FSK) receiver has been designed for deep space applications which exhibits potential for ultra low power performance. The receiver is based on a novel, almost all-digital architecture. It supports a wide range of data rates and is very robust against large and fast frequency offsets due to Doppler. The architecture utilizes subsampling and 1-bit data processing together with a discrete Fourier transform-based detection scheme to enable power consumption dramatically lower than implementations reported in the literature. Novel and power-efficient algorithms are derived for frequency and timing tracking. Most of the power saving techniques are applicable to a variety of applications, but some are achieved by taking advantage of the asymmetric power constraints for the receiver and the transmitter as well as the absence of adjacent channel interferers. The worst-case bit-error rate (BER) performance of the receiver is just 2.5 dB below that of the optimal uncoded noncoherent FSK receiver at a BER of 10^-6 and better for lower BERs     

多相滤波的数字相干检波原理及FPGA实现

多相滤波是实现数字下变频及数字相干检波的关键技术,是雷达、声纳和通信等系统中为数字信号处理提供高质量的正交信号的有效手段。文中讨论了多相滤波的基本原理,给出了采用多相滤波的方法对中频带限信号处理的仿真分析,并结合一款脉冲压缩雷达中频数字化接收机的实现方案进行工程验证,结果表明,在技术指标上可有效克服正交通道不一致问题,具有较高的应用价值。     

RF Band‐Pass Sampling Frontend for Multiband Access CR/SDR Receiver

Radio frequency (RF) subsampling can be used by radio receivers to directly down‐convert and digitize RF signals. A goal of a cognitive radio/software defined ratio (CR/SDR) receiver design is to place the analog‐to‐digital converter (ADC) as near the antenna as possible. Based on this, a band‐pass sampling (BPS) frontend for CR/SDR is proposed and verified. We present a receiver architecture based second‐order BPS and signal processing techniques for a digital RF frontend. This paper is focused on the benefits of the second‐order BPS architecture in spectrum sensing over a wide frequency band range and in multiband receiving without modification of the RF hardware. Methods to manipulate the spectra are described, and reconstruction filter designs are provided. On the basis of this concept, second‐order BPS frontends for CR/SDR systems are designed and verified using a hardware platform.     

An Algorithm for an Adaptive Multifrequency Receiver

This paper presents a simple and effective algorithm for an adaptive multifrequency receiver that can be used for several types of multifrequency signals. This algorithm uses the ability of frequency detection of signal processing using extreme and zero-crossing points in the multifrequency signals and an adaptive second-order notch filter.     

UWB数字接收机量化阶数的研究

脉冲超宽带(I-UWB)系统采用时域宽度极窄的脉冲作为信息载体,占用的频谱极宽。在目前技术条件下,模/数转换器件是实现I-UWB全数字化接收机的难点之一。分析了量化阶数对检测I-UWB信号的影响,建立了理论模型,给出了UWB不同频谱规范下对应的仿真结果。结果表明过高的量化阶数对系统性能的改善并没有太大的贡献,4位A/D转换器就可以很可靠地检测出淹没在噪声和干扰中的I-UWB信号。     

New Realization of DFT Applied to CCITT No. 5 Telephone Signaling System

This paper describes a digital multifrequency signal receiver based on the discrete Fourier transform (DFT) principle. The new lookup table implementation for fast multiplication of an input PCM sample and a kernel sample leads to simple hardware for the operation of 128 time-multiplexed channels of the CCIT No. 5 line signal receiver. Overlap operation and guard logics are also employed to meet the signaling system requirements.     

数字合成孔径雷达接收机设计

为了解决模拟合成孔径雷达接收机带来的幅相不平衡等诸多问题,设计了一种基于高速A/D转换和FPGA高速信号处理的数字合成孔径雷达中频接收机.该设计结构简单、信号带宽大、镜频抑制比高.对多相滤波正交解调算法进行了改进,给出了数字中频接收机的工作原理和系统结构框图,设计了基于Virtex-4 FPGA的信号处理模块.仿真验证结果表明该设计完全符合系统设计参数的要求,可以应用于高分辨率合成孔径雷达.     

一种雷达接收机的优化设计与实现

本文介绍了接收机优化设计的具体思路。其主要功能是将回波信号经两次下变频处理，得到中频信号，然后将中频信号进行放大滤波处理，在进行 AGC 控制后得到功率稳定的中频信号，最终由信号处理组合进行 AD 变换、数字滤波等处理。将传统的微波接收机与中频接收机优化整合，实现接收通道功能模块化，提高了其可靠性和维修性。     

红外化学遥感数字信号处理算法的研究进展

介绍了几种为远距离红外蒸汽信号监测开发的分类器设计，频域数字滤波，时域数字滤波等数字信号处理技术。对线性分类器，分段线性分类器和神经网络分类器等在红外化学遥感系统中的应用做了初步的探讨。对背景扣除技术，频域数字滤波技术，数字滤波的切趾方法等做了简要的描述。阐述了时域滤波技术的基本原理及实际应用。展望了红外化学遥感数字信号处理算法的研究前景。     

多频GNSS射频采样接收机设计与实现

针对多频GNSS接收机采用模拟射频前端存在的缺陷,研究基于直接射频采样技术的多频GNSS接收机设计与实现。根据当前公开导航频段,设计了一种可配置、可兼容的前端数字信号处理结构,将模数转换器件紧接在天线后端,直接在射频域对导航信号进行数字化,射频以下的所有处理功能全部采用软件模块来实现,使接收机通过参数设置就可以兼容多种导航系统。对采样频率选择、本振频率选择、抽取滤波等关键技术进行了分析,基于可编程片上系统平台给出一种射频采样GNSS接收机的实现方案,分析了其中各功能模块的实现框图与工作流程,通过测试给出接收机的性能指标。      

基于Simulink的单比特数字接收机设计

瞬时测频接收机拥有大工作带宽以及高截获概率,是电子战系统的一个重要组成部分,然而它无法对同时到达的多个信号进行测频。单比特接收机是解决这个问题的一种方法,由于它采用了很低的ADC采样位数,以及直接射频采样能力和独特的测频算法,使它具有大带宽、实时测量双音信号频率信息的优异性能。相比于典型的数字接收机,自身结构也得到了极大的简化。提出了一种单比特接收机硬件设计架构,并基于Simulink工具搭建了模型,分析了这种设计的性能。该模型具有高度的灵活性,对于单比特接收机的设计与系统实现具有一定的指导意义。     

A low-power multirate differential PSK receiver for space applications

Wireless communication for deep-space and satellite applications needs to accommodate the Doppler shift caused by the movement of the space vehicle and should consume low power to conserve the onboard power. A low-power phase-shift keying (PSK) receiver has been designed for such applications. The receiver employs double differential detection to be robust against Doppler shift and uses subsampling with a 1-bit A/D converter and digital decimation architecture at the front end to achieve low-power consumption. The receiver is also designed to be programmable to operate using single-stage differential detection instead of double-stage differential detection at low Doppler rates to obtain optimum performance. Furthermore, the baseband can be employed in either direct subsampling or intermediate frequency (IF)-sampling front ends. Both front ends offer minimal power consumption and differ from traditional types by replacing some conventional analog components such as a voltage-controlled oscillator, mixer, or phase-locked loop with their digital counterparts. This eliminates problems due to dc offset, dc voltage drifts, and low-frequency (LF) noise. The paper also includes a brief discussion of the nonidealities existing in real applications. The proposed phase shift keying (PSK) receiver supports a wide range of data rates from 0.1-100 Kbps and has been implemented in a CMOS process.     

Advanced channelization for RF, microwave, and millimeterwaveapplications

An overview of the channelization function, the parallel signal processing techniques used in channelizers, the signal processing functions, and the critical channelizer parameters is given. Signal processing capabilities that use analog techniques suitable for channelized receivers are compared with those capabilities that can be obtained by using current or foreseen digital techniques. The receiver signal-processing needs are outlined, and the limitations of digital signal processing in terms of the overall receiver signal processing needs are discussed. Options and tradeoffs at the receiver and channelizer technology levels are discussed. Promising channelizer technologies, including components, that have been or potentially may be implemented with small volumes and moderate dynamic range are described. Parallel signal-processing methods, architectural techniques, and hardware for channelized receiver technologies that can be implemented in a small volume (tens of channels per in³) with a moderately high dynamic range (>50 dB) are discussed. These include the surface-acoustic-wave (SAW), bulk-acoustic-wave (BAW), magnetostatic-wave (MSW), and acoustooptical (AO) channelizer technologies. The critical signal preprocessing functions required in channelized receivers before the needed information is passed on to the host computer, so that the host computer can be operated at a possible computation rate, are discussed, and the first successful monolithic integrated circuit preprocessor component for channelizers, is presented     

A flexible adaptive FIR filter VLSI IC

The architecture and features of the Motorola DSP56200 are described. The DSP56200 is an algorithm-specific cascadable digital signal processing peripheral designed to perform the computationally intensive tasks associated with finite impulse response (FIR) and adaptive FIR digital filtering applications. The DSP56200 is implemented in high-performance, low-power 1.5-μm HCMOS technology and is available in a 28-pin DIP package. The on-chip computation unit includes a 97.5-ns 24-bit×24-bit coefficient RAM, and a 256-bit×16-bit data RAM. Three modes of operation allow the part to be used as a single, dual, or single adaptive FIR filter, with up to 256 taps per chip. In the adaptive mode, the part performs the FIR filtering and least-mean-square (LMS) coefficient update operations for a single tap in 195 ns, permitting use of the part as a 19-kHz sampling rate, 256-tap adaptive FIR filter. A programmable DC tap, coefficient leakage, and adaptation coefficient parameters in the adaptive FIR mode allow the DSP56200 to be used in a wide variety of adaptive FIR filtering applications. The performance of the part in an echo canceler configuration is presented. Typical applications of the part are also described     

A 6-bit 600-MS/s 5.3-mW Asynchronous ADC in 0.13-μm CMOS

An asynchronous analog-to-digital converter (ADC) based on successive approximation is used to provide a high-speed (600-MS/s) and medium-resolution (6-bit) conversion. A high input bandwidth (>4 GHz) was achieved which allows its use in RF subsampling applications. By using asynchronous processing techniques, it avoids clocks at higher than the sample rate and speeds up a nonbinary successive approximation algorithm utilizing a series nonbinary capacitive ladder with digital radix calibration. The sample rate of 600 MS/s was achieved by time-interleaving two single ADCs, which were fabricated in a 0.13-mum standard digital CMOS process. The ADC achieves a peak SNDR of 34 dB, while only consuming an active area of 0.12mm² and having power consumption of 5.3 mW     

A Voiceband Codec with Digital Filtering

Oversampling and digital filtering have been used to design a per-channel voiceband codec with resolution that exceeds the typical transmission system requirement by more than 15 dB. This extended dynamic range will allow for the use of digital processing in the management of signal levels and system characteristics in many telecommunication applications. Digital filtering contained in the codec provides rejection of out-of-band inputs and smoothing of the analog output that is sufficient to eliminate the need for analog filtering in most telephone applications. Some analog filtering may be required only to maintain the expanded dynamic range in cases where there is a danger of large amounts of out-of-band energy on the analog input impairing the dynamic range of the modulator. The encoder portion of the oversampled codec comprises an interpolating modulator that samples at 256 kHz followed by digital filtering that produces a 16-bit PCM code at a sample rate of 8 kHz. In the decoder, digital processing is used to raise the sampling rate to 1 MHz prior to demodulation in a 17-level interpolating demodulator. The circuits in the codec are designed to be suitable for large-scale integration. Component matching tolerances required in the analog circuits are of the order of only ± 1 percent, While the digital circuits can be implemented with fewer than 5000 gates with delays on the order of 0.1 μs. In this paper the response of the codec is described mathematically and the results are confirmed by measurements of experimental breadboard models.     

System co-optimization in wireless receiver design with TrACS

System co-optimization of the analog receiver front end circuit and the digital baseband processing could enable receiver designs with lower power budgets, as the signal processing in the digital receiver is asymmetric across circuit topologies. This paper presents a simulation tool that could assist with such co-optimized designs. TrACS (Transceiver Architecture and Channel Simulator) is an RF/DSP co-simulator, capable of providing an application-specific system-level perspective to receiver design. The simulator is especially relevant in the context of energy-constrained wireless sensor node design, where the simulator’s system perspective determines the compatibility of circuit topologies, modulation techniques and synchronization methods for various wireless scenarios. A few case studies are presented, which illustrate co-optimization of a ZigBEE receiver using TrACS.