Flexible, dry-released process for aluminum electrostatic actuators

We present an all-aluminum MEMS process (Al-MEMS) for the fabrication of large-gap electrostatic actuators with process steps that are compatible with the future use of underlying, pre-fabricated CMOS control circuitry. The process is purely additive above the substrate as opposed to processes that depend on etching pits into the silicon, and thereby permits a high degree of design freedom. Multilayer aluminum metallization is used with organic sacrificial layers to build up the actuator structures. Oxygen-based dry etching is used to remove the sacrificial layers. While this approach has been previously used by other investigators to fabricate optical modulators and displays, the specific process presented herein has been optimized for driving mechanical actuators with relatively large travels. The process is also intended to provide flexibility for design and future enhancements. For example, the gap height between the actuator and the underlying electrode(s) can be set using an adjustable polyimide sacrificial layer and aluminum “post” deposition step. Several Al-MEMS electrostatic structures designed for use as mechanical actuators are presented as well as some measured actuation characteristics     

High quality factor copper inductors integrated in deep dry-etched quartz substrates

This paper reports on an inductor fabrication method capable to deliver high quality factor (Q) and high self-resonance frequency (SRF) devices using quartz insulating substrates and thick high-conductivity copper lines. Inductors are key devices in RF circuits that, when fabricated on traditional semiconductor substrates, suffer from poor RF performances due to thin metallization and substrate related losses. Many previous works revealed that RF performances are strongly dependent on the limited metallization thickness and on the conductivity of the substrate. In this paper we demonstrate a new fabrication process to improve the Q factor of spiral inductors by patterning thick high conductive metal layers directly in a dielectric substrate. Moreover, we develop and validate accurate equivalent circuit modeling and parameter extraction for the characterization of the fabricated devices.     

Silicon-based microelectrodes for neurophysiology fabricated usinga gold metallization/nitride passivation system

The multimicroelectrode probe (microprobe) is a device used in neurophysiology to record signals from nerve cells. Microprobes typically have a number of gold recording sites supported on a narrow cantilever beam which is inserted into the tissue. Conducting tracks connect the recording sites to bonding pads on the body of the device. The metallization is insulated, except at the recording sites and bonding pads, by a passivation layer. Boron etch stop techniques can be used to produce narrow cantilever beams upon which recording sites are situated. Previously, polysilicon interconnects were used on microprobes fabricated using boron etch stop techniques, with gold inlaid onto the recording sites using a lift-off technique. This meant that mechanical jigging was required before the final shaping of the probes in potassium hydroxide (or other etch) to prevent the etch from attacking the polysilicon conductors beneath the inlaid gold. The process reported here incorporates a gold metallization layer, in conjunction with a plasma-enhanced chemical vapor deposition (PECVD) nitride passivation layer. Since both these materials etch very slowly in potassium hydroxide, no mechanical jigging, or other steps, need to be taken to protect the front of the wafer during the shaping stage. This simplifies the fabrication of these devices     

Planarity of large MEMS

A systematic approach is developed to study the planarity of large (few mm long) micromechanical cantilever beams made of μm-size features. The beams are made by the SCREAM (single crystal reactive etching and metallization) process. SCREAM beams consist of a single crystal silicon (SCS) core coated on top and sides by oxide or nitride and a metal. The sidewalls overhang the SCS core. The beams deform out of plane due to thermal and intrinsic strains of the coating films. These strains are defined and measured for plasma deposited SiO₂ and sputtered aluminum films. A linear elastic model of SCREAM cantilever beams is then developed to evaluate the deformation of the beams caused by film strains. The model predicts that the beams may bend up or down or remain planar depending on their cross-sectional design. Also, the greater the depth of the beams, the more planar they are, and a change in temperature (room temp-100°C) has little influence on planarity for beams with thin (~.2 μm) metallization. The model is validated by fabricating large (up to 2 mm long) cantilever beams, 1 and 2 μm wide, with PECVD SiO₂ and sputtered Al coatings. The deformations of the beams prior to metallization as well as before and after annealing of the metallized beams are measured. Good agreement is obtained between the experimental deformations and those predicted by the model. The paper is concluded with an example of a working, large (4×5 mm²), planar MEM device fabricated by the SCREAM process     

A low cost approach for the fabrication of microwave phase shifter on laminates

This paper presents a simple and low cost fabrication approach using extended printed circuit board processing techniques for an electrostatically actuated phase shifter on a common microwave laminate. This approach uses 15???m thin copper foils for realizing the bridge structures as well as for a spacer. A polymeric thin film deposited by spin coating and patterned using lithographic process is used as a dielectric layer to improve the reliability of the device. The prototype of the phase shifter for X-band operation is fabricated and tested for electrical and electromechanical performance parameters. The realized devices have a figure of merit of 70°/dB for a maximum applied bias potential of 85?V. Since these phase shifters can be conveniently fabricated directly on microwave substrates used for feed distribution networks of phased arrays, the overall addition in cost, dimensions and processing for including these phase shifters in these arrays is minimal.     

Fabrication of a stainless steel shadow mask using batch mode micro-EDM

A metal shadow mask for organic thin-film transistors (OTFTs) has been fabricated by batch mode electro-discharge machining (EDM). Batch mode micro-electro-discharge machining method was applied for productivity improvement. Negative electrode with multiple holes (3 × 3 or 4 × 4) was fabricated using a single tool electrode. With the negative electrode, 3 × 3 and 4 × 4 tool electrode arrays are EDMed; 6 × 6 and 16 × 16 square hole array masks were batch mode EDMed with the fabricated multi-electrodes arrays. With 4 × 4 electrode array, the productivity is improved to five times of that in the case using a single electrode. Source and drain electrodes of OTFTs were successfully patterned on a pentacene active layer through the mask, and the fabricated pentacene TFTs had good output characteristics.     

A low cost approach for the fabrication of microwave phase shifter on laminates

This paper presents a simple and low cost fabrication approach using extended printed circuit board processing techniques for an electrostatically actuated phase shifter on a common microwave laminate. This approach uses 15 μm thin copper foils for realizing the bridge structures as well as for a spacer. A polymeric thin film deposited by spin coating and patterned using lithographic process is used as a dielectric layer to improve the reliability of the device. The prototype of the phase shifter for X-band operation is fabricated and tested for electrical and electromechanical performance parameters. The realized devices have a figure of merit of 70°/dB for a maximum applied bias potential of 85 V. Since these phase shifters can be conveniently fabricated directly on microwave substrates used for feed distribution networks of phased arrays, the overall addition in cost, dimensions and processing for including these phase shifters in these arrays is minimal.

     

Optimization of a wafer-level process for the fabrication of highly reproducible thin-film MOX sensors

Thin-film metal oxide semiconductor (MOX) gas sensors are characterized by high sensitivity and fast response. Those characteristics make them very promising among the several existing technologies for the production of solid state gas sensors. Furthermore, by means of silicon micro-machining technology, MOX sensors can be made on micro hotplates, allowing to reach very low-power consumption, and the batch production guaranties a high yield. However, reproducibility and reliability are still major issues preventing the use of thin-film MOX sensors in mass-market applications.

In this work, a wafer-level fabrication process for micro-machined low-power consumption thin-film MOX sensor arrays is reported. Different solutions for the optimization of the fabrication process are investigated, aiming to increase the reproducibility. The critical technological steps related to signal generation and acquisition, like the thin-film definition and positioning and the definition of the sensing layer electrodes, have been optimized. The devices considered are 4-sensor arrays based on thin films of SnO₂ deposited by a modified rheotaxial growth and thermal oxidation (M-RGTO) technique on micro-machined low-power hotplates.

The different fabrication techniques are described in detail. 45 sensors from 3 wafers, made using the different fabrication techniques, are comparatively characterized. The spread of the main sensor functional parameters values shows an evident decrease when the optimized fabrication process is used.     

Arrays of monocrystalline silicon micromirrors fabricated using CMOS compatible transfer bonding

In this paper, we present CMOS compatible fabrication of monocrystalline silicon micromirror arrays using membrane transfer bonding. To fabricate the micromirrors, a thin monocrystalline silicon device layer is transferred from a standard silicon-on-insulator (SOI) wafer to a target wafer (e.g., a CMOS wafer) using low-temperature adhesive wafer bonding. In this way, very flat, uniform and low-stress micromirror membranes made of monocrystalline silicon can be directly fabricated on top of CMOS circuits. The mirror fabrication does not contain any bond alignment between the wafers, thus, the mirror dimensions and alignment accuracies are only limited by the photolithographic steps. Micromirror arrays with 4/spl times/4 pixels and a pitch size of 16 /spl mu/m/spl times/16 /spl mu/m have been fabricated. The monocrystalline silicon micromirrors are 0.34 /spl mu/m thick and have feature sizes as small as 0.6 /spl mu/m. The distance between the addressing electrodes and the mirror membranes is 0.8 /spl mu/m. Torsional micromirror arrays are used as spatial light modulators, and have potential applications in projection display systems, pattern generators for maskless lithography systems, optical spectroscopy, and optical communication systems. In principle, the membrane transfer bonding technique can be applied for integration of CMOS circuits with any type of transducer that consists of membranes and that benefits from the use of high temperature annealed or monocrystalline materials. These types of devices include thermal infrared detectors, RF-MEMS devices, tuneable vertical cavity surface emitting lasers (VCSEL) and other optical transducers.     

A polymer-based spiky microelectrode array for electrocorticography

The advanced technology of microelectromechanical systems (MEMS) makes possible precise and reproducible construction of various microelectrode arrays (MEAs) with patterns of high spatial density. Polymer-based MEMS devices are gaining increasing attention in the field of electrophysiology, since they can be used to form flexible, yet reliable electrical interfaces with the central and the peripheral nervous system. In this paper we present a novel MEA, designed for obtaining neural signals, with a polyimide (PI)—platinum (Pt)—SU-8 layer structure. Electrodes with special, arrow-like shapes were formed in a single row, enabling slight penetration into the tissue. The applied process flow allowed reproducible batch fabrication of the devices with high yield. In vitro characterization of the electrode arrays was performed with electrochemical impedance spectroscopy in lactated Ringer’s solution. Functional tests were carried out by performing acute recordings on rat neocortex. The devices have proven to be convenient tools for acute in vivo electrocorticography.     

Atomic layer deposition enabled interconnect technology for vertical nanowire arrays

We have demonstrated an atomic layer deposition (ALD) enabled interconnect technology for vertical, c-axis oriented gallium nitride (GaN) nanowire (NW, 5–10 μm in length, 80–200 nm in diameter) arrays encapsulated by benzocyclobutene (BCB). The nano-scaled ALD multilayer is essential to provide conformal co-axial dielectric (ALD-alumina)/conductor (ALD-tungsten) coverage and precise thickness control for nanowire metallization. Furthermore, we have successfully developed a fabrication process to locally remove and connect tungsten (W) interconnect on NWs. Cross-sectional image taken in a focused ion beam (FIB) tool confirms the conformality of ALD interconnects. Photoluminescence (PL) wavelengths of the nanowires array can be tuned dynamically by changing the input current supplied to ALD-tungsten interconnect which heats nanowires. Such an experiment also demonstrated the quality of interconnect. This interconnect technology can be applied to various vertical nanowire-based devices, such as nanowire light emitting diodes, nanowire-based field effect transistors, resonators, batteries or biomedical applications.     

Fabrication of multilayer systems combining microfluidic andmicrooptical elements for fluorescence detection

This paper presents the fabrication of a microchemical chip for the detection of fluorescence species in microfluidics. The microfluidic network is wet-etched in a Borofloat 33 (Pyrex) glass wafer and sealed by means of a second wafer. Unlike other similar chemical systems, the detection system is realized with the help of microfabrication techniques and directly deposited on both sides of the microchemical chip. The detection system is composed of the combination of refractive microlens arrays and chromium aperture arrays. The microfluidic channels are 60 μm wide and 25 μm deep. The utilization of elliptical microlens arrays to reduce aberration effects and the integration of an intermediate (between the two bonded wafers) aluminum aperture array are also presented. The elliptical microlenses have a major axis of 400 μm and a minor axis of 350 μm. The circular microlens diameters range from 280 to 300 μm. The apertures deposited on the outer chip surfaces are etched in a 3000-Å-thick chromium layer, whereas the intermediate aperture layer is etched in a 1000-Å-thick aluminum layer. The overall thickness of this microchemical system is less than 1.6 mm. The wet-etching process and new bonding procedures are discussed. Moreover, we present the successful detection of a 10-nM Cy5 solution with a signal-to-noise ratio (SNR) of 21 dB by means of this system     

High frequency integrated feed for front end circuitry and antenna arrays

Low‐cost printed circuit board waveguide (PCBWG) technology is employed to develop new waveguide‐fed microstrip antenna arrays with low profile and light weight while maintaining high efficiency and gain at 12.5 GHz. The proposed corporate feed network has two parts: on the antenna layer, microstrip lines are used to form a 2 × 4 sequentially rotated sub‐array of circularly polarized microstrip patches and on the feed layer PCB‐WG is utilized to combine any number of these sub‐arrays to form a larger array. Because PCB‐WGs transmit the power over a large portion of the feed network, losses are substantially reduced and spurious radiations from feed circuit are eliminated. Several microstrip arrays with PCBWG feed were designed and fabricated using standard PCB process. Comparing the results with those of a hybrid array with conventional waveguide feed shows that there is only a negligible degradation in gain and efficiency when bulky and expensive aluminum waveguides are replaced by PCB‐WGs. © 2008 Wiley Periodicals, Inc. Int J RF and Microwave CAE, 2009.     

Fabrication of vapor-deposited micro heat pipe arrays as anintegral part of semiconductor devices

Vapor-deposited micro heat pipe arrays (VDMHP) were fabricated as an integral part of semiconductor devices to act as efficient heat spreaders by reducing the thermal path between the heat sources and heat sink. Fabrication of the VDMHP was accomplished by first establishing a series of grooves in a silicon wafer. Orientation dependent etching (ODE) using a KOH-1-propanol-H₂O solution on a (100) wafer with a (111) flat covered with an oxide mask, resulted in grooves 25 μm wide and 25 μm deep with sharp, perpendicular edges. The wafers were predeposited with a layer of chromium followed by a layer of gold to improve the adhesion characteristics. Dual electron beam vapor deposition, followed by planetary process using molybdenum crucibles, were used to deposit copper 31.5-33.0 μm thick, and provide complete closure of the grooves. A glass cover slip was bonded on the top of the deposited layer. The grooves were finally charged and sealed. A computer model Simulation and Modeling of Evaporated Deposition Profiles (SAMPLE) was used to optimize the metal step coverage and successfully predict the cross-sectional profile of the VDMHP     

Surface modification with self-assembled monolayers for nanoscalereplication of photoplastic MEMS

A release technique that enables to lift microfabricated structures mechanically off the surface without using wet chemistry is presented. A self-assembled monolayer of dodecyl-trichlorosilane forms a very uniform ~1.5-nm-thick anti-adhesion coating on the silicon dioxide surface, on full wafer scale. The structural layers are formed directly onto the organic layer. They consist here of a 100-nm-thick aluminum film and a high-aspect ratio photoplastic SU-8 structure. After the microfabrication the structure can be lifted off the surface together with the aluminum layer. This generic technique was used to make a variety of novel structures. First, aluminum electrodes that are embedded in plastic are made using lithography, etching and surface transfer techniques. Second, using a patterned monolayer as defined by microcontact printing, resulted in a spatial variation of the surface adhesion forces. This was used to directly transfer the stamped pattern into a metal structure without using additional transfer etching steps. Third, the monolayer's ability to cover surface features down to nanometer scale was exploited to replicate sharp surface molds into metal coated photoplastic tips with ~30-nm radii for use in scanning probe instruments such as near-field optical techniques. The advantage compared to standard sacrificial layer techniques is the ability of replication at the nanoscale and the absence of etchants or solvents in the final process steps     

High-throughput thermodynamic screening of carbide/refractory metal cermets for ultra-high temperature applications

Carbide/refractory metal cermets possess attractive combinations of thermal and mechanical properties for ultra-high temperature structural applications. Using a high-throughput computational thermodynamic approach, 16 carbide/refractory metal cermet systems were identified, out of 1808 possible combinations, that could be fabricated by the displacive compensation of porosity (DCP) method using molten copper alloys as infiltrators at 1300 °C. Experimental results for ZrC/W and ZrC/Mo, and other proposed systems in the literature provide a level of validation to this approach. We found that copper alloys are more suitable for DCP than aluminum alloys owing to the low melting temperature of copper alloys (e.g., Zr₂Cu and Ti₂Cu), and the minimal chemical reaction as well as very limited mutual solid solubility of copper with refractory metals. Our results show that high-throughput thermodynamics calculation is a robust approach for systematically and thoroughly identifying refractory metal cermets that are suitable for DCP.     

基于正交试验的光纤传感器金属化连接工艺优化

为了克服光纤传感器有机胶封装带来的可靠性差、应变传递效率低的问题,采用粒子扩散系统对光纤传感器进行金属化连接以实现光纤传感器的无胶封装;为提高金属粘接层与基体的结合强度,设计了以工作距离、驱动电压、进给速度、粒子场气压为试验素的4水平正交试验方案,并用划痕法对金属粘接层的结合强度结果进行评估。通过统计分析,获得了影响金属粘接层与基体结合强度的主要因素和次要因素,优化了光纤传感器金属化连接工艺。     

碳化硅肖特基器件多层金属化技术研究

碳化硅作为近年来迅速发展起来的一种宽禁带半导体材料,具有宽禁带、高击穿电场、高载流子饱和漂移速率、高热导率、高功率密度等优点,是制备大功率、高温、高频器件的理想材料.欧姆接触的实现是碳化硅器件制造工艺的关键.为保证欧姆接触的低接触电阻和高稳定性,基于对碳化硅材料金属化技术的理论分析,进行大量工艺实验,调整工艺参数,并进...     

Formation of metal nanostructures by high-temperature imprinting

Metal nanostructures are used as wire grids for liquid crystal displays and lighting-receiving surface electrodes of solar cells. They are also integrated in emerging devices for chemical and biomedical detection and analyses carried out under various research and development programs. Currently, the mainstream fabrication method of metal nanostructures needs many manufacturing processes including patterning and metallization technologies. Here, our high-temperature nanoimprint technology for glass materials was applied to metals, which led to the development of technology to transfer nanopatterns onto a metal foil using a quartz mold. Although the glass transition temperature does not exist in metal but plastic deformation of metal is possible if the metal is made to re-crystallize at a high-temperature, but kept below its melting point. In our experiment, Al, Ag, and Cu foils of 100 μm thickness were bonded on a glass substrate of 1 mm thickness using an intermediation layer of the same metal. After that, a heated quartz mold was pressed against each metal foil, and nano-patterning was carried out. Within the limits of the specifications of a used thermal nanoimprint system, the optimal imprint temperature for Al, Ag, and Cu foils was 500, 600, and 650 °C respectively. For all metals the imprint pressure and holding time were set as 20 MPa and 1 h. As a result of trial experiments, on the three kinds of metal foils we succeeded in forming line/space with a minimum linewidth of 350 nm; and concave and convex square dotted patterns with a minimum width of 500 nm. This technique required imprint pressure less than used in conventional direct-nanoimprinting at the room temperature. With this technique of nanofabrication, molds with a low mechanical strength could be used.     

Mechanical and electrical bonding between silicon wafer and glass wafer with etched channels containing metal tracks

In this paper a novel process to bond and, at the same time, to electrically connect a silicon wafer to a glass wafer is presented. It consists of a low temperature anodic bonding process between silicon and glass by using a glass wafer with etched channels in order to contain metal tracks. The glass-to-silicon anodic bonding process at low temperatures (not exceeding 300°C) assures a strong mechanical link (Berthold et al. in Transducers 1999, June:7–10, 1999). The electrical contacts between the metal pads on the backside of a silicon wafer and the metal pads on the glass wafer are achieved by sintering and diffusion of metals due to a kind of thermo compression bonding. This bonding method permits a high vertical control due to a well-controlled etching of the cavity depth and to the thickness precision of both metallization (pads on silicon wafers and metal tracks on glass wafer). This IC-processing compatible approach opens up the way to a new electrical connection concept keeping, at the same time, a strong mechanical bond between glass and silicon wafers for an easier fabrication of a more complex micro-system.