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为减小逆变器功率器件的开关损耗,提高装置输出效率,应该控制逆变器的工作频率实时跟踪负载谐振频率,确保开关器件工作在零电流开关(ZCS)状态。介绍了高频逆变电源中采用TMS320F2812实现频率跟踪的数字锁相环(DPLL)方法,给出了实现DPLL的算法,并对采用DPLL的高频逆变电源系统进行了Simulink仿真,仿真结果表明逆变器的工作频率能实时跟踪负载谐振频率,验证了ZCS软开关工作模式。 相似文献
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本文提出了一种原子钟驾驭算法,方法是使用等价于Kalman滤波器加延迟器的数字锁相环(DPLL)。本文完整地推导了DPLL的闭环系统传递函数和闭环误差传递函数,给出了其实现结构,和每次的对于被驾驭原子钟的调整量,并给出了使DPLL输出信号的频率稳定度最优的参数选取方法。在此基础上,提出了使用两个这样的DPLL级联起来的二级驾驭算法。理论分析和仿真实验都表明:该算法相比传统原子钟驾驭算法,参数选取更容易,可以保证输出信号的频率稳定度最优;并保证输出信号与第一级的参考输入保持时间同步。该两级驾驭算法可以应用于设计锁相振荡器,即先用铯钟驾驭氢钟,然后再驾驭数控振荡器(NCO);也可以应用于建立 GNSS 时间基准,即先用 UTC (BSNC)驾驭产生BDT,然后再用BDT驾驭主控站主钟来产生BDT(MC)。 相似文献
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针对下变频后含有残余载波的周期长码直扩信号PN(Pseudo-Noise)码盲估计难题,在已知码片速率和PN码周期前提下,该文提出一种结合矩阵特征值分解和数字锁相环(Digital Phase Locked Loop, DPLL)的PN码盲估计方法。该方法首先将带有残余载波的周期长码直扩信号等效建模为虚拟多用户短码直扩信号模型,利用矩阵特征值分解和模糊酉矩阵的方法估计出含有残余载波的PN码,然后利用DPLL对残余载波的频率和相位进行跟踪和估计并最终消除残余载波,最后根据特定约束条件(如m序列、Gold序列)去除分段相位模糊,最终估计出PN码序列。理论分析和仿真结果表明,提出的方法能够有效地工作在较低信噪比下,且表现出良好的性能。 相似文献
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PCM/FM遥测系统中用于去除多谱勒频率和载波频偏的新方法 总被引:1,自引:0,他引:1
本文首先分析了均匀采样二阶DPLL(Digital Phase-Locked Loop)误差传递函数的特性,并基于均匀采样二阶DPLL误差传递函数的高通特性提出了脉冲编码调制/调频(PCM/FM)遥测系统中用于去除多谱勒频率和载波频偏的新方法;然后给出了设计实例和相应的计算机仿真结果;最后给出了有效的实现方法。计算机仿真结果表明,基于均匀采样二阶DPLL误差传递函数的高通特性用于去除多谱勒频率和载波频偏的方法是可行的。 相似文献
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本文利用高速高精度数据采集、数字下变频DDC(Digital Downconversion)CORDIC(Coordinate RotationDigital Computer)数字鉴相、一阶差分鉴频和均匀采样二阶数字锁相环DPLL(Digital Phage—Locked Loop)去除多谱勒频率和载波频偏等技术完成了2MHz码速率10.7MHz中频频率的PCM/FM遥测中频数字化接收机设计,并给出了实现系统接收线性动态范围和不同输入信噪比条件输出信号波形的测试结果。测试结果表明,设计系统的接收线性动态范围可达50dB以上,而在输入信噪比≤7dB的情况下设计系统还可以正常工作。 相似文献
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提出了一种新的适用于突发摸式的QPSK全数字快速同步方案,该方案采用DPLL结构实现。重点介绍了载波恢复和位时钟恢复环路的原理和算法,并进行了仿真。仿真结果证实了算法的可行性,同前馈估计的方案相比,由于算法简单,因而更易于硬件实现。 相似文献
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具有锁频/锁频-锁相两种工作模式的CMOS数字锁相环 总被引:1,自引:1,他引:0
提出了一种新型的数字锁相环(DPLL),它具有锁频(FL)和锁频-锁相(FPL)两种工作模式,在FL和FPL两种工作模式下分别可以获得较低的频率抖动和相位噪声。并采用自校准技术,具有快速锁定,低抖动,工作频率范围宽的优点。 相似文献
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采用基于DSP的数字锁相环(DPLL)对高频逆变电源输出频率的实时控制,可实现逆变器工作频率对负载谐振频率的同步跟踪,确保逆变器开关器件工作在零电压电流软开关(ZVZCS)状态,显著减小功率器件的开关损耗和提高装置效率。文中在给出DSP控制的逆变电源拓扑结构基础上,推出了适用于高频逆变电源的锁相环数学模型,在Z域中对二阶数字锁相环进行了稳定性分析和动态设计。在对锁相环Z域传递函数分析的基础上,得出二阶数字锁相环的稳定条件,并给出数字锁相环的软件实现,最后进行了实验验证。实验结果表明在Z域中对基于DSP的二阶数字锁相环的动态分析和设计是合理可行的。用此方法设计的电源具有良好的动态响应和抗扰性能。 相似文献
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Quantization and sampling effects on the digital phasedlocked loop (DPLL) structures obtained for demodulation of anglemodulated signals using extended Kalman filter algorithms are investigated for the high signal-to-noise ratio (SNR) case in this paper. First, the problem of quantization is considered. The validity of the uniform white sequence model for quantizer error in the DPLL is established independent of the sampling rate. Simulation results are presented for several quantizer word lengths. Also, an effective SNR is defined which allows prediction of quantized performance from unquantized results. Secondly, minimum sampling requirements for the DPLL are considered. The effect of sampling rate variation upon the predicted phase error covariance is examined. Again, simulation results are presented and compared to the predicted phase error covariance values. This results in an analytical method for determining minimum sampling rates for the DPLL. Minimum sampling rates for quantized DPLL have also been determined using the effective SNR previously defined. 相似文献
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An approach to the analysis of performance of quasioptimum digital phase-locked loops (DPLL's) is presented. An expression for the characteristic function of the prior error in the state estimate is derived, and from this expression an infinite dimensional equation for the prior error variance is obtained. The prior errorvariance equation is a function of the communication system model and the DPLL gain and is independent of the method used to derive the DPLL gain. Two approximations are discussed for reducing the prior error-variance equation to finite dimension. The effectiveness of one approximation in analyzing DPLL performance is studied. 相似文献
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Chak Chie 《Communications, IEEE Transactions on》1978,26(6):860-865
This concise paper provides an exact analysis of the phase error statistics of a first-order digital phase-locked loop (DPLL) by soloing the chapman-Kolmogorov equation using the method of moments. Both time independent and time dependent solutions are presented. In addition, the parameters which characterize the performance of a DPLL are identified with those of an analog phase-locked loop (APLL). It is Shown under what design parameter conditions the solution provided herein for a DPLL is equivalent to that obtained by applying the Fokker-Planck equation to the analysis of an APLL. Numerical comparisons are provided for specific parameter ranges of interest in practice. 相似文献
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A second-order DPLL with time-varying loop gains is applied to the symbol synchronization of burst mode data signals. An algorithm to control the DPLL loop gains is derived from adaptive Kalman filtering theory. Simulation results for the variable gain DPLL compared to a fixed gain DPLL demonstrate the improved acquisition performance 相似文献
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Byungjin Chun Yong Hoon Lee Beomsup Kim 《Communications, IEEE Transactions on》1997,45(12):1520-1522
An approach to the derivation of variable loop gain sequences of dual-loop digital phase-locked loop (DPLL) is developed based on some modifications of the Kalman filtering formulation. It is shown that optimal loop gain sequences which are independent of measurement noise statistics can be obtained under a deterministic source model. Computer simulation results demonstrate that the adaptive dual-loop DPLL designed by using the proposed method is more robust to noise variations than the adaptive DPLL of Driessen (see ibid., vol.47, p.673-75, 1994) 相似文献
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Shi Hao Yan Puqiang 《Communications, IEEE Transactions on》1991,39(3):365-368
A digital phase-locked loop (DPLL) consisting of a modified 9-gate phase detector, a frequency multiplier, and a loop filter is described. All the components are implemented in digital hardware. The Z -transform is employed to deduce the system function, and some simple properties of the DPLL are inferred by examining the mathematical model. The advantages of the proposed DPLL are: high lock-in speed, no steady-state frequency tracking error even for period ramp input signals; and ease of integration into a single chip. The use of the DPLL to realize the pitch synchronous analysis of voiced speech is reported 相似文献