Nanoelectronics from the bottom up

Electronics obtained through the bottom-up approach of molecular-level control of material composition and structure may lead to devices and fabrication strategies not possible with top-down methods. This review presents a brief summary of bottom-up and hybrid bottom-up/top-down strategies for nanoelectronics with an emphasis on memories based on the crossbar motif. First, we will discuss representative electromechanical and resistance-change memory devices based on carbon nanotube and core-shell nanowire structures, respectively. These device structures show robust switching, promising performance metrics and the potential for terabit-scale density. Second, we will review architectures being developed for circuit-level integration, hybrid crossbar/CMOS circuits and array-based systems, including experimental demonstrations of key concepts such lithography-independent, chemically coded stochastic demultipluxers. Finally, bottom-up fabrication approaches, including the opportunity for assembly of three-dimensional, vertically integrated multifunctional circuits, will be critically discussed.     

A complete fabrication route for atomic-scale, donor-based devices in single-crystal germanium

Despite the rapidly growing interest in Ge for ultrascaled classical transistors and innovative quantum devices, the field of Ge nanoelectronics is still in its infancy. One major hurdle has been electron confinement since fast dopant diffusion occurs when traditional Si CMOS fabrication processes are applied to Ge. We demonstrate a complete fabrication route for atomic-scale, donor-based devices in single-crystal Ge using a combination of scanning tunneling microscope lithography and high-quality crystal growth. The cornerstone of this fabrication process is an innovative lithographic procedure based on direct laser patterning of the semiconductor surface, allowing the gap between atomic-scale STM-patterned structures and the outside world to be bridged. Using this fabrication process, we show electron confinement in a 5 nm wide phosphorus-doped nanowire in single-crystal Ge. At cryogenic temperatures, Ohmic behavior is observed and a low planar resistivity of 8.3 kΩ/□ is measured.     

Digital memory device based on tobacco mosaic virus conjugated with nanoparticles

Nanostructured viruses are attractive for use as templates for ordering quantum dots to make self-assembled building blocks for next-generation electronic devices. So far, only a few types of electronic devices have been fabricated from biomolecules due to the lack of charge transport through biomolecular junctions. Here, we show a novel electronic memory effect by incorporating platinum nanoparticles into tobacco mosaic virus. The memory effect is based on conductance switching, which leads to the occurrence of bistable states with an on/off ratio larger than three orders of magnitude. The mechanism of this process is attributed to charge trapping in the nanoparticles for data storage and a tunnelling process in the high conductance state. Such hybrid bio-inorganic nanostructures show promise for applications in future nanoelectronics.     

Crossbar demultiplexers for nanoelectronics based on n-hot codes

Demultiplexers are expected to be key components in interfacing submicrometer-scale and nano-scale electronic circuits. Designing them is challenging because most nanoarchitectures are limited to simple regular structures, such as crossbars, and nanoelectronic circuits in general are likely to be plagued with relatively high hard-defect and soft-error rates. Previous work has shown how linear codes can be used to design defect-tolerant demultiplexers using resistor or diode crossbars. We extend those results with nonlinear codes, constructing resistor and diode crossbar-based demultiplexers that have better electrical characteristics and defect tolerance for a given area of the nano substrate, at the cost of more complex address encoding circuitry.     

Reconfigurable Hybrid CMOS/Nanodevice Circuits for Image Processing

We have analyzed two options of using hybrid CMOS/nanodevice circuits with area-distributed (CMOL) interface for the low-level image processing tasks, on the simplest example of 2-D image convolution with a sizable filter window. The first option is to use digital, DSP-like circuits based on a reconfigurable CMOL fabric, while the second one is based on mixed-signal CMOL circuits with the analog presentation of input and output data and the binary presentation of the filter function. Estimates of the circuit performance have been carried out for the 45-nm CMOS technology and the 4.5-nm nanowire half-pitch, and the power consumption fixed at a manageable, ITRS-specified level. In the digital case, the circuit area per pixel is about 25times25 , and the time necessary for convolving a 10²⁴times10²⁴-pixel, 12-bit-accurate image with a 3232-pixel window function of similar accuracy is close to 25 , much shorter than that estimated for purely CMOS circuits with the same minimum feature size on 45 nm. For a mixed-signal CMOL circuit, the corresponding numbers are much better ( ~1 mum² and 1mus, respectively), but this option requires a very high (~1%) reproducibility of on currents of the necessary crosspoint devices (programmable diodes), which has not yet been reached experimentally.     

SOI single-electron transistor with low RC delay for logic cells and SET/FET hybrid ICs

We report on a successful fabrication of silicon-based single-electron transistors (SETs) with low RC time constant and their applications to complementary logic cells and SET/field-effect transistor (FET) hybrid integrated circuit. The SETs were fabricated on a silicon-on-insulator (SOI) structure by a pattern-dependent oxidation (PADOX) technique, combined with e-beam lithography. Drain conductances measured at 4.2 K approach large values of the order of microsiemens, exhibiting Coulomb oscillations with peak-to-valley current ratios /spl Gt/1000. Data analysis with a probable mechanism of PADOX yields their intrinsic speeds of /spl sim/ 2 THz, which is within an order of magnitude of the theoretical quantum limit. Incorporating these SETs as basic elements, in-plane side gate-controlled complementary logic cells and SET/FET hybrid integrated circuits were fabricated on an SOI chip. Such an in-plane structure is very efficient in the Si fabrication process, and the side gates adjacent to the electron island could easily control the phase of Coulomb oscillations. The input-output voltage transfer, characteristic of the logic cell, shows an inverting behavior where the output voltage gain is estimated to be about 1.2 at 4.2 K. The SET/FET hybrid integrated circuit consisting of one SET and three FETs yields a high-voltage gain and power amplification with a wide-range output window for driving the next circuit. The small SET input gate voltage of 30 mV is finally converted to 400 mV, corresponding to an amplification ratio of 13.     

CMOS/nano co-design for crossbar-based molecular electronic systems

Future electronic systems will need to adopt novel nanoelectronic solutions to keep pace with Moore's Law. Crossbar-based molecular electronics are among the most promising of nanotechnologies. However, circuits similar to the conventional mainstream electronics of today will have a presence in future complex systems for some time. This paper presents a circuit paradigm where silicon and molecular electronics are integrated. We discuss methods for realizing memory and logic using nanoscale crossbars as well as for interfacing the crossbars to CMOS circuitry. Using custom nanoscale device models, we perform circuit simulation and analysis of the crossbar circuits and the peripheral CMOS circuitry. Finally, we present a design methodology to accompany the CMOS/nano paradigm.     

Defect-tolerant architectures for nanoelectronic crossbar memories

We have calculated the maximum useful bit density that may be achieved by the synergy of bad bit exclusion and advanced (BCH) error correcting codes in prospective crossbar nanoelectronic memories, as a function of defective memory cell fraction. While our calculations are based on a particular ("CMOL") memory topology, with naturally segmented nanowires and an area-distributed nano/CMOS interface, for realistic parameters our results are also applicable to "global" crossbar memories with peripheral interfaces. The results indicate that the crossbar memories with a nano/CMOS pitch ratio close to 1/3 (which is typical for the current, initial stage of the nanoelectronics development) may overcome purely semiconductor memories in useful bit density if the fraction of nanodevice defects (stuck-on-faults) is below approximately 15%, even under rather tough, 30 ns upper bound on the total access time. Moreover, as the technology matures, and the pitch ratio approaches an order of magnitude, the crossbar memories may be far superior to the densest semiconductor memories by providing, e.g., a 1 Tbit/cm2 density even for a plausible defect fraction of 2%. These highly encouraging results are much better than those reported in literature earlier, including our own early work, mostly due to more advanced error correcting codes.     

Run-Time Data-Dependent Defect Tolerance for Hybrid CMOS/Nanodevice Digital Memories

This paper presents a data-dependent defect tolerance design approach to improve the storage capacity of defect-prone hybrid CMOS/nanodevice digital memories. The basic idea is to reduce the memory redundancy overhead by exploiting the run-time matching between the data and memory defects. A conditional bit-flipping technique is used to enable the practical realization of this design approach in presence of the conflict between the dynamic nature of run-time data-defect matching and static nature of memory system design. Computer simulations show that the proposed method can achieve much higher storage capacity compared with conventional data-independent defect tolerance at small memory operation overhead.     

A large-area nanoscale gold hemisphere pattern as a nanoelectrode array

Two-dimensional (2D) nanostructure patterns have extensive applications in photonic devices, nanoelectronics, electrochemical devices, biosensors, catalysts and high-density magnetic recording devices. It remains a challenge to develop low-cost, high-throughput, high-resolution techniques for the fabrication of large-area (wafer-scale) 2D nanostructure array patterns with controlled feature size, shape and pitch. The present work has demonstrated a low-cost, high-throughput, high-resolution approach for the fabrication of large-area, high-quality nanostructure array patterns by nanosphere lithography combined with electroplating. The gold hemisphere array pattern obtained is capable of functioning as a nanoelectrode array (NEA) in which the gold hemispheres act as individual electrodes that are separated with an insulating polypyrrole (PPY) film. Cyclic voltammetry measurement has shown a sigmoid-shaped voltammogram, which is characteristic of electrochemical characteristics of a nanoelectrode array. NEAs are expected to find extensive applications in fundamental electrochemistry studies and electrochemical devices.     

High yield assembly and electron transport investigation of semiconducting-rich local-gated single-walled carbon nanotube field effect transistors

We report the fabrication and electron transport investigation of individual local-gated single-walled carbon nanotube field effect transistors (SWNT-FET) with high yield using a semiconducting-rich carbon nanotube solution. The individual semiconducting nanotubes were assembled at the selected position of the circuit via dielectrophoresis. Detailed electron transport investigations on 70 devices show that 99% display good FET behavior, with an average threshold voltage of 1 V, subthreshold swing as low as 140 mV/dec, and on/off current ratio as high as 8 × 10(5). The high yield directed assembly of local-gated SWNT-FET will facilitate large scale fabrication of CMOS (complementary metal-oxide-semiconductor) compatible nanoelectronic devices.     

Transformable functional nanoscale building blocks with wafer-scale silicon nanowires

Through the fusion of electrostatics and mechanical dynamics, we demonstrate a transformable silicon nanowire (SiNW) field effect transistor (FET) through a wafer-scale top-down approach. By felicitously taking advantage of the proposed electrostatic SiNW-FET with mechanically movable SiNWs, all essential logic gates, including address decoders, can be monolithically integrated into a single device. The unification of various functional devices, such as pn-diodes, FETs, logic gates, and address decoders, can therefore eliminate the complex fabrication issues associated with nanoscale integration. These results represent a step toward the creation of multifunctional and flexible nanoelectronics.     

Hybrid silicon/molecular FETs: a study of the interaction of redox-active molecules with silicon MOSFETs

Redox-active molecular monolayers were incorporated in silicon MOSFETs to obtain hybrid silicon/molecular FETs. Cyclic voltammetry and FET characterization techniques were used to study the properties of these hybrid devices. The redox-active molecules have tunable charge states, which are quantized at room temperature and can be accessed at relatively low voltages. The discrete molecular states were manifested in the drain current and threshold voltage characteristics of the device, confirming the presence of distinct energy levels within the molecules at room temperature. This study demonstrates the modulation of Si-MOSFETs' drain currents via redox-active molecular monolayers. The single-electron functionality provided by the redox-active molecules is ultimately scalable to molecular dimensions, and this approach can be extended to nanoscale field-effect devices including those based on carbon nanotubes. The molecular states coupled with CMOS devices can be utilized for low-voltage, multiple-state memory and logic applications and can extend the impact of silicon-based technologies.     

Magnetic‐Induced‐Piezopotential Gated MoS2 Field‐Effect Transistor at Room Temperature

Utilizing magnetic field directly modulating/turning the charge carrier transport behavior of field‐effect transistor (FET) at ambient conditions is an enormous challenge in the field of micro–nanoelectronics. Here, a new type of magnetic‐induced‐piezopotential gated field‐effect‐transistor (MIPG‐FET) base on laminate composites is proposed, which consists of Terfenol‐D, a ferroelectric single crystal (PMNPT), and MoS₂ flake. When applying an external magnetic field to the MIPG‐FET, the piezopotential of PMNPT triggered by magnetostriction of the Terfenol‐D can serve as the gate voltage to effectively modulate/control the carrier transport process and the corresponding drain current at room temperature. Considering the two polarization states of PMNPT, the drain current is diminished from 9.56 to 2.9 µA in the P_up state under a magnetic field of 33 mT, and increases from 1.41 to 4.93 µA in the P_down state under a magnetic field of 42 mT and at a drain voltage of 3 V. The current on/off ratios in these states are 330% and 432%, respectively. This work provides a novel noncontact coupling method among magnetism, piezoelectricity, and semiconductor properties, which may have extremely important applications in magnetic sensors, memory and logic devices, micro‐electromechanical systems, and human–machine interfacing.     

Defect and Transient Fault-Tolerant System Design for Hybrid CMOS/Nanodevice Digital Memories

Targeting on the future fault-prone hybrid CMOS/nanodevice digital memories, this paper presents two fault-tolerance design approaches that integrally address the tolerance for defects and transient faults. These two approaches share several key features, including the use of a group of Bose-Chaudhuri-Hocquenghem (BCH) codes for both defect tolerance and transient fault tolerance, and integration of BCH code selection and dynamic logical-to-physical address mapping. The first approach is straightforward and easy to implement but suffers from a rapid drop of achievable storage capacity as defect densities and/or transient fault rates increase, while the second approach can achieve much higher storage capacity under high defect densities and/or transient fault rates at the cost of higher implementation complexity and longer memory access latency. Based on extensive computer simulations and BCH decoder circuit design, we have demonstrated the effectiveness of the presented approaches under a wide range of defect densities and transient fault rates, while taking into account of the fault-tolerance storage overhead and BCH decoder implementation cost in CMOS domain     

A general approach for high yield fabrication of CMOS-compatible all-semiconducting carbon nanotube field effect transistors

We report strategies to achieve both high assembly yield of carbon nanotubes at selected positions of the circuit via dielectrophoresis (DEP) and field effect transistor (FET) yield using an aqueous solution of semiconducting-enriched single-walled carbon nanotubes (s-SWNTs). When the DEP parameters were optimized for the assembly of individual s-SWNTs, 97% of the devices showed FET behavior with a maximum mobility of 210 cm2 V(-1) s(-1), on-off current ratio ～10(6) and on-conductance up to 3 μS, but with an assembly yield of only 33%. As the DEP parameters were optimized so that one to five s-SWNTs are connected per electrode pair, the assembly yield was almost 90%, with ～90% of these assembled devices demonstrating FET behavior. Further optimization gave an assembly yield of 100% with up to 10 SWNTs per site, but with a reduced FET yield of 59%. Improved FET performance including higher current on-off ratio and high switching speed were obtained by integrating a local Al2O3 gate to the device. Our 90% FET with 90% assembly yield is the highest reported so far for carbon nanotube devices. Our study provides a pathway which could become a general approach for the high yield fabrication of complementary metal oxide semiconductor (CMOS)-compatible carbon nanotube FETs.     

COMMENT Practical voltage/current-controlled groundedresistor with dynamic range extension

Recently, Maundy, Gift and Aronhime presented a voltage/current-controlled grounded resistor which makes use of bisection of the drain-to-source voltage of a FET to produce a linear resistor with wide dynamic range extension. The purpose of this communication is to bring on record, in the context of the above paper, our works on the same topic published more than a decade back which are closely related to the work reported in the above-mentioned paper but have not been cited therein.     

Programmable Negative Differential Resistance Effects Based on Self‐Assembled Au@PPy Core–Shell Nanoparticle Arrays

The negative differential resistance (NDR) effect observed in conducting polymer/Au nanoparticle composite devices is not yet fully clarified due to the random and disordered incorporation of Au nanoparticles into conducting polymers. It remains a formidable challenge to achieve the sequential arrangement of various components in an optimal manner during the fabrication of Au nanoparticle/conducting polymer composite devices. Here, a novel strategy for fabricating Au nanoparticle/conducting polymer composite devices based on self‐assembled Au@PPy core–shell nanoparticle arrays is demonstrated. The interval between the two Au nanoparticles can be precisely programmed by modulating the thickness of the shell and the size of the core. Programmable NDR is achieved by regulating the spacer between two Au nanoparticles. In addition, the Au/conducting polymer composite device exhibits a reproducible memory effect with read–write–erase characteristics. The sequentially controllable assembly of Au@PPy core–shell nanoparticle arrays between two microelectrodes will simplify nanodevice fabrication and will provide a profound impact on the development of new approaches for Au/conducting polymer composite devices.     

Experimental demonstration of a defect-tolerant nanocrossbar demultiplexer

Ultradense memory and logic circuits fabricated at local densities exceeding 100 × 10(9) cross-points per cm(2) have recently been demonstrated with nanowire crossbar arrays. Practical implementation of such nanocrossbar circuitry, however, requires effective demultiplexing to solve the problem of electrically addressing individual nanowires within an array. Importantly, such a demultiplexer (demux) must also be tolerant of the potentially high defect rates inherent to nanoscale circuit fabrication. We have built a 50?nm half-pitch nanocrossbar circuit using imprint lithography and configured it for a demux application. Utilizing a class of Hamming codes in the hardware design, we experimentally demonstrate defect-tolerant demux operations on a 12 × 8 nanocrossbar array with up to two stuck-open defects per addressed line.     

Hybrid metal-based carbon nanotubes: Novel platform for multifunctional applications

Combining objects with diverse properties has often the advantage of giving rise to novel functionalities. In this scenario, metal-filled and decorated carbon nanotubes (m-CNTs) represent a class of hybrid carbon-based nanostructured materials with enormous interest for application in several fields, ranging from nanoelectronics and spintronics to nanomedicine and magnetic data recording. The present review will provide the reader with an overview of state-of-the-art hybrid architectures based on m-CNT systems, methods currently employed for their fabrication, the set of their unique properties and how they can be applied toward novel devices with multifunctional properties for a broad range of applications.