Leakage current degradation in n-MOSFETs due to hot-electron stress

The field-induced drain-leakage current can become significant in NMOS devices with thin gate oxides. This leakage current component is found to be more prominent in devices with gate-drain overlap and can increase considerably with hot-electron stress. A method which shows how measuring the gate voltage needed to obtain a constant leakage value of 0.1 nA can yield useful information on the interface charge trap density is discussed     

Temperature dependence of hot-electron degradation in bipolartransistors

Degradation of the base current and current gain observed in bipolar transistors that were electrically stressed at-75, 175, and 240°C for 1000 h with a constant reverse-bias voltage applied to the emitter-base junctions is discussed. The rate of degradation was found to be temperature-dependent with a larger degradation occurring at the lower temperature. This temperature dependency is studied using an electron energy simulation technique and experimental data on degradation and postdegradation annealing. From the electron energy simulations, the number of hot electrons above a damage threshold energy was seen to increase with increasing ambient temperature at a constant reverse-bias voltage. This increase with temperature occurred because higher stress currents dominated over a reduction in the electron mean free path between collisions at higher temperatures. However, an actual degradation rate reduction at higher temperatures occurs because of simultaneous annealing of the states produced by hot electrons. A model that describes the temperature dependence of degradation and postdegradation annealing is described     

Temperature dependence of gate induced drain leakage current insilicon CMOS devices

The temperature dependence of the gate induced drain leakage (GIDL) current in CMOS devices is investigated from 20K up to 300K. It is shown that, at sufficiently high electric field, the conventional band-to-band tunnelling GIDL current law is applicable down to near-liquid helium temperatures for both nand p-channel devices. The exponential factor B of the GIDL current law is found to be nearly independent of temperature. Moreover, the decrease of the GIDL current as the temperature is lowered, is shown to originate from the temperature variation of the pre-exponential coefficient A of the GIDL current law     

Subbreakdown drain leakage current in MOSFET

Significant drain leakage current can be detected at drain voltages much lower than the breakdown voltage. This subbreakdown leakage can dominate the drain leakage current at zero VGin thin-oxide MOSFET's. The mechanism is shown to be band-to-band tunneling in Si in the drain/gate overlap region. In order to limit the leakage current to 0.1 pA/µm, the oxide field in the gate-to-drain overlap region must be limited to 2.2 MV/cm. This may set another constraint for oxide thickness or power supply voltage.     

Gate-induced drain leakage in FD-SOI devices: What the TFET teaches us about the MOSFET

This paper compares the gate-induced drain leakage (GIDL) in fully-depleted (FD) silicon-on-insulator (SOI) tunneling field effect transistor (TFET) and in standard metal-oxide-semiconductor FET (MOSFET) fabricated in the same process. The measurements show that the MOSFET GIDL current is lower than the GIDL in a TFET with the same junction doping, especially for devices with thick gate oxide and under low drain bias. A model describing lateral band-to-band tunneling (BTBT) is developed for GIDL in the FD-SOI TFET. By combining the model of gate-controllable tunneling diode in series with a field effect diode, we achieve an accurate picture of GIDL in FD-SOI MOSFETs.     

A comprehensive study of hot carrier stress-induced drain leakagecurrent degradation in thin-oxide n-MOSFETs

The mechanisms and characteristics of hot carrier stress-induced drain leakage current degradation in thin-oxide n-MOSFETs are investigated. Both interface trap and oxide charge effects are analyzed. Various drain leakage current components at zero V_gs such as drain-to source subthreshold leakage, band-to-band tunneling current, and interface trap-induced leakage are taken into account. The trap-assisted drain leakage mechanisms include charge sequential tunneling current, thermionic-field emission current, and Shockley-Read-Hall generation current. The dependence of drain leakage current on supply voltage, temperature, and oxide thickness is characterized. Our result shows that the trap-assisted leakage may become a dominant drain leakage mechanism as supply voltage is reduced. In addition, a strong oxide thickness dependence of drain leakage degradation is observed. In ultra-thin gate oxide (30 Å) n-MOSFETs, drain leakage current degradation is attributed mostly to interface trap creation, while in thicker oxide (53 Å) devices, the drain leakage current exhibits two-stage degradation, a power law degradation rate in the initial stage due to interface trap generation, followed by an accelerated degradation rate in the second stage caused by oxide charge creation     

Modeling of drain leakage current in SOI pMOSFETs

In this paper we present a compact drain leakage current model for fully-depleted (FD) SOI pMOSFETs. The analytical and physics-based model was developed using a quasi-two dimensional approach, in which the longitudinal and vertical surface channel electric fields can be calculated. It can be used to accurately calculate drain leakage current as a function of drain and gate biases. This model in conjunction with our previous published subthreshold and above threshold model forms a concrete drain current model for FD SOI pMOSFET operation in off and on states.     

Clear correspondence between gated-diode R-G current and performance degradation of SOI n-MOSFETs after F-N stress tests

A clear correspondence between the gated-diode generation-recombination (R-G) current and the per-formance degradation of an SOI n-channel MOS transistor after F-N stress tests has been demonstrated. Due to the increase of interface traps after F-N stress tests, the R-G current of the gated-diode in the SOI-MOSFET architecture increases while the performance characteristics of the MOSFET transistor such as the saturation drain current and sub-threshold slope are degraded. From a series of experimental measurements of the gated-diode and SOI-MOSFET DC characteristics, a linear decrease of the drain saturation current and increase of the threshold volt-age as well as a like-line rise of the sub-threshold swing and a corresponding degradation in the trans-conductance are also observed. These results provide theoretical and experimental evidence for us to use the gated-diode tool to monitor SOI-MOSFET degradation.     

F-N应力下SOI n-MOSFETs性能退化与栅控二极管产生-复合（G-R）电流的对应关系

本文验证了F-N应力导致的SOI n- MOSFET器件性能退化与栅控二极管的产生-复合（G-R）电流的对应关系。F-N应力导致的界面态增加会导致SOI-MOSFET结构的栅控二极管的产生-复合（G-R）电流增大,以及MOSFET饱和漏端电流,亚阈斜率等器件特性退化。通过一系列的SOI-MOSFET栅控二极管和直流特性测试,实验观察到饱和漏端电流的线性退化和阈值电压的线性增加,亚阈摆幅的类线性上升以及相应的跨导退化。理论和实验证明栅控二极管是一种很有效的监控SOI-MOSFET退化的方法。     

Nonlocal hot-electron injection as the mechanism for the predominant source-side gate oxide degradation in CHE-stressed deep submicrometer n-MOSFETs

A possible mechanism behind the predominant source-side gate oxide degradation in channel hot-electron (CHE)-stressed deep submicrometer n-MOSFETs is presented. The role of a nonlocal hot-electron injection mechanism, arising possibly from carrier-to-carrier interaction and/or impact ionization feedback, is emphasized. The latter effect is prominently revealed through a systematic stress scheme that employs a reverse substrate bias. Oxide degradation behaviour is shown to be consistent with the anode electron-energy model. The more severe source-side oxide degradation may be attributed to nonlocally injected tertiary electrons possessing greater available energy on arrival at the anode (gate), as a result of a coupled heating process.     

The impacts of SILC and hot carrier induced drain leakage current on the refresh time in DRAM

This paper reports the temperature dependence of SILC and hot carrier induced drain leakage current, and their impact on the refresh time in Giga-bit level DRAM with practical considerations. SILC has been found to increase as the monitoring and stress temperature increases. Due to the generation of interface states, hot carrier induced pn junction leakage current and band-to-band tunneling current have been found to increase as the monitoring temperature increases.From the simulation results of a refresh circuit for Giga-bit level DRAM, it has been found that the increase of SILC with stress time is a dominant factor in refresh failure below 373K, and the pn junction leakage current will be a dominant factor at the high elevated temperature. It has been also observed that the increase of hot carrier induced drain leakage current can be a cause for the refresh failure.     

Radiation source dependence of performance degradation in thin gate oxide fully-depleted SOI n-MOSFETs

The degradation of the electrical performance of thin gate oxide fully depleted SOI n-MOSFETs and its dependence on the radiation particles are investigated. The transistors are irradiated with 7.5-MeV protons and 2-MeV electrons at room temperature without bias. The shift of threshold voltage and the coupling effect with the degraded opposite gate are clarified. A remarkable reduction of the floating body effects is observed after irradiation. The degradation of the extracted parameters is discussed by a comparison with the damage coefficients.     

On the drain current saturation in short channel MOSFETs

Submicron MOSFETs are the issue for ULSI integrated circuits. However, drastic reduction of device size leads to a complex modeling of the MOSFET drain current, which is affected by the electrical and physical phenomena induced by the low device dimension. Several current models are proposed to explain the drain current behavior in the saturation region of the I_D-V_D characteristic curve. Mainly, we can distinguish two types: long channel and short channel current modeling. In the present work, a survey of current voltage models is presented aiming a contribution to the interpretation of the current behavior in the saturation region of the I-V curves, i.e. non-saturation of the drain current, which are critical in submicronic devices.     

Stress induced gate–drain leakage current in ultra-thin gate oxide

Ultra-thin gate oxide reliability, in large area MOSFETs, can be monitored by measuring the gate current when the substrate is depleted. When the channel length is scaled down, the tunneling current associated with the source/drain extension region (SDE) to the gate–overlap regions can dominate the gate current. In N-MOSFETs, as a function of the negative gate voltage two components of the gate–drain leakage current should be considered, the first for V_FB < V_G < 0 V and the second for V_G < V_FB. These components are studied in this work before and after voltage stresses. The aim of this work is to see whether this gate–drain current can be used to monitor the oxide degradation above or near the source and/or drain extension region in N-MOSFETs. It is important because the most serious circuit-killing breakdown occurs above or near the drain (or source) extension region. Finally, we show that it is necessary, before explaining the gate LVSILC curves obtained after stresses on short-channel devices, to verify which is the dominate current at low voltage.     

The leakage current improvement in an ultrashallow junction NMOSwith Co silicided source and drain

The leakage current characteristics of the cobalt silicided NMOS transistors with a junction depth of 800 Å have been studied. In order to minimize the junction leakage current, the thickness of the CoSi₂ layer should he controlled under 300 Å and the Si surface damage induced by the gate spacer etch should be minimized. The post furnace annealing after the second silicidation by the rapid thermal annealing (RTA) process also affected the leakage current characteristics. The gate induced drain leakage (GIDL) current was not affected by the lateral encroachment of CoSi₂ layer into the channel direction when the gate spacer length was larger than 400 Å     

Comparison of channel current and drain avalanche current-induced hot-carrier effects in MOSFET's

Hot-carrier effects induced by the channel current and the drain avalanche current in short-channel MOSFET's are investigated and compared by characterizing the substrate current at different stages of stress. Not only does the drain avalanche stress (DAS) degrade devices much faster than the triode region stress (TCS) does, but the substrate current versus the stress time shows a characteristic difference between the DAS mode and the TCS mode. The difference is that the DAS mode involves localized interface trap generation near the drain and more widely distributed hole trapping in the oxide, while in the TCS mode the mechanism is mainly localized electron trapping in the oxide.     

Hole trapping during low gate bias, high drain bias hot-carrierinjection in n-MOSFETs at 77 K

Injection and trapping of holes in the gate oxide of n-channel MOS transistors during operation at large drain and small gate biases are investigated at liquid-nitrogen temperature. Experimental evidence is given that about three times less trapping of holes occurs in the gate oxide at 77 K as compared to 295 K. The authors show that this is due to the small hole mobility in SiO₂ at low temperature     

Roles of electron trapping and interface state generation ongate-induced drain leakage current in p-MOSFETs

The roles of electron trapping and of acceptor-type interface state generation (ΔD_it) in the off-state gate-induced drain leakage (GIDL) current in p-MOSFETs are studied. It is found that both trapped electrons and negatively charged acceptor-type interface states reduce the GIDL current at the high-surface-field region, in which GIDL is still governed by the band-to-band tunneling process. However, the neutral acceptor-type ΔD_it increases the GIDL current significantly at the low-surface-field region     

Junction leakage current degradation under high temperature reverse-bias stress induced by band-defect-band tunnelling in power VDMOS

A deep analysis of the intrinsic junction and surface currents in power vertically diffused MOS devices with sub-micrometer channel length and thin gate oxide has been carried on after a typical reliability high temperature reverse bias (HTRB) stress. A reference set of gated diodes has also been examined in order to better understand the onset and evolution of post-stress leakage degradation. A comparison among complete MOSs, single body diodes and enriched diodes allows to highlight the role played by the point defectivity both at gate interface and in the bulk silicon close to the junction surface. We found that the typical interface defects involved in the leakage degradation are shallow traps and can be de-populated simply by a thermally activated mechanism. More specifically, the main degradation mechanism relies to band-defect-band tunneling localized at the surface drain/body junction where an intrinsic n-i-p region evolves due to a bird’s beak lateral profile of the body diffusion. We have demonstrated that the most important contribution to the activation of the precursor defect sites is given by the transverse electrical field that develops just below the SiO₂/Si interface within the n-i-p region during the stress.