基于电感电容振荡器的电荷泵锁相环的设计

设计并实现了一种采用电感电容振荡器的电荷泵锁相环,分析了锁相环中鉴频/鉴相器(PFD)、电荷泵(CP)、环路滤波器(LP)、电感电容压控振荡器(VCO)的电路结构和设计考虑。锁相环芯片采用0.13μm MS&RF CMOS工艺制造。测试结果表明,锁相环锁定的频率为5.6～6.9 GHz。在6.25 GHz时,参考杂散为-51.57 dBc;1 MHz频偏处相位噪声为-98.35 dBc/Hz;10 MHz频偏处相位噪声为-120.3 dBc/Hz;在1.2 V/3.3 V电源电压下,锁相环的功耗为51.6 mW。芯片总面积为1.334 mm2。     

A 14-GHz 256/257 dual-modulus prescaler with secondary feedback and its application to a monolithic CMOS 10.4-GHz phase-locked loop

A 14-GHz 256/257 dual-modulus prescaler is implemented using secondary feedback in the synchronous 4/5 divider on a 0.18-/spl mu/m foundry CMOS process. The dual-modulus scheme utilizes a 4/5 synchronous counter which adopts a traditional MOS current mode logic clocked D flip-flop. The secondary feedback paths limit signal swing to achieve high-speed operation. The maximum operating frequency of the prescaler is 14 GHz at V/sub DD/=1.8 V. Utilizing the prescaler, a 10.4-GHz monolithic phase-locked loop (PLL) is demonstrated. The voltage-controlled oscillator (VCO) operates between 9.7-10.4 GHz. The tuning range of the VCO is 690 MHz. The phase noise of the PLL and VCO at a 3-MHz offset with I/sub vco/=4.9 mA is -117 and -119 dBc/Hz, respectively. At the current consumption of I/sub vco/=8.1 mA, the phase noise is -122 and -122 dBc/Hz, respectively. The PLL output phase noise at a 50-kHz offset is -80 dBc/Hz. The PLL consumes /spl sim/31 mA at V/sub DD/=1.8 V.     

A wideband 2.4-GHz delta-sigma fractional-NPLL with 1-Mb/s in-loop modulation

A phase noise cancellation technique and a charge pump linearization technique, both of which are insensitive to component errors, are presented and demonstrated as enabling components in a wideband CMOS delta-sigma fractional-N phase-locked loop (PLL). The PLL has a loop bandwidth of 460 kHz and is capable of 1-Mb/s in- loop FSK modulation at center frequencies of 2402 + k MHz for k = 0, 1, 2, ..., 78. For each frequency, measured results indicate that the peak spot phase noise reduction achieved by the phase noise cancellation technique is 16 dB or better, and the minimum suppression of fractional spurious tones achieved by the charge pump linearization technique is 8 dB or better. With both techniques enabled, the PLL achieves a worst-case phase noise of -121 dBc/Hz at 3-MHz offsets, and a worst-case in-band noise floor of -96 dBc/Hz. The PLL circuitry consumes 34.4 mA from 1.8-2.2-V supplies. The IC is realized in a 0.18-/spl mu/m mixed-signal CMOS process, and has a die size of 2.72 mm /spl times/ 2.47 mm.     

The design and analysis of a DLL-based frequency synthesizer for UWB application

A delay-locked loop (DLL)-based frequency synthesizer is designed for the ultrawideband (UWB) Mode-1 system. This frequency synthesizer with 528-MHz input reference frequency achieves less than 9.5-ns settling time by utilizing wide loop bandwidth and fast-settling architecture. Additionally, a discrete-time model of the DLL and an analytical model of phase noise of the delay line are proposed in this work. Experimental results show great consistency with predicted settling time and phase noise. The circuit has been fabricated in a 0.18-/spl mu/m CMOS technology and consumes only 54 mW from a 1.8-V supply. It exhibits a sideband magnitude of -35.4 dBc and -120-dBc/Hz phase noise at the frequency offset of 1 MHz.     

A 13.5-mW 5-GHz frequency synthesizer with dynamic-logic frequency divider

The adoption of dynamic dividers in CMOS phase-locked loops for multigigahertz applications allows to reduce the power consumption substantially without impairing the phase noise and the power supply sensitivity of the phase-locked loop (PLL). A 5-GHz frequency synthesizer integrated in a 0.25-/spl mu/m CMOS technology demonstrates a total power consumption of 13.5 mW. The frequency divider combines the conventional and the extended true-single-phase-clock logics. The oscillator employs a rail-to-rail topology in order to ensure a proper divider function. This PLL intended for wireless LAN applications can synthesize frequencies between 5.14 and 5.70 GHz in steps of 20 MHz. The reference spurs at 10-MHz offset are as low as -70 dBc and the phase noise is lower than -116 dBc/Hz at 1 MHz over the whole tuning range.     

带有自适应频率校准单元的26~41 GHz锁相环

采用45 nm SOI CMOS工艺,设计了一种带有自适应频率校准单元的26~41 GHz 锁相环。该锁相环包括输入缓冲器、鉴频鉴相器、电荷泵、环路滤波器、压控振荡器、高速时钟选通器、分频器和频率数字校准单元。采用了基于双LC-VCO的整数分频锁相环,使用了自适应频率选择的数字校准算法,使得锁相环能在不同参考时钟下自适应地调整工作频率范围。仿真结果表明,该锁相环的输出频率能够连续覆盖26~41 GHz。输出频率为26 GHz时,相位噪声为-103 dBc/Hz@10 MHz,功耗为34.64 mW。输出频率为41 GHz时,相位噪声为-96 dBc/Hz@10 MHz,功耗为35.44 mW。     

An Agile VCO Frequency Calibration Technique for a 10-GHz CMOS PLL

This paper reports an agile VCO frequency calibration technique and its application on a 10-GHz CMOS integer-N phase-locked loop. The proposed calibration method accomplishes efficient search for an optimum VCO discrete tuning curve among a group of frequency sub-bands. The agility is attributed to a proposed frequency comparison technique which is based on measuring the period difference between two signals. Other mixed-signal circuits are also developed to facilitate this approach. The PLL incorporating the proposed calibration technique is implemented in a 0.18-mum CMOS process. The measured PLL phase noise at 10 GHz is -102 dBc/Hz at 1-MHz offset frequency and the reference spurs are lower than -48 dBc. The PLL consumes 44 mW in the low-current mode. The calibration time is less than 4mus     

A Wide-Bandwidth 2.4 GHz ISM Band Fractional-N PLL With Adaptive Phase Noise Cancellation

A fast-settling adaptive calibration technique is presented that makes phase noise cancelling DeltaSigma fractional-N PLLs practical for the low reference frequencies commonly used in wireless communication systems. The technique is demonstrated as an enabling component of a 2.4 GHz ISM band CMOS PLL IC with a 730 kHz bandwidth, a 12 MHz reference, and an on-chip loop filter. In addition to the adaptive calibration technique, the IC incorporates a dynamic charge pump biasing technique to reduce power dissipation. The worst-case phase noise of the IC is -101 dBc/Hz and -124 dBc/Hz at 100 kHz and 3 MHz offsets, respectively, and the adaptive phase noise cancellation technique has a worst-case settling time of 35 mus . The IC is implemented in 0.18 CMOS technology. It measures 2.2 x 22 mm² and its core circuitry consumes 20.9 mA from a 1.8 V supply.     

A 1.5 V 7.656 GHz PLL with I/Q outputs for a UWB synthesizer

A fully integrated CMOS phase-locked loop (PLL) which can synthesize a quadrature output frequency of 7.656 GHz is presented.The proposed PLL can be employed as a building block for an MB-OFDM UWB frequency synthesizer.To achieve fast loop settling,integer-N architecture operating with 66 MHz reference frequency and wideband QVCO are implemented.I/Q carriers are generated by two bottom-series cross-coupled LC VCOs.Realized in 0.18μm CMOS technology,this PLL consumes 16 mA current (including buffers) from a 1.5 V supply and the phase noise is-109.6 dBc/Hz at 1 MHz offset.The measured oscillation frequency shows that the QVCO has a range of 6.95 to 8.73 GHz.The core circuit occupies an area of 1×0.5 mm2.     

A 20-GHz phase-locked loop for 40-gb/s serializing transmitter in 0.13-/spl mu/m CMOS

A 20-GHz phase-locked loop with 4.9 ps/sub pp//0.65 ps/sub rms/ jitter and -113.5 dBc/Hz phase noise at 10-MHz offset is presented. A half-duty sampled-feedforward loop filter that simply replaces the resistor with a switch and an inverter suppresses the reference spur down to -44.0 dBc. A design iteration procedure is outlined that minimizes the phase noise of a negative-g/sub m/ oscillator with a coupled microstrip resonator. Static frequency dividers made of pulsed latches operate faster than those made of flip-flops and achieve near 2:1 frequency range. The phase-locked loop fabricated in a 0.13-/spl mu/m CMOS operates from 17.6 to 19.4GHz and dissipates 480mW.     

A 4224 MHz low jitter phase-locked loop in 0.13-μm CMOS technology

A 4224 MHz phase-locked loop (PLL) is implemented in 0.13 μm CMOS technology. A dynamic phase frequency detector is employed to shorten the delay reset time so as to minimize the noise introduced by the charge pump. Dynamic mismatch of charge pump is considered. By balancing the switch signals of the charge pump, a good dynamic matching characteristic is achieved. A high-speed digital frequency divider with balanced input load is also designed to improve in-band phase noise performance. The 4224 MHz PLL achieves phase noises of-94 dBc/Hz and -114.4 dBc/Hz at frequency offsets of 10 kHz and 1 MHz, respectively. The integrated RMS jitter of the PLL is 0.57 ps (100 Hz to 100 MHz) and the PLL has a reference spur of-63 dB with the second order passive low pass filter.     

A quad-band GSM-GPRS transmitter with digital auto-calibration

A low-power low-voltage fully integrated fast-locking quad-band (850/900/1800/1900-MHz) GSM-GPRS transmitter is described. It exploits closed-loop phase-locked loop (PLL) upconversion using a modulated fractional-N frequency synthesizer with digital auto-calibration. It uses a type-I PLL in a mostly digital IC with no external components and achieves a lock time of 43 /spl mu/s, a tuning range of 500 MHz, receive-band phase noise of -158dBc/Hz and -165 dBc/Hz for the high and low bands, respectively, and reference feed through of -93.9 dBc. It is implemented in 2.1 mm/sup 2/ using a 0.13-/spl mu/m CMOS process and meets all quad-band GSM transmitter specifications with a current consumption of only 28 mA from a single 1.5-V power supply.     

A 17-mW transmitter and frequency synthesizer for 900-MHz GSM fully integrated in 0.35-/spl mu/m CMOS

A fractional-N phase-locked loop (PLL) serves as a Gaussian minimum-shift keying (GMSK) transmitter and a receive frequency synthesizer for GSM. The entire transmitter/synthesizer is fully integrated in 0.35-/spl mu/m CMOS and consumes 17.4 and 12 mW from 2.5 V in the transmit and receive modes, respectively, including an on-chip voltage-controlled oscillator. The circuit meets GSM specifications on modulation accuracy in transmit mode, and measured phase noise from the closed-loop PLL is -148 dBc/Hz and -162 dBc/Hz, respectively, at 3- and 20-MHz offset. Worst case spur at 13-MHz offset is -77 dBc.     

A 2.4-GHz ring-oscillator-based CMOS frequency synthesizer with a fractional divider dual-PLL architecture

A 2.4-GHz frequency synthesizer was designed that uses a fractional divider to drive a dual-phase-locked-loop (PLL) structure, with both PLLs using only on-chip ring oscillators. The first-stage narrow-band PLL acts as a spur filter while the second-stage wide-band PLL suppresses VCO phase noise so that simultaneous suppression of phase noise and spur is achieved. A new low-power, low-noise, low-frequency ring oscillator is designed for this narrow-band PLL. The chip was designed in 0.35-/spl mu/m CMOS technology and achieves a phase noise of -97 dBc/Hz at 1-MHz offset and spurs of -55 dBc. The chip's output frequency varies from 2.4 to 2.5 GHz; the chip consumes 15 mA from a 3.3-V supply and occupies 3.7 mm/spl deg/.     

A fast-locking agile frequency synthesizer for MIMO dual-mode WiFi/WiMAX applications

In this paper, a wide-range and fast-locking phase-locked loop (PLL) frequency synthesizer using the band selection technique for the agile voltage-controlled oscillator (VCO) is proposed. The minimum time for band selection, discretely tuned by a time-to-voltage converter, can reach four times of the reference period. In addition, a current-enhanced circuit applied to the PLL can make settling behavior faster. The synthesizer is implemented in a 0.13-μm CMOS process, which provides the range from 4.6 GHz to 5.4 GHz with the phase noise of −106 dBc/Hz at 1-MHz offset. Combining the fast-locking techniques, the lock time of the synthesizer can be less than 13.2 μs and consume 39 mW from a 1.2-V power supply.     

A 1.8-GHz self-calibrated phase-locked loop with precise I/Qmatching

This paper describes a 1.8-GHz self-calibrated phase-locked loop (PLL) implemented in 0.35-μm CMOS technology. The PLL operates as an edge-combining type fractional-N frequency synthesizer using multiphase clock signals from a ring-type voltage-controlled oscillator (VCO). A self-calibration circuit in the PLL continuously adjusts delay mismatches among delay cells in the ring oscillator, eliminating the fractional spur commonly found in an edge-combing fractional divider due to the delay mismatches. With the calibration loop, the fractional spurs caused by the delay mismatches are reduced to -55 dBc, and the corresponding maximum phase offsets between the multiphase signals is less than 0.20. The frequency synthesizer PLL operates from 1.7 to 1.9 GHz and the closed-loop phase noise is -105 dBc/Hz at 100-kHz offset from the carrier. The overall circuit consumes 20 mA from a 3.0-V power supply     

A stabilization technique for phase-locked frequency synthesizers

A stabilization technique is presented that relaxes the tradeoff between the settling speed and the magnitude of output sidebands in phase-locked frequency synthesizers. The method introduces a zero in the open-loop transfer function through the use of a discrete-time delay cell, obviating the need for resistors in the loop filter. A 2.4-GHz CMOS frequency synthesizer employing the technique settles in approximately 60 /spl mu/s with 1-MHz channel spacing while exhibiting a sideband magnitude of -58.7 dBc. Designed for Bluetooth applications and fabricated in a 0.25-/spl mu/m digital CMOS technology, the synthesizer achieves a phase noise of -112 dBc/Hz at 1-MHz offset and consumes 20 mW from a 2.5-V supply.     

一种超高频RFID阅读器中的双环锁相环

采用GF 130 nm CMOS工艺,设计了一种低功耗低噪声的电荷泵型双环锁相环,该锁相环可应用于符合国际及中国标准的超高频射频识别阅读器芯片。通过对双环锁相环在带宽和工作频率上的合理设置,以及对压控振荡器中变容二极管偏置电阻及电荷泵中参考杂散的理论分析和优化设计,改进了锁相环电路功耗和噪声性能。仿真结果表明,该锁相环在输出工作频率范围为840~960 MHz时,功耗为31.21 mW,在距中心频率840.125 MHz频偏100 kHz处的相位噪声为 -108.5 dBc/Hz,频偏1 MHz处的相位噪声为 -132.3 dBc/Hz。与同类锁相环相比较,本文电路在噪声和功耗方面具有一定优势。     

A fast-hopping single-PLL 3-band MB-OFDM UWB synthesizer

This paper describes a 3-band (mode 1) multi-band-OFDM UWB synthesizer implemented in a 0.25-/spl mu/m SiGe BiCMOS process. The interference-robust, fast-hopping synthesizer uses one single-sideband (SSB) mixer for frequency shifting. A single phase-locked loop (PLL) generates the steady input signals for the SSB-mixer. Crucial in the design is a divide-by-5 frequency divider that generates quadrature signals at a frequency of 528 MHz. The 0.44 mm/sup 2/ fully integrated synthesizer consumes 52 mW from a 2.7 V supply. Out-of-band spurious tones are below -50 dBc, allowing co-operability with WLAN applications in the 2.4 GHz and 5 GHz range. The integrated phase noise is below 2/spl deg/ rms. The measured frequency transition time is well below the required 9.5 ns.