A two-path tree search algorithm for use with DFE

The two-path tree search is a detection algorithm that improves the performance of standard decision-feedback equalizer detectors by examining two likely paths through the decision tree. The method achieves about 1-dB improvement over standard decision-feedback equalization for typical magnetic recording channels used in hard disk drives. The implementation complexity is modest and is compared with other improved decision-feedback structures     

A simple precharged CMOS phase frequency detector

We propose a simple precharged CMOS phase frequency detector (PFD). The circuit uses 18 transistors and has a simple topology. Therefore, the detector, in a 0.8-μm CMOS process, works up to clock frequencies of 800 MHz according to SPICE simulations on extracted layout. Further, the detector has no dead-zone in the phase characteristic which is important in low jitter applications. The phase and frequency characteristics are presented and comparisons are made to other PFDs. The phase offset of the detector is sensitive to differences of the duty-cycle between the inputs. Mixed-mode simulations are presented of the lock-in procedure for a phase-locked loop (PLL) where the detector is used. Measurements on the detector are presented for a test-chip with a delay-locked loop (DLL) where the phase detection ability of the detector has been verified     

A CMOS motion detector system for pointing devices

A motion detector system uses an array of 93 photodiodes integrated along with processing circuits to detect the motion of a printed random pattern on a ball used in a pointing device application. It is based on the detection and tracking of spot edges passing over a matrix of pixels during the period between two light pulses. Motion in x and y directions is estimated by aggregating local information about moving edges over the photosensitive pixels. The 4.4×4.3 mm² chip detects the ball motion from 0 to 11.8 in/s with a resolution higher than 800 dpi over a 100-2000 mW/m² light-intensity range     

基于65 nm标准CMOS工艺的3.0 THz 探测器

基于Dyakonov和Shur等离子体波振荡原理设计并流片制备了一种采用65 nm标准CMOS工艺的3.0THz探测器,探测器包括贴片天线、NMOS场效应晶体管、匹配网络及陷波滤波器。探测器在室温条件下可达到526 V/W的响应率(Rv)和73 pW/Hz1/2的噪声等效功率(NEP)。采用该探测器和步进电机搭建了太赫兹扫描成像系统,获得了太赫兹源出射光斑的远场形状,光斑的半高宽(FWHM)为240μm;并对聚甲醛牙签和树叶进行了扫描成像实验,结果表明CMOS太赫兹探测器在成像领域有潜在的应用前景。     

基于CMOS工艺的双层非制冷热敏电阻型红外探测器

采用0.5μm标准CMOS工艺和微机械加工工艺,设计并制作了低成本双层非制冷热敏电阻型红外探测器。探测器采用隐藏桥腿式微桥结构,使用表面牺牲层技术实现,其中包括Al、W和Si3种牺牲层材料。CMOS工艺加工完成后,双层微桥结构的微机械加工过程只需进行湿法腐蚀即可,成本较低。对双层红外探测器的热性能和光电特性进行测试,其热导为1.96×10-5 W/K,热容为2.23×10-8 J/K,热时间常数为1.14ms。当红外辐射调制频率为10Hz时,双层红外探测器的电压响应率为2.54×104 V/W,探测率为1.6×108 cm·Hz1/2/W。     

采用CMOS太赫兹波探测器的成像系统

太赫兹波成像技术在生物医疗和安全检测等领域具有广阔的应用前景。针对新一代信息技术对便携式太赫兹波成像设备的需求,设计了基于CMOS太赫兹波探测器的成像系统。该系统包括一款CMOS太赫兹波探测器、片外模数转换器（ADC）、FPGA数字信号处理器、二位步进机、四个抛物面镜和太赫兹波辐射源等。CMOS太赫兹波探测器集成了片上贴片天线以及作为检波元件的NMOS晶体管,探测器由180 nm标准CMOS工艺制成。太赫兹波探测器的输出被片外模数转换器（ADC）采集并转换为数字信号,该数字信号被FPGA采集并传输到电脑上成像。所有上述元件均被装备在印刷线路板（PCB）上以减小系统体积。该系统实现了透射式太赫兹波扫描成像而无需斩波-锁相技术,并给出在860 GHz的太赫兹波照射下隐藏在信封内部金属的成像结果。     

A 300-MHz fixed-delay tree search-DFE analog CMOS disk-drive readchannel

A decision feedback equalizer (DFE) with digital error detection and correction implements a fixed-delay tree search with depth of 2. The disk-drive read waveform is first equalized to EPR4 for clock recovery and then re-equalized to the DFE target. A mostly analog implementation of this read channel in 0.6-μm CMOS implements a tapped delay-line forward filter with a cascade of track-and-hold circuits and variable transconductors. Using MTR (2,k) code, the compact read channel IC surpasses a conventional EPR4 read channel with Viterbi detector at user densities in the range 2.0-3.0     

应用于射频自动增益控制的CMOS数字校准RMS功率检测器

This paper presents the design and implementation of a digitally calibrated CMOS wideband radio frequency(RF) root-mean-square(RMS) power detector for high accuracy RF automatic gain control(AGC).The proposed RMS power detector demonstrates accurate power detection in the presence of process,supply voltage, and temperature(PVT) variations by employing a digital calibration scheme.It also consumes low power and occupies a small chip area.The measurement results show that the scheme improves the accuracy of the detector to better than 0.3 dB over the PVT variations and wide operating frequency range from 0.2 to 0.8 GHz.Implemented in a 0.18μm CMOS process and occupying a small die area of 263×214μm~2,the proposed digitally calibrated CMOS RMS power detector only consumes 1.6 mA in power detection mode and 2.1 mA in digital calibration mode from a 1.8 V supply voltage.     

CMOS design of the tree arbiter element

An asynchronous arbiter dynamically allocates a resource in response to requests from processes. Glitch-free operation when two requests arrive concurrently is possible in MOS technologies. Multiway arbitration using a request-grant-release-acknowledge protocol can be achieved by connecting together two-way arbiters (mutual exclusion and tree arbiter elements). We have devised a fast and compact design for the tree arbiter element which offers eager forward-propagation of requests. It compares favorably with a well-known design in which request propagation must wait for arbitration to complete. Our analysis and simulations also suggest that no performance improvement will be obtained by incorporating eager acknowledgment of releases. All of the designs considered in this paper are speed-independent, a formal property of a network of elements which can be taken as a positive indication of their robustness     

A bit-level systolic architecture for implementing a VQ tree search

A bit-level systolic array system for performing a binary tree Vector Quantization codebook search is described. This consists of a linear chain of regular VLSI building blocks and exhibits data rates suitable for a wide range of real-time applications. A technique is described which reduces the computation required at each node in the binary tree to that of a single inner product operation. This method applies to all the common distortion measures (including the Euclidean distance, the Weighted Euclidean distance and the Itakura-Saito distortion measure) and significantly reduces the hardware required to implement the tree search system.     

A two-path bandpass sigma-delta modulator with extended noiseshaping

A three-stage bandpass sigma-delta (ΣΔ) analog-to-digital converter has been designed specifically for operation at low oversampling ratios. In the proposed architecture, the center frequency of the third stage is shifted slightly from that of the first two stages to achieve more efficient noise shaping across the signal band. An experimental modulator based on the proposed topology has been integrated in a 0.25-μm CMOS technology and achieves a dynamic range of 75 dB with a maximum signal-to-noise-plus-distortion ratio (SNDR) of 70 dB when digitizing a 2-MHz signal band centered at 16 MHz. This circuit implements an f_s/4 bandpass architecture and thus operates at 64-MHz clock rate. It dissipates 110 mW from a 2.5-V supply, and its active area is 4 mm²     

基于CMOS的高响应度太赫兹探测器线阵

本文提出了一种基于CMOS 0.18μm工艺的改进型高响应度太赫兹探测器线阵,各探测像素单元由高增益片上天线、高耦合度差分自混频功率探测电路和集成电压放大器组成。其中,差分探测电路利用源极差分驱动场效应管的交叉耦合电容,将太赫兹差分信号耦合至场效应管的栅极与源极,增强场效应管沟道内自混频太赫兹信号的强度,实现高响应度。其次,该探测器配备高增益片上环形差分天线与集成电压放大器,可有效放大混频后的信号,进而提高系统信噪比,最终达到增强探测器响应度的目的。探测器1×3线阵系统充分利用CMOS工艺多层结构的特点,将电压放大器布置在天线地平面下方,提高了芯片面积的利用率,有效降低了制作成本,整个系统的面积为0.5 mm²。测试结果表明,当场效应管的栅极偏置为0.42 V时,该探测系统对0.3 THz辐射信号的电压响应度(Rv)最大可达到43.8 kV/W,对应的最小噪声等效功率(NEP)为20.5 pW/Hz^1/2。动态测试结果显示该探测器可对不同材质的隔挡物进行区分。     

An integrated analog CMOS Viterbi detector for digital magneticrecording

An analog Viterbi detector has been fabricated in a 2-μm double-poly p-well CMOS process. The detector takes a continuous-time analog input equalized to a class-IV partial response and produces the corresponding digital output at over 40 Mb/s while consuming less than 100 mW from a single 5-V supply. Measured performance is close to theoretical expectations and the performance is demonstrated to be robust with respect to changes in bias     

High-speed CMOS analog Viterbi detector for 4-PAM partial-responsesignaling

In this paper, a 1-Gb/s analog Viterbi detector based on a 4-PAM duobinary scheme is discussed with experimental results for a 0.25-μm CMOS implementation. This chip is the first analog integrated implementation of a reduced state sequence detector. Pipelining and parallel processing have been incorporated in this design for high-speed operation. Due to test equipment limitations, experimental results are given for 200-Mb/s operation while simulation results indicate a speed of 1 Gb/s. Power dissipation is 55 mW from a 2.5-V supply. The active area occupies 0.78 mm². Although a duobinary scheme has been the focus of this work for its application in optical links, this design can be readily modified or extended to other partial-response signaling schemes such as dicode and PR4     

CMOS/BiCMOS mixed design using tabu search

The problem of optimising mixed CMOS/BiCMOS circuits is solved using a tabu search. Only gates on critical sensitisable paths are considered. This strategy leads to a circuit speed improvement of >20% with a <3% increase in the overall circuit capacitance. Comparison and experimental results are presented     

A CMOS low-noise and low-power charge sampling integrated circuitfor capacitive detector/sensor interfaces

This paper describes the design and experimental results of a multichannel calibrationless charge sampling integrated circuit for capacitive detector/sensor interfaces. The integrated circuit incorporates multiple channels of sensitive charge preamplifiers, current/charge-mode amplifiers, pipelined analog storage cells, A/D converters, and static CMOS digital control circuitry. It is implemented in a 1.2 μm single-poly double-metal CMOS p-well technology. The power dissipation is 1 mW/channel. The input-referred equivalent noise charge (ENC) for a detector/sensor source capacitance of 30 pF and an integration time window of 128 ns is 1800 rms electrons. The input-referred channel-to-channel offset variation from chip to chip is only 292 rms electrons while the storage-cell-to-storage-cell offset variation is 142 rms electrons. The channel-to-channel gain variation from chip to chip is 1.6%     

一种长波红外光导探测器CMOS电路设计

CMOS 电路是高输入阻抗,而长波红外光导探测器是低阻抗,实现低阻抗红外光导探测器与CMOS 电路的良好匹配,是目前长波红外探测器高性能成像的关键技术。文中设计了一种能在低温下工作的低阻抗红外光导探测器CMOS 电路,差分放大器采用正负电源供电,在输入级采用桥式输入方式,该电路第一级采用1M的负反馈电阻实现信号放大,第二级放大采用正端放大方式,输入级、第一级放大、第二级放大均采用直接耦合方式。测试结果表明,该放大器与长波红外低输入阻抗光导探测器连接后能正常工作,总放大倍数大于1 万倍,3 dB 带宽大于4 kHz,等效输入电压噪声小于1.5 V,有效地解决了低阻抗光导探测器与高阻CMOS 电路的匹配问题。     

Pump-probe measurements of CMOS detector rise time in the blue

This paper proposes the use of shorter wavelengths and monolithic integration for chip-to-chip and on-chip optical communication. The promise of monolithic detectors for high-speed interconnection is demonstrated through experimental measurements and matching simulations. Responsivities >0.06 A/W and transit-time-limited response can be expected in the blue from planar p-i-n silicon-on-insulator (SOI) detectors.     

基于CMOS工艺的150 GHz正交外差探测器电路设计

传统太赫兹探测器仅能获取信号幅值信息,为此提出一种正交外差混频结构,可同时获得信号的幅值、相位和极化信息,有效提升探测器的灵敏度和信息量。该探测器基于40 nm互补金属氧化物半导体(CMOS)工艺,在传统吉尔伯特双平衡混频结构的开关级与跨导级之间串联电感,输出级联cascode中频放大器,进一步提高探测器响应电压。经过仿真优化,该探测器在 -50 dBm射频功率,0 dBm本振功率条件下,1 GHz中频信号的电压响应度为1 100 kV/W,噪声等效功率为26.8 fW/Hz^1/2,输出波形显示了良好的正交性。同时,设计了一个1∶8层叠式功分器用于分配本振功率,在150 GHz频率处,该功分器的插入损耗约为5 dB,四路差分输出信号的幅值差为0.8~1.2 dB,相位差为0.4°~1.7°。